JPH113597A - Non-volatile semiconductor memory, verifying method for writing data to non-volatile semiconductor, memory, and writing method for data to non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory in which the difference of read-out speed in selected memory cells can be made small as much as possible. SOLUTION: This device is provided with a memory cell having a drain connected electrically to a bit line, a source, a floating gate, and a control gate connected electrically to a word line, a sense amplifier comparing given plural reference potentials with a potential of a bit line, detecting data stored in a memory cell, and outputting output 1, 2, 3, and a logic circuit deciding storage data D1, D2 from logic of the output 1, 2, 3. In this case, discrimination for whether desired data is written or not for data read out by verify-read-out performed after writing data is performed at a time TJD being later than a time TOD at which data read out at the time of normal reading is outputted to the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly, to a non-volatile semiconductor memory device that stores a plurality of bits of data in one memory cell.

[0002]

2. Description of the Related Art A nonvolatile semiconductor memory device in which two bits of data are stored in one memory cell is disclosed in, for example, Japanese Patent Application Laid-Open No. Sho 59-121696 proposed by the present inventors.
No., etc., are disclosed. In the conventional example disclosed therein, three reference potentials are provided, and these stored reference potentials are compared with a potential from a memory cell by a sense amplifier to detect stored data.

FIG. 30 is a block diagram schematically showing a configuration of a nonvolatile semiconductor memory device, FIG. 31 is a diagram showing a relationship between a conventional reference potential and a bit line potential, and FIG. 32 is a diagram showing a conventional sense amplifier. FIG. 33 schematically shows a configuration diagram, and shows the relationship between the output of the sense amplifier and the stored data.

That is, 2-bit data is used to read data (bit line potential) from the memory cell MC shown in FIG. 30 at any position relative to the reference potentials 1, 2, and 3 shown in FIG. It is read by identifying whether it is. There are four types of 2-bit data combinations. The combination of these four types of data is stored by changing the amount of electrons injected into the floating gate of the memory cell into four types and changing the threshold voltage of the memory cell into four types in accordance with the amount of injection. . That is, if the bit line potential is lower than the smallest reference potential 1 among the reference potentials, data “00” is stored (threshold having the lowest threshold voltage), and the bit line potential becomes If it is higher than the largest reference potential 3, the data "11" is stored (the one with the highest threshold voltage). If the bit line potential is between the reference potential 1 and the reference potential 2, "01" is stored. Is stored (threshold voltage is the third highest), and if the bit line potential is between the reference potential 2 and the reference potential 3, "1"
0 ”data is stored (threshold voltage is the second highest).

As shown in FIG. 32, the sense amplifiers 101, 102, and 103, to which reference potentials 1, 2, and 3 are input, are used to identify combinations of the four types of data. Is compared with the bit line potential.

If the bit line potential is lower than the reference potentials 1, 2 and 3, as shown in FIG.
Outputs 1, 2, 2, which are the outputs of 102, 103, respectively.
3 are both "0", and this is detected by a logic circuit (not shown), and D1 =
"0" and D2 = "0" are output. Similarly, if the bit line potential is a potential between the reference potentials 1 and 2, the output 1 is "1" and the outputs 2 and 3 are both "0".
= "0", D2 = "1", and if the bit line potential is a potential between reference potentials 2 and 3, both outputs 1 and 2 are "1" and output 3 is "0". D1 = “1”, D2
= “0”, and if the bit line potential is higher than the reference potential 3, the outputs 1, 2, and 3 are both “1”.
= "1" and D2 = "1".

Writing data to a memory cell is performed by injecting electrons into a floating gate. Before writing data to a memory cell, the data in the memory cell is erased. At the time of data erasure, the control gate is set to 0 V, a high voltage is applied to the drain or the source, electrons are emitted from the floating gate, and an initial state is set. This erased state is a kind of writing and has the lowest threshold voltage, that is, D1 = "0" and D2 = "0".
Corresponds to the state in which the data is stored. Thereafter, other data is selectively written into the memory cells to be stored. To write data to the memory cell, a predetermined voltage is applied to each of the drain and the control gate of the memory cell,
The source is set to 0 V, a current is passed through the memory cell, and electrons are injected into the floating gate. Thus, data is written to the memory cells. After writing the data, the data is read from the memory cell (verify reading), and the writing and reading are repeated until the output results from the sense amplifiers 101, 102, and 103 match the data to be written. Then, when they match, writing is stopped. The determination as to whether they match may be made by reading data out of the integrated circuit and performing it externally, or may be performed inside the integrated circuit.

In such a conventional nonvolatile semiconductor memory device, according to data stored in a memory cell,
For example, the bit line potential can be set between the reference potential 1 and the reference potential 2. However, the write characteristics of the memory cells are different for individual memory cells. For this reason, the bit line potential after reading differs depending on the writing characteristics of the memory cell selected for reading. For this reason, conventionally, the reading speed of the selected memory cell varies greatly.

That is, in FIG. 31A, the bit line potentials 2, 3, and 4 are each represented by a single line, but actually, as shown in FIG. The line potentials 2, 3, and 4 were respectively distributed above and below the bit line potentials according to the selected memory cell, and had a variation "r". The data read speed depends on where the selected memory cell is in the distribution. For example, the reading speed is significantly different between the area (I) and the area (II).

Before writing data to a memory cell, the data in the memory cell is erased. When erasing data, the control gate is set to 0 V, a high voltage is applied to the source of the memory cell, and electrons are emitted from the floating gate to the source side of the memory cell. A high voltage is supplied from the source potential circuit shown in FIG. 5, and a reference potential (for example, 0 V) is supplied from the source potential circuit to the source of the memory cell when reading and writing data. In FIG. 34, I / O1 to I / O8
Respectively correspond to each bit of the output data (8 bits). The source potential circuit is provided commonly for a plurality of output bits. Data writing is performed by setting the source of a memory cell to a reference potential (for example, 0 V), applying a high voltage to a control gate and a drain of the memory cell, flowing a current to the memory cell, and injecting a charge from a channel region to a floating gate. Done. In data writing, data is simultaneously written to eight memory cells corresponding to each output bit. The amount of electrons injected into the floating gate is determined according to the potential of the control gate of the memory cell. That is, the higher the potential of the control gate, the greater the amount of injected electrons. For this reason, at the time of writing data, the potential of the control gate and the potential of the drain are set for the one having the highest threshold voltage after writing. Therefore, in order not to increase the injection of electrons into the memory cells for which the threshold voltage is set low,
The time for injecting charges is shortened, and writing and verify reading are repeatedly performed. Needless to say, in order to accurately set the threshold voltage to a predetermined value, it is better to shorten the time for injecting charges and gradually inject the charges, but this disadvantage in that the time required for writing data is long. There is. Further, in order to accurately set the threshold voltage of the memory cell, the potential of the control gate is changed in accordance with the set threshold voltage, that is, writing is performed from the memory cell whose threshold voltage is set low, and then the control gate is set. Has been increased by a predetermined value, and writing has been performed on a memory cell having the next highest threshold voltage. Also in this case, since writing is performed for each threshold voltage to be set, there is a disadvantage that the writing time is long.

[0011]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a nonvolatile semiconductor memory capable of minimizing a difference in reading speed between selected memory cells. It is an object of the present invention to provide a device and a method for verifying write data of a nonvolatile semiconductor memory device.

Another object of the present invention is to provide a nonvolatile semiconductor memory device capable of shortening a write time for writing data stored by a plurality of types of threshold voltages as much as possible, and a method of writing data in the nonvolatile semiconductor memory device. It is to provide a method.

[0013]

In order to solve the above problems and achieve the object, the present invention uses the following means.

(1) A nonvolatile semiconductor memory device according to the present invention comprises a row line, a column line, a drain and a source electrically connected to the column line, a charge storage portion, and an electric line connected to the row line. A memory cell having a control gate connected thereto and storing a plurality of bits of data by changing the amount of charge stored in the charge storage unit; and a memory cell stored in the memory cell using a plurality of predetermined reference potentials. A sense amplifier for detecting data, and after writing data to the memory cell, reading is performed to check the charge accumulation state of the charge accumulation unit after the writing, and it is determined that desired data has been written by the reading. When it is determined that the writing is completed, when the reading determines that the desired data has not been written, it is determined that the desired data has been written. Program means that repeats the writing and the reading until the reading is performed.The determination as to whether or not desired data has been written, which is performed at the time of reading by the programming means, is performed by reading from the memory cell at the time of normal reading. This is performed at a time later than the time at which the output data is output to the outside.

(2) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device described in the above (1), wherein reading by the program means is performed by using the sense amplifier. It is.

(3) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device described in the above (1) or (2), wherein the plurality of reference potentials are different from those of the normal read. At the time of the reading by the program means, the read voltage is set higher than the corresponding reference voltage.

(4) The non-volatile semiconductor memory device according to the present invention is the non-volatile semiconductor memory device according to any one of (1) to (3), wherein the data of a plurality of bits is at least two bits. Minute binary data, wherein the plurality of reference potentials are at least three reference potentials having different potentials respectively, and when the storage data of the memory cell is a first combination of binary data of 2 bits. A threshold voltage of the memory cell is set such that a potential of the column line at the time of normal reading is lower than a reference potential of the lowest potential among the three reference potentials; When the stored data is a second combination of binary data of 2 bits, the potential of the column line at the time of normal reading is the same as the lowest reference potential among the three reference potentials. The threshold voltage of the memory cell is set so as to be a potential between an intermediate potential of the three reference potentials, and the storage data of the memory cell is a binary data of two bits. In the case of a combination of three, the potential of the column line at the time of normal reading is a reference potential of an intermediate potential among the three reference potentials and a reference potential of the highest potential among the three reference potentials. The threshold voltage of the memory cell is set so as to be a potential between the column line and the column line at the time of normal reading when the storage data of the memory cell is the fourth combination of binary data of 2 bits. The threshold voltage of the memory cell is set so that the potential of the memory cell becomes higher than the highest reference potential of the three reference potentials, and at the time of writing data to the memory cell, The third When writing data mating seen, when the voltage supplied to the row lines than when writing a second combination of the data set to a high value, and writes the data of the fourth combination,
The voltage supplied to the row line is controlled to be set to a higher value than when the data of the third combination is written.

(5) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device described in (3) above, wherein the potential of the column line corresponds to the time of the reading by the program means. When the potential becomes higher than the reference potential, writing of data to the memory cell is stopped.

(6) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device according to the above (1), wherein at the time of writing data to the memory cell,
The voltage supplied to the control gate of the memory cell is controlled so as to change according to the write data.

(7) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device according to the above (6), wherein the data is written to the memory cell corresponding to the write data. The amount of change in the voltage supplied to the control gate of the memory cell is either a difference between the threshold voltages of the set memory cells or a difference between the corresponding reference potentials.

(8) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device according to any one of the above (1) to (6), wherein the program means stores data in the memory cell. Writing is performed simultaneously on a plurality of memory cells connected to the same row line. When at least two different threshold voltages are set in the plurality of memory cells, the lower threshold voltage corresponds first. A threshold voltage is set for the memory cell, and after this setting, a threshold voltage is set for the memory cell corresponding to the higher threshold voltage, and a threshold voltage is set for the plurality of memory cells corresponding to the lower threshold voltage. When the charge is injected into the charge storage section of the corresponding memory cell, the charge is simultaneously injected into the charge storage section of the memory cell set to the higher threshold voltage. It is intended to control to so that.

(9) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device described in (2) above, wherein data is read by the program means,
When data is output to the outside, the charge / discharge time of the external output terminal is set longer than during normal reading.

(10) The method for verifying write data of a nonvolatile semiconductor memory device according to the present invention comprises the steps of (a) writing write data of a desired value into a rewritable nonvolatile memory cell; Writing data written in the memory cell to a bit line; (c) comparing a bit line potential after the writing data is read to the bit line with a reference potential; and (d) a result of the comparison. (E) repeating the steps (a) to (d) until the desired write data is written, wherein (e) The procedure d) is performed at the time of normal reading after a lapse of a time at which read data is output to the outside.

(11) The method of verifying write data of a nonvolatile semiconductor memory device according to the present invention comprises the steps of (a) writing write data of a desired value into a rewritable nonvolatile memory cell; (C) comparing the bit line potential after the write data is read out to the bit line with a reference potential, and (d) comparing the result of the comparison with the result of the comparison. (E) repeating the steps (a) to (d) until the desired write data is written, where (d) The speed at which write data is output to the outside in the procedure of (3) is lower than the speed at which read data is output to the outside during normal reading.

(12) In a nonvolatile semiconductor memory device according to the present invention, a read circuit for reading out storage data stored in a rewritable nonvolatile memory cell to a bit line; A comparison circuit for comparing the bit line potential after being read to the reference potential with a reference potential, and an output circuit for outputting detection data detected based on the result of the comparison to the outside, wherein the output circuit is an integrated circuit. First and second insulated gate FETs connected in series between power supply voltages inside a circuit and electrically connecting an output to an external terminal
Wherein the first, which is performed according to the detection data,
The charge / discharge speed of charging one gate and discharging the other gate of the second insulated gate FET is made slower at the time of reading for checking write data performed after writing than at the time of normal reading. The time required for charging / discharging the external terminal is set to be longer than at the time of reading for checking the write data than at the time of normal reading.

(13) In the data writing method for a nonvolatile semiconductor memory device according to the present invention, the first reference potential and the first
At least three first, second, and third data are distinguished by at least two reference potentials of a second reference potential at a level different from that of the first reference potential, and the first data is stored by a first threshold voltage. And storing the second data with a second threshold voltage higher than the first threshold voltage, storing the third data with a third threshold voltage higher than the second threshold voltage, A data writing method for a nonvolatile semiconductor memory device having a plurality of data rewritable nonvolatile memory cells stored by at least three threshold voltages, wherein the first memory is set to the first threshold voltage Setting the first threshold voltage to a cell, applying a first write voltage to a gate of a second memory cell set to the second threshold voltage, and applying the first write voltage to the second memory cell. Threshold of 2 A voltage between the second threshold voltage and the third threshold voltage, and a voltage between the first reference potential and the third reference voltage. The second threshold voltage is applied to the third memory cell by applying a second write voltage whose voltage is higher than the first write voltage by an amount corresponding to one of the differences from the second reference potential. This is for setting the voltage.

(14) The nonvolatile semiconductor memory device of the present invention stores the first data with the first threshold voltage,
Is stored by a second threshold voltage higher than the first threshold voltage, third data is stored by a third threshold voltage higher than the second threshold voltage, and at least three threshold voltages are used. A memory cell array in which a plurality of non-volatile memory cells that can store and rewrite data are integrated, and a voltage applied to a column line of the memory cell array is controlled based on the write data, and the write data is written to the memory cells. A write circuit, detecting whether the write data is the second data or the third data,
When the write data is the second data, a voltage applied to a row line of the memory cell array is a first write voltage, and when the write data is the third data, a voltage applied to the row line is And the first writing voltage according to one of a difference between the second threshold voltage and the third threshold voltage and a difference between the first reference potential and the second reference potential. A write data detection circuit that outputs a control signal to be a second write voltage whose voltage has been increased.

(15) In the data writing method for a nonvolatile semiconductor memory device according to the present invention, the first data is stored at a first threshold voltage, and the second data is stored at a second voltage higher than the first threshold voltage. And a plurality of data rewritable nonvolatile memory cells that store third data with at least three threshold voltages of a third threshold voltage higher than the second threshold voltage. A method for writing data to a plurality of memory cells simultaneously in a nonvolatile semiconductor memory device, wherein the first threshold voltage is set in a first memory cell set to the first threshold voltage. After that, the second threshold voltage set to the second threshold voltage
A first write voltage is applied to each of the gates of the memory cells and the gate of the third memory cell set to the third threshold voltage, and the threshold voltage of each of the second and third memory cells is changed. , From the first threshold voltage to the second
After setting a second threshold voltage in the second memory cell, the threshold voltage is shifted from the first threshold voltage to the second threshold voltage. A second write voltage is applied to a gate of a third memory cell set to a third threshold voltage, and a third threshold voltage is set to the third memory cell.

(16) A data writing method for a nonvolatile semiconductor memory device according to the present invention is the method described in the above (15), wherein the first, second and third data are each a first data. The second write voltage is distinguished by at least two reference potentials, a reference potential and a second reference potential at a level different from the first reference potential, wherein the second write voltage is different from the first write voltage by the second write potential. The voltage is increased by an amount corresponding to one of a difference between a threshold voltage and the third threshold voltage and a difference between the first reference potential and the second reference potential.

(17) The method of writing data in a nonvolatile semiconductor memory device according to the present invention may be arranged as described in (15) or (1) above.
6) The method according to 6), wherein when at least one of the second and third data does not exist in the write data for the plurality of memory cells to which data is simultaneously written, the non-existent data is written. Is omitted.

(18) The nonvolatile semiconductor memory device of the present invention stores the first data with the first threshold voltage,
Is stored by a second threshold voltage higher than the first threshold voltage, and the third data is stored by at least three threshold voltages of a third threshold voltage higher than the second threshold voltage. A memory cell array in which a plurality of data rewritable nonvolatile memory cells are integrated, a voltage applied to a column line of the memory cell array based on write data, and the write data is written to the memory cell. A write circuit, and, for each of the write data input to the plurality of write circuits, detecting whether the second data or the third data,
When there is at least one second data in the write data, a row line of the memory cell array is set to a first write voltage in order to write the second data, and the third data is one in the write data. When the third
The row line of the memory cell array is set to a second write voltage in order to write the data, and when at least one of the second and third data does not exist in the write data, the writing of the nonexistent data is omitted. And a write control circuit for outputting a control signal to be performed.

(19) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device according to the above (18), wherein the first, second, and third data are each a first data. The second write voltage is distinguished by at least two reference potentials, a reference potential and a second reference potential at a level different from the first reference potential, wherein the second write voltage is different from the first write voltage by the second write potential. The voltage is increased by an amount corresponding to one of a difference between a threshold voltage and the third threshold voltage and a difference between the first reference potential and the second reference potential.

(20) A nonvolatile semiconductor memory device according to the present invention includes row lines and column lines, is arranged in a matrix,
Each has a drain, a source, a floating gate, and a control gate, has memory cells that store a plurality of bits of data by storing different amounts of electrons in the floating gate, and the control gate of the memory cells in the same row is A memory cell array commonly connected to one of the row lines and a drain of the memory cell in the same column commonly connected to one of the column lines, and data to the memory cell injecting charge into the floating gate At the time of writing, corresponding to the data to be stored,
Source potential setting means for varying the potential of the source.

(21) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device described in (20) above, wherein the source potential setting means has a drain connected to a source of the memory cell, The source is a transistor connected to a reference potential, and the resistance value changes in accordance with the stored data when writing the data.

(22) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device according to the above (20), wherein a plurality of bits of data stored in the memory cell are data of different addresses. There is something.

(23) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device according to (20), wherein a plurality of bits of data stored in the memory cell are a plurality of output bits. It is something that is.

(24) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device according to the above (20), wherein a plurality of bits of data stored in the memory cell have the same address. Have

(25) A nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device described in (20) above, wherein a plurality of the memory cell arrays are provided.

(26) A nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device described in (25) above, wherein the plurality of memory cell arrays have the same bit output data. is there.

(27) A nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device described in (25), wherein data is simultaneously written in the plurality of memory cell arrays.

(28) A nonvolatile semiconductor memory device according to the present invention has a drain, a source, a floating gate, and a control gate, and stores a plurality of bits of data by storing different amounts of electrons in the floating gate. The memory cells are arranged in a matrix, the control gates of the memory cells in the same row arranged in the matrix are commonly connected to one of a plurality of row lines, and the drains of the memory cells in the same column are plural. And a memory cell array including a plurality of memory cell blocks formed by commonly connecting the sources of the memory cells, and a memory cell array provided for each memory cell block. A source potential setting that varies the potential of the source in accordance with the data to be stored when writing data to the memory cell into which the data is to be injected. It is intended to and a stage.

(29) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device according to the above (28), wherein a plurality of bits of data stored in the memory cell are data of different addresses. It is something that is.

(30) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device according to the above (28), wherein a plurality of bits of data stored in the memory cell are a plurality of output bits. It is something that is.

(31) A nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device described in (28) above, wherein a plurality of the memory cell arrays are provided.

(32) A nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device according to (31), wherein the corresponding memory cell blocks of the plurality of memory cell arrays are the same. This is bit output data.

(33) A nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device described in (28), wherein data is simultaneously written in a plurality of memory cell blocks in the memory cell array. Things.

(34) A nonvolatile semiconductor memory device according to the present invention includes row lines and column lines, is arranged in a matrix,
A plurality of bits of data are stored by varying the threshold voltage according to the amount of charge in the charge storage unit, each having a drain, a source, a memory cell having the charge storage unit and a control gate, and The control gates of the memory cells are commonly connected to one of the row lines, and the memory cells in the same column are connected to the same row line as a memory cell array commonly connected to one of the column lines. When simultaneously writing data to at least two of the connected memory cells and setting at least two different threshold voltages to the at least two memory cells, the memory cells corresponding to the lower threshold voltage first After this setting, a threshold voltage is set for the memory cell corresponding to the higher threshold voltage, and the charge storage of the memory cell corresponding to the lower threshold voltage is set. When injecting electric charges into the charge storage portion of the corresponding memory cell in order to inject charge into parts,
Program means for controlling so as to simultaneously inject electric charge into the electric charge accumulating portion of the memory cell set to the higher threshold voltage.

(35) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device described in (34) above, wherein the program means, when writing data to the memory cell, A corresponding voltage is supplied to a control gate of the memory cell.

(36) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device according to the above (34) or (35), further comprising data erasing means, After setting the storage data of the memory cell to a predetermined value, the program means selectively writes data to the memory cell.

(37) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device according to the above (34), wherein the program means is provided for the memory cell corresponding to a lower threshold voltage. When setting a threshold voltage, a first voltage is supplied to the row line, and a charge storage unit of the memory cell set to the lower threshold voltage and a charge storage unit of the memory cell set to the higher threshold voltage are set. Simultaneously injecting charges into the charge storage unit, after setting the threshold voltage of the memory cell corresponding to the lower threshold voltage, when setting a threshold voltage to the memory cell set to the higher threshold voltage, Supplying a second voltage having a voltage value higher than the first voltage to the row line, injecting a charge into a charge storage portion of the memory cell set to the higher threshold voltage, Against voltage It is for setting the threshold voltage to the memory cells.

(38) A nonvolatile semiconductor memory device according to the present invention includes row lines and column lines, is arranged in a matrix,
A plurality of bits of data are stored by varying the threshold voltage according to the amount of charge in the charge storage unit, each having a drain, a source, a memory cell having the charge storage unit and a control gate, and A memory cell array unit including a plurality of memory cell arrays in which the control gates of the memory cells are commonly connected to one of the row lines, and the memory cells in the same column are commonly connected to one of the column lines; An output circuit provided corresponding to the plurality of memory cell arrays, for outputting storage data of the memory cells to the outside; and the memory cells in the plurality of memory cell arrays corresponding to write data to the memory cells. When simultaneously writing data to the memory cells of the plurality of memory cell arrays and setting at least two different threshold voltages to the memory cells in the plurality of memory cell arrays, A threshold voltage is set to the memory cell corresponding to the value voltage, and after this setting, a threshold voltage is set to the memory cell corresponding to the higher threshold voltage, and a threshold voltage is set to the memory cell corresponding to the lower threshold voltage. When the charge is injected into the charge storage section of the corresponding memory cell to set the voltage, control is performed so that the charge is simultaneously injected into the charge storage section of the memory cell set to the higher threshold voltage. Program means.

(39) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device according to the above (38), wherein the corresponding row lines of the plurality of memory cell arrays are connected to each other. It is.

(40) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device according to the above (38) or (39), wherein the program means is
When writing data to the memory cell, a voltage corresponding to the data to be written is supplied to a control gate of the memory cell.

(41) The non-volatile semiconductor memory device according to the present invention is the non-volatile semiconductor memory device according to any one of the above (38) to (40), and wherein the program means comprises a lower threshold voltage. When a threshold voltage is set for the memory cell corresponding to the first threshold voltage, a first voltage is applied to the control gate of the memory cell corresponding to the lower threshold voltage and the memory cell corresponding to the higher threshold voltage. Supplying the control gate and simultaneously injecting charge into the charge storage portion of the memory cell set to the lower threshold voltage and the charge storage portion of the memory cell set to the higher threshold voltage; When setting a threshold voltage for the memory cell corresponding to the higher threshold voltage after setting the threshold voltage of the memory cell corresponding to the threshold voltage of the
A second voltage having a voltage value larger than the voltage of the memory cell is supplied to the control gate of the memory cell corresponding to the higher threshold voltage, and the charge storage portion of the memory cell that is set to the higher threshold voltage is Injecting a charge and setting a threshold voltage in the memory cell corresponding to the higher threshold voltage.

(42) The nonvolatile semiconductor memory device according to the present invention is the nonvolatile semiconductor memory device described in the above (38) to (41), further comprising a data erasing means. After setting the storage data of the memory cell to a predetermined value, the program means selectively writes data to the memory cell.

According to the present invention, a nonvolatile semiconductor memory device capable of minimizing a difference in read speed between selected memory cells, a method of verifying write data of the nonvolatile semiconductor memory device, and a plurality of types of threshold voltages A nonvolatile semiconductor memory device capable of shortening the writing time for writing data stored by
And a method of writing data in a nonvolatile semiconductor memory device.

[0057]

BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment FIG. 1 is a waveform chart showing the operation of the nonvolatile semiconductor memory device according to the first embodiment, and FIG. 2 is a diagram showing the word line potential at the time of data writing in the nonvolatile semiconductor memory device according to the first embodiment. FIGS. 3A and 3B are diagrams showing the relationship between the reference potential and the bit line potential of the nonvolatile semiconductor memory device according to the first embodiment, respectively, and FIG. 4 is a diagram showing the nonvolatile semiconductor memory device. FIG. 5 is a schematic diagram showing a sense amplifier included in the nonvolatile semiconductor memory device according to the first embodiment, and FIG. 6 is a diagram showing a relationship between an output of the sense amplifier and stored data. It is.

First, the basic configuration of the memory according to the first embodiment will be described with reference to FIGS.

As shown in FIG. 4, a plurality of memory cells M
Memory cell array 1 in which C are arranged in a matrix
There is. Each of the memory cells MC has a drain D, a source S, a floating gate FG, and a control gate CG.
The drain D of the memory cell MC is a bit line (column line) BL
The source S is connected to the source line SL and the control gate C
G is connected to a word line (row line) WL. The floating gate FG is formed, for example, in a gate insulating film that insulates the control gate CG from the channel. The memory cell MC is basically an insulated gate FET, and changes its threshold voltage according to the charged state of the floating gate FG. The memory cell MC stores data in association with the threshold voltage.
The memory cell array 1 shown in FIG. 4 is generally called a NOR type. In the NOR type, a plurality of memory cells MC are integrated on the basis of connecting memory cells MC one by one between a bit line BL and a source line SL.

The word line WL is for selecting a row of the memory cell array 1. The selection is made by the row decoder 2. The row decoder 2 decodes a row address signal (not shown) and determines a selected word line WL.

The bit line BL transmits data of the memory cell MC electrically connected to the selected word line WL as an electric signal outside the memory cell MC, for example, at the time of reading data. The column of the memory cell array 1 is specified by the column decoder 3. The column decoder 3 decodes a column address signal (not shown) and determines a column to be read and designated. The bit line BL belonging to the designated column electrically connects the memory cell MC to the readout circuit 5 via the column selector 4. The memory cell MC connected to the read-related circuit 5 changes the potential of the output node 6 of the read-related circuit 5 via the bit line BL. The amount of change in the potential of the output node 6 changes according to the conduction state of the memory cell MC, that is, the amount of drain current that can flow through the memory cell MC. The amount of the drain current changes according to the threshold voltage of the memory cell MC.

In the first embodiment, the memory cell MC
Are provided in four ways, and one memory cell MC has two threshold voltages.
Bit data can be written.

Read data (bit line potential) output to output node 6 is applied to sense amplifiers 11 and 1 shown in FIG.
2 and 13 respectively. Sense amplifier 11, 1
2, 13 have reference potentials 1, 2, 2,
3 are given. The sense amplifiers 11, 12, and 13 compare the bit line potential with reference potentials 1, 2, and 3, respectively. Thus, the bit line potentials are changed to the reference potentials (READ reference potential, VRFY reference potential) 1, 2, 3 shown in FIG.
, Where it is located. As shown in FIG. 6, the sense amplifiers 11, 12, and 13 output outputs 1, 2, and 3, respectively, having four combinations according to the bit line potential. Thus, data of 2 bits is identified.

In the first embodiment, the reference potential 1 and the reference potential 1 are set at the time of normal reading and at the time of verify reading for checking whether or not predetermined data has been written after writing data to the memory cell. 2 and 3 are mutually changed.

In FIG. 3A, the reference potentials 1, 2, and 3 at the time of the verify read are “VRFY reference potentials 1, 2, 3”.
It is shown as The reference potentials 1, 2, and 3 at the time of normal reading are indicated as "READ reference potentials 1, 2, and 3".

As shown in FIG. 3A, in the first embodiment, the VRFY reference potential 1 is set to a potential lower by a predetermined value than an intermediate potential between the READ reference potential 1 and the READ reference potential 2. Is set. This can be expressed as follows.

[VRFY reference potential 1] = [(READ reference potential 1)
+ READ reference potential 2) / 2]-[α] Here, α is a predetermined positive value. Like VRFY reference potential 1, VRFY reference potential 2 is a potential intermediate between READ reference potential 2 and READ reference potential 3. Is set to a potential lower by a predetermined value. VRFY reference potential 3
Is set to a potential higher than the READ reference potential 3 by a predetermined value. Thus, in the first embodiment, each of the VRFY reference potentials 1, 2, and 3 is set to a potential higher than the READ reference potentials 1, 2, and 3, respectively.

Further, in the first embodiment, the determination of read data at the time of verify read after write is
At a time when data is output to the outside, which is later than a normal time, the data is read out inside the integrated circuit or by reading out the data to the outside. For example, as shown in FIG.
At the time of normal read, the read data at the time of the verify read is determined at a time TJD later than the time TOD when the data D1 of “0” is output to the outside. FIG. 1 shows an example in which the data D1 and D2 are “01”. The determination of the read data is as shown in FIG.
The write cycle is performed at the "strobe" time.

The later the strobe, the better.
This is because, as the strobe time is later, the data to be determined is more stable in DC current. However, if it is too slow, the entire writing time will be long. Therefore, the optimum value may be set to an allowable value in consideration of the relationship with the write characteristics of the memory cell. For example, the time from time TOD to time TJD for judging data is set relatively long according to the write characteristics of the memory cell, or when the write characteristics of the memory cell are excellent or improved, the time is set accordingly. It is also possible to shorten it.

At present, to give a preferred example of the time TJD, the time TMSL at which the memory cell is selected
From 1 μsec, for example. On the other hand, from time TMSL to time TOD, for example, 100 ns
c later. Thus, from time TOD to time TJD
At present, 900 nsec is a preferable value.

According to the nonvolatile semiconductor memory device of the first embodiment, the determination of read data at the time of verify read after writing is performed by outputting the data to the outside.
At a time later than the normal time, the reading is performed inside the integrated circuit or outside the data. Therefore, the determination of the read data can be performed at a time when the read data is somewhat stable in terms of DC current. By judging the read data at a time when the read data is stable in terms of DC current, the bit line potential and the reference potential are determined.
The data can be determined at the time when there is a slight difference, that is, when the bit line potential slightly exceeds the reference potential. Therefore, as shown in FIG. 3B, the variation “r” of the bit line potential is smaller than the conventional variation “r”, and the variation of the reading speed in the selected memory cell is reduced as much as possible. be able to.

In the nonvolatile semiconductor memory device according to the first embodiment, in which the variation in the read speed is small, for example, the characteristic failure due to the expected value of the read speed of the nonvolatile semiconductor memory device not reaching the expected value is reduced, and the yield is improved. Further, a small variation in the read speed means that the read speed of the slowest cell is increased, so that the read speed can be further accelerated.

In the first embodiment, if the writing time for one time, for example, the writing pulse width φp shown in FIG. 2 is made as small as possible and writing is performed little by little, the potential of the bit line in each memory cell can be reduced. Can be further reduced.

Second Embodiment In the first embodiment, when it is determined whether or not desired data has been written outside the integrated circuit chip,
It is desirable that power supply noise is also considered. In the first embodiment, at the time of verify reading, data is determined when the bit line potential becomes slightly higher than the reference potential in order to minimize the variation “r” of the bit line potential. This means that the difference between the bit line potential and the reference potential is extremely small.

When data is output to the outside, a charge / discharge current from an output buffer flows into a power supply line inside the integrated circuit. When the charge / discharge current flows into the internal power supply line, the power supply voltage inside the integrated circuit fluctuates. When the internal power supply voltage fluctuates, the bit line potential and the reference potential change. For example, the bit line potential may fluctuate so as to be lower than the reference potential.

If the bit line potential fluctuates so as to be lower than the reference potential due to the fluctuation of the internal power supply voltage, even if the desired data is actually written,
It is determined that the data has not been written, and the writing is repeated. Such writing is an operation of giving extra writing to a memory cell. Therefore, according to the first embodiment, the variation “r” in the bit line potential reduced is
It may grow again.

In view of such circumstances, in the second embodiment, when data is output to the outside and the verify read is determined, the power supply voltage is not largely changed at the time of data output. .

For this reason, in the second embodiment, when outputting data to the outside, the change of the output data is moderated.
That is, at the time of normal reading, data is rapidly output to the outside from the output buffer to maintain high-speed data reading, while at the time of verify reading, data is gradually output from the output buffer to the outside. This makes it possible to reduce fluctuations in power supply inside the integrated circuit at the time of verify reading.

FIG. 7 is a diagram showing an output buffer of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.
8 is a circuit diagram of the output buffer shown in FIG. 7, FIG. 9 is a diagram showing the level of a signal input to the output buffer shown in FIG. 8 for each mode, and FIGS. FIG. 9 is a waveform chart showing an output waveform at the time of data output of the nonvolatile semiconductor memory device according to the second embodiment.

Hereinafter, the second embodiment will be described using a 2-bit output buffer as an example.

As shown in FIG.
There is a non-volatile semiconductor storage device chip 21 packaged by the company. An output buffer 22 is provided on the chip 21 for each of the data D1 and D2. The output buffer 22 receives the detection data (internal D1, D2),
Verify signals VR, / VR (leading "/" indicates inverted signal, so-called "bar"), output enable signals OE, / OE (leading "/" indicates inverted signal, so-called "bar") The detection data is output to the outside of the integrated circuit chip 20 via the pad 23 in accordance with (a).
Here, the detected data is the sense amplifier 1 shown in FIG.
The levels of outputs 1, 2, 3 from 1, 12, 13 are replaced with data D1, D2 by a logic circuit (not shown). In the second embodiment, the data D1, D
2, the data up to the input to the output buffer 22 are referred to as “internal D1” and “internal D2”, and the data output from the output buffer 22 are referred to as “D1” and “D2”.

Next, an example of a circuit of the output buffer will be described with reference to FIGS.

In the circuit example of the output buffer 22 shown in FIG. 8, as shown in FIG. 9, during normal reading, the signal OE is set to "1" and the inverted signal / OE is set to "0".
Further, the signal VR is "0", and the inverted signal / VR is "1".
To be. Therefore, the P-channel type MOSF shown in FIG.
ET (hereinafter, PMOS) 33 and N-channel type MOS
The FET (hereinafter, NMOS) 41 is turned off, and the NMOS 3
5, 38 and the PMOS 39, 42 are turned on.

If the detection data is "1", the NMOS
34 and 37 are turned on, and the PMOS 36 is turned off. Therefore, the gates of the PMOS 31 are discharged to the “0” level by the NMOSs 34 and 35 and the NMOSs 37 and 38, the PMOS 31 is turned on, and data “1” is output to the outside. Also, the NMOS 44 turns on and the PMOS 4
Since 0 and 43 are turned off, the gate of the NMOS 32 is also discharged to the “0” level, and the NMOS 32 is turned off.

As described above, the output buffer 22 shown in FIG.
In normal reading, when the detection data is at the “1” level, the gate of the PMOS 31 is connected to the NMOSs 34 and 3.
5 and two current paths, NMOS 37 and 38, are discharged to "0" level. Therefore, the PMOS3
The 1 gate quickly goes to "0" level. Therefore, as shown in FIG. 10A, the output buffer 22
An external output terminal, for example, an outer lead terminal 24 shown in FIG.

When the detection data is at "0" level, the NMOSs 34 and 37 are turned off and the PMOS 36 is turned on. Therefore, the PMOS 36 causes the PMOS 31
Is charged to the “1” level, and the PMOS 31 is turned off. Further, the NMOS 44 is turned off, and the PMOS 40,
Since 43 is turned on, the gate of the NMOS 32 is also charged to the “1” level, and the NMOS 32 is turned on.

As described above, at the time of normal reading, when the detection data is at the “0” level, the gate of the NMOS 32 is
Since the two current paths of the PMOSs 39 and 40 and the PMOSs 42 and 43 are rapidly charged to the “1” level, the gate of the NMOS 32 quickly becomes the “1” level. Therefore, as shown in FIG. 10B, the output buffer 22 rapidly discharges the lead terminal 24 through the NMOS 32.

On the other hand, at the time of verify reading, the signal OE remains at "1" and the signal / OE remains at "0", but the signal VR is set to "1" and the signal / VR is set to "0". . Therefore, PMOS 33, NMOS 41, NMOS 3
8, the PMOS 42 is turned off, and the NMOS 35, P
The MOS 39 turns on.

In the verify reading, if the detected data is at the “1” level, the NMOSs 34 and 37 are turned on,
The PMOS 36 turns off. At this time, since the NMOS 38 is turned off, the gate of the PMOS 31 is discharged to the “0” level by the NMOSs 34 and 35, the PMOS 31 is turned on, and “1” level data is output to the outside.

As described above, at the time of the verify read, when the detection data is at the "1" level, the gate of the PMOS 31 is connected to the NMOS 34, 3 unlike the normal read.
5 only one current path discharges to the "0" level. For this reason, the gate of the PMOS 31 is gradually discharged to the “0” level, and the conduction resistance of the PMOS 31 gradually decreases. Therefore, as shown in FIG. 10C, the lead terminal 24 is slowly charged through the PMOS 31.

When the detection data is at "0" level, the NMOS 44 is turned off and the PMOSs 40 and 43 are turned on, but since the PMOS 42 is off, the PMOSs 39 and 4 are turned off.
Through 0, the gate of the NMOS 32 is charged to the “1” level.

As described above, at the time of verify reading, even when the sensed data is at the "0" level, unlike the case of normal reading, the gate of the NMOS 32 is connected to the PMOS 39,4.
Only one current path of 0 is charged to the “1” level, and the gate of the NMOS 32 gradually becomes the “1” level. Therefore, as shown in FIG.
, The lead terminal 24 is gradually discharged.

In the second embodiment, the charge or discharge of the gate of the transistor for outputting data to the outside is set to be slower at the time of verify reading than at the time of normal reading. ing. As a result, the output buffer 22 becomes more
At the time of verify reading, the charging and discharging of the lead terminals 24 are performed more slowly, and the change in the current flowing into the power supply lines Vs and Vc during the charging and discharging of the lead terminals 24 can be made smaller than at the time of normal reading. . Therefore, at the time of verify reading, the fluctuation of the power supply voltage inside the integrated circuit becomes small, and even if the potential difference between the bit line potential and the reference potential is small, as shown in FIG.
2, 13 can accurately detect data.

Third Embodiment In the first and second embodiments, when writing data to a memory cell, a predetermined write voltage Vpp is applied to a control gate of the memory cell. This voltage Vpp is "0
The value is constant when any of the data “1”, the data “10”, and the data “11” is written.

On the other hand, in the third embodiment, when writing data to a memory cell, the value of the voltage applied to the control gate of the memory cell is changed according to the data to be written.

Before describing the third embodiment, writing of data to a memory cell and erasing of data will be described with reference to FIG.

FIG. 11A is a schematic view of a cross section of a memory cell having no offset gate portion, and FIG.
FIG. 3 is a schematic view of a cross section of a memory cell of a type having an offset gate portion.

When erasing data from a memory cell, the potential of the control gate CG connected to the word line is set to 0V
In the cell shown in FIG. 2A, a high voltage is applied to either the drain D or the source S, and in the cell shown in FIG. 2B, a high voltage is applied to the drain D. As a result, electrons are emitted from the floating gate FG.

At the time of such erasing, in the cell shown in FIG. 9A, the threshold voltage of the memory transistor section MT must be prevented from becoming a negative value, which complicates the control. In the memory transistor unit MT, the control gate CG
This portion is capacitively coupled to the channel CH via the floating gate FG.

On the other hand, the cell shown in FIG. 10B has the offset gate portion OG, so that the threshold voltage of the memory transistor portion MT may be a negative value. There is an advantage that the control at the time of erasing is simpler than the cell shown. The offset gate OG is
Unlike the memory transistor section MT, the control gate CG
Are capacitively coupled to the channel CH without passing through the floating gate FG.

However, the ease of miniaturization of the cell is higher in the cell shown in FIG. 2A than in the cell shown in FIG. 2B because the offset gate portion “OG” does not have to be formed, for example. It can be small and is excellent.

FIG. 11 has the above advantages.
In each of the cells shown in (A) and (B), the state where the threshold voltage is the lowest is the state when data is erased.

FIG. 12 shows the relation between the threshold voltage of the cell and the stored data.

As shown in FIG. 12, this corresponds to a state where data is erased, that is, a state where data having the lowest threshold voltage Vth1 of "00" is stored.

"01", "10", "1"
When writing the data of "1", FIGS. 11A and 11B
In each of the cells shown in (1), a predetermined voltage is applied to the drain D and the control gate CG, and the source S is set to 0V. As a result, a current flows through the channel CH,
Electrons are injected into the floating gate FG. The injection of the electrons is performed by using the corresponding threshold voltages Vth2, Vth3, and Vth.
Repeat until th4.

In the third embodiment, “01”,
When writing “10” and “11” data, as shown in FIG. 13, the threshold voltage values Vth2, Vth
3 and Vth4, at least the value of the voltage supplied to the control gate CG is set to “Vpp1”, “Vpp2”, “Vp4”.
p3 ".

That is, when setting the threshold voltage of the memory cell to the second lowest threshold voltage Vth2, the lowest write voltage Vpp1 is supplied to the control gate CG of the memory cell, and electrons are injected into the floating gate FG. . After the electrons are injected, the verify read for checking is performed as described in the first embodiment. This injection and verify read are repeatedly performed until a predetermined value, that is, the threshold voltage of the memory cell becomes Vth2. Similarly, the threshold voltage of the memory cell is set to the third lowest threshold voltage Vth3.
Is set to 2 in the control gate CG of the memory cell.
The second lowest write voltage Vpp2 is supplied to inject electrons into the floating gate FG. Similarly, when setting the threshold voltage of the memory cell to the highest threshold voltage Vth4, the highest write voltage V
pp3 is supplied to inject electrons into the floating gate FG.

As in the third embodiment, the control gate CG
To the threshold voltages Vth2, Vth3, Vt
When changing according to h4, the amount of the change may correspond to the threshold voltage after the end of writing. Hereinafter, this basis will be described.

It is the potential of the floating gate FG that controls the channel CH of the memory cell, in other words, controls on / off of the memory cell. Even when the threshold voltages are different, the potential of the floating gate FG when the memory cell is turned on is the same.

When the memory cell is turned on, for example, the memory cell whose threshold voltage is Vth1 is supplied to the control gate CG with the voltage Vt.
Turns on when h1 is given. Similarly, the threshold voltage Vth2
Are turned on when the voltage Vth2 is applied to the control gate CG. This is because the floating gate F is applied both when the voltage Vth1 is applied to the control gate CG of the memory cell having the threshold voltage Vth1 and when the voltage Vth2 is applied to the control gate CG of the memory cell having the threshold voltage Vth2.
This means that the potential of G is the same.

The floating gate FG is connected to the control gate CG
Capacitively coupled to Therefore, assuming that the potential of the floating gate FG is in a neutral state, the potential of the floating gate FG becomes a function of the potential of the control gate CG. Here, it is assumed that the drain D and the source S are each 0 V, and the potential of the control gate CG is VCG. At this time, if the potential of the floating gate FG is set to VFG, the potential VFG of the floating gate FG determined by the capacitive coupling with the control gate CG is expressed by the following equation.

VFG = β × VCG Here, β is an arbitrary value between 0 and 1 The potential of the floating gate FG when the memory cell is turned on is constant regardless of the threshold voltage of the memory cell.

Now, considering a memory cell having a threshold voltage of Vth2, it turns on when a voltage of Vth2 is applied to the control gate CG. Depending on the injected electrons,
The potential of the floating gate FG lowered in the negative direction is set to “V2”
Assuming that the potential of the floating gate FG when applying the voltage Vth2 to the control gate CG is “VFG2”, the potential V
FG2 can be represented by the following equation (1).

[VFG2] = [Vth2 × β−V2] (1) Further, when the voltage Vth3 is applied to the control gate CG of this memory cell, the potential of the floating gate FG is set to “VFG2”.
The potential "VFG23" is determined by the following (2)
It is represented by an equation.

[VFG23] = [Vth3 × β−V2] (2) In the memory cell with the threshold voltage Vth3, the floating gate F lowered in the negative direction by the injected electrons.
G is set to “V3”, and the potential of the floating gate FG when the voltage of Vth3 is applied to the control gate CG is set to “VFG”.
Assuming 3 ″, the potential VFG3 can be expressed by the following equation (3).

[VFG3] = [Vth3 × β−V3] (3) That is, the memory cell having the threshold voltage Vth2 has a floating gate F
Turns on when the potential of G is “VFG2” shown in equation (1),
Since the memory cell having the threshold voltage Vth3 is turned on when the potential of the floating gate FG is "VFG3" shown in the equation (3),
Equations (1) and (3) are equal to each other, and the following equation (4) holds.

[Vth3 × β-V3] = [Vth2 × β-V2] (4) The threshold voltage of the memory cell having the threshold voltage of Vth3 is V
Since the injection amount of electrons is larger than that of the memory cell of th2,
The difference depending on the amount of injected electrons is expressed by the following equation (5).

[V3−V2] = [(Vth3 × β) − (Vth2 × β)] = [β (Vth3−Vth2)] (5) In order to set the memory cell to the threshold voltage of Vth2,
When the voltage Vpp1 is applied to the control gate CG to perform writing, and the potential of the floating gate when the voltage Vpp1 at the time of completion of the writing is applied is “VFG2P”, this potential VFG2P is expressed by the following equation (6). Become like

[VFG2P] = [Vpp1 × β−V2] (6) Since the electrons are drawn to the positive potential of the floating gate FG and injected into the floating gate FG, the injection of the electrons into the floating gate FG is performed by floating. It depends on the level of the potential of the gate FG. When the threshold voltage of the memory cell is set to Vth3, the voltage V is applied to the control gate CG.
pp2, the potential of the floating gate FG when the injection of electrons is completed is set to the same potential as the potential of the floating gate FG when the injection is completed when the threshold voltage of the memory cell is set to Vth2. Can be obtained by using the above equation (6) and satisfying the following equation (7).

[Vpp2 × β-V3] = VFG2P = [Vpp1 × β-V2] (7) The voltage Vpp2 satisfying the above equation (7) is obtained by modifying the above equation (7) and applying the following equation (8) Given by the equation.

Vpp2 = [Vpp1 + {(V3−V2) / β}] (8) That is, the voltage Vpp2 is set to {(V3
−V2) It is sufficient to set the voltage higher by / β}. From the above equation (5), (V3-V2) is [β (Vth3-V
th2)], substituting this into equation (8) yields the following equation (9).

Vpp2 = Vpp1 + (Vth3−Vth2) (9) As shown in the equation (9), it is understood that it is sufficient to supply a higher voltage by the difference between the threshold voltages to be set.

Similarly, when the threshold voltage of the memory cell is set to Vth4, the voltage Vpp3 applied to the control gate CG of the memory cell is higher than the voltage Vpp1 applied when the threshold voltage Vth2 of the memory cell is set. Is set to a higher voltage by a value obtained by subtracting the threshold voltage Vth2 from.

As described above, in the third embodiment, since the voltage for writing is changed in accordance with the data to be written, the potential state of the floating gate FG after writing is completed can be made equal, and electrons can be transferred to the floating gate. When injecting into the FG, the advantage that the potential difference between the floating gate FG and the channel CH can be equalized regardless of the value of the write data can be obtained.

In the third embodiment, a large voltage is supplied by the difference between the threshold voltages to be set. However, this is because of the difference between the reference potentials corresponding to the threshold voltages to be set. Only a high voltage may be supplied. For example, when the data of “10” of the bit line potential 3 shown in FIG. 3A is written, the VRFY reference potential 2 is higher than the voltage applied to the control gate CG when the data of “01” of the bit line potential 2 is written. And the difference between VRFY reference potential 1 and
Alternatively, a voltage higher by the difference between the READ reference potential 2 and the READ reference potential 1 may be applied.

Next, the configuration of the nonvolatile semiconductor memory device according to the third embodiment will be described. In the first and second embodiments,
As shown in FIG. 4, memory cells MC are arranged in a matrix, and a plurality of bits of data are stored in one memory cell MC.

When writing data to one memory cell MC connected to one word line (row line) WL,
A configuration in which a plurality of memory cell arrays 1 having the configuration shown in FIG. 4 are arranged and word lines (row lines) WL are commonly connected to the plurality of memory cell arrays 1 may be adopted. Such a configuration is shown in FIG.

FIG. 14 is a configuration diagram schematically showing a configuration of a nonvolatile semiconductor memory device according to the third embodiment.

As shown in FIG. 14, four memory cell arrays 1-1 to 1-4 are provided. Word line WL
, WL2,... Represent four memory cell arrays 1-1 to 1-1.
-4 are common to each other. Column selector 4
(4-1 to 4-4) correspond to the memory cell arrays 1-1 to 1-
For every four, a total of four are provided. Readout circuit 5
(5-1 to 5-4) and the write system circuit 7 (7-1)
7-4), the memory cell array 1-1
There are a total of four provided for each of .about.1-4.

In the structure shown in FIG. 14, one memory cell MC to which data is written has one word line (row line) W
In L, there are a plurality. For example, in the example shown in FIG. 14, when the word line WL1 is selected, the word line WL
1 is connected to the control gate, and the drains are connected to the bit lines BL11, BL12,.
Memory cell M with drain connected to BL13, BL14
C111, memory cell MC112, memory cell MC11
3. Data is written to the memory cell MC114.

As described above, in the third embodiment in which a plurality of memory cells MC to which data is written exist on one word line WL, the data is written starting from the data "01" set to the second lowest threshold voltage Vth2. , Data "10" set to the third lowest threshold voltage Vth3, and data "11" set to the highest threshold voltage Vth4 are written in this order so that the threshold voltages are sequentially increased.

Further, in the third embodiment, for example, FIG.
In order to write data “01” to the memory cell MC112 shown in FIG. 4, when electrons are injected into the floating gate FG of the memory cell MC112, the floating gate FG of the memory cell MC113 to which data “10” is written and the data “11” are written. Is also injected into each of the floating gates FG of the memory cells MC114 in which the threshold voltage is written. For this reason, the write voltage is applied to the bit line BL.
12 as well as bit lines BL13 and BL14
And a write voltage is applied to the drain of each of the memory cells MC112 to MC114. This is shown in FIG.

FIG. 15 is a waveform diagram showing changes in the drain potential and the word line potential of the memory cell at the time of writing according to the third embodiment.

As shown in FIG. 15, when writing data "01", that is, when setting the threshold voltage to Vth2,
While supplying the voltage Vpp1 to the word line WL1,
A predetermined write voltage, for example, a voltage Vc is applied to the drains of the memory cells MC112 to MC114. The verify read at the time of writing the data “01” may be performed only by the memory cell MC112,
C112, memory cell MC113, memory cell MC11
4 may be performed.

After the writing of the data “01” is completed,
As shown in FIG. 15, data "10" is written. When writing data “10”, the word line WL1
, The voltage Vpp2 and the data “10”
Is written to the memory cell MC113 and the data “11” is written to the memory cell MC114.
Write voltage is applied to the drain of. Note that no write voltage is applied to the drain of the memory cell MC112 into which the data “01” has been written.

After the writing of data “10” is completed,
Data “11” is written. When writing the data “11”, the voltage Vpp3 is supplied to the word line WL1, and a write voltage is applied to the drain of the memory cell MC114 to which the data “11” is written. Note that the memory cell MC11 in which the data “01” is written
2. Memory cell MC11 in which data "10" is written
No writing voltage is applied to each of the three drains.

The row decoder comprises a voltage generator for generating the above-mentioned three write voltages Vpp1, Vpp2 and Vpp3, and a decoder for applying any one of these three voltages to a selected word line.

As described above, according to the third embodiment, the setting of the threshold voltage according to each of the data "01", "10", and "11" is set in order from the lower threshold voltage. When electrons are injected into the floating gate of a memory cell whose threshold voltage is set low, electrons are also injected into the floating gate of a memory cell whose threshold voltage is set higher. Therefore, the data “01”,
The writing time can be reduced as compared with the case where “10” and “11” are individually written.

When writing the same data to each of a plurality of memory cells MC connected to the same word line WL, for example, when writing data “10” to each of the memory cells MC112 to MC114, the word line WL1
, A corresponding write voltage, that is, only the voltage Vpp2 may be supplied.

The third embodiment is not limited to the writing method in which the word line voltage is changed in accordance with the threshold voltage to be set. For example, as shown in FIG. Can be applied to a writing method that does not change the voltage of.

FIG. 16 is a waveform diagram showing changes in the drain potential and the word line potential of the memory cell at the time of writing according to a modification of the third embodiment. Note that FIG.
Are drawn corresponding to the waveforms shown in FIG.

As shown in FIG. 16, at the time of writing to a memory cell, even when the voltage supplied to the control gate is kept constant without changing the voltage supplied to the control gate in accordance with the threshold voltage to be set, data remains at 2 Writing is performed from the memory cell MC112 set to the second lowest threshold voltage Vth2. At this time, similarly to the waveform shown in FIG. 15, memory cell MC113 set to the third lowest threshold voltage Vth3, and memory cell MC11 set to the highest threshold voltage Vth4
Also in 4, a predetermined write voltage is supplied to the drain, and electrons are injected into the floating gate. Similarly, when setting to the third lowest threshold voltage Vth3, the highest threshold voltage Vth3 is set.
A predetermined write voltage is supplied to the drain of the memory cell MC114 set to 4, and electrons are injected into the floating gate.

In such a modification, the same effect as that of the writing described with reference to FIG. 15 can be obtained.

Two bits of data written to the memory cell, that is, “D1” and “D2” are “0”,
Whether it is "1" or "1" or "0"
Whether it is "1" or "1" is detected by a circuit as shown in FIG. 17, for example.

FIG. 17 is a circuit diagram of a detection circuit for detecting the type of data included in the nonvolatile semiconductor memory device according to the third embodiment.

As shown in FIG. 17, the detection circuit 51 includes
Three NOR gate circuits 61, 62, 63 are provided.

When the data D1 input to the detection circuit 51 is “0” and the data D2 is “1”, the N
Since both inputs of the OR gate circuit 61 become "0", the output signal S01 is made "1". At this time, in the other NOR gate circuits 62 and 63, since at least one of the two inputs becomes "1", their output signals S10 and S11 are each set to "0".

When the data D1 is "1" and the data D2 is "0", both inputs of the NOR gate circuit 62 become "0", so that the output signal S10 becomes
It is set to “1”. In the other NOR gate circuits 61 and 63, at least one of the two inputs is “1”.
Therefore, the output signals S01 and S11 are each set to “0”.

When the data D1 and D2 are both "1", the two inputs of the NOR gate circuit 63 are both "0", so that the output signal S11 is "1". In the other NOR gate circuits 61 and 62, at least one of the two inputs becomes "1".
The output signals S01 and S10 are each set to "0".

As described above, in the detection circuit 51, the signal S0 depends on the combination of data to be written into the memory cell.
One of the signals S1, S10 and S11 is set to "1".

Now, as shown in FIG. 14, four memory cell arrays 1 are arranged, and a word line (row line) WL selected by one row decoder 2 is connected to each memory cell array 1.
Assuming that the memory cells are commonly connected to -1, 1-2, 1-3 and 1-4, a maximum of four memory cells MC connected to one word line WL, for example, memory cells MC111 and MC11
2. Data is written to MC113 and MC114.

In such a case, four memory cells MC1
If all of the memory cells 11 to MC114 are set to the threshold voltage Vth1 (data “00”), it is not necessary to supply a voltage to the word line WL1 and write data to the memory cells MC111 to MC114. In the case of only two types (data “01”) and Vth3 (data “10”), only the voltages Vpp1 and Vpp2 need be supplied to the word line WL1.

In the third embodiment, data to be written is determined, and a voltage is supplied to a memory cell only when necessary. Therefore, the detection circuit 51 shown in FIG.
As shown in FIG.

FIG. 18 is a circuit diagram of a control circuit provided in the nonvolatile semiconductor memory device according to the third embodiment for determining data to be written and controlling the supply of voltage.

For example, 2-bit data (D1, D2), (D3, D4), (D5, D6), stored in four memory cells MC111 to MC114 as shown in FIG.
(D7, D8) respectively correspond to 4 of the control circuit shown in FIG.
Detection circuits 51-1, 51-2, 51-3, 51-4
To enter. A total of four signals S01 output from each of the four detection circuits 51-1 to 51-4 are input to the OR gate circuit 71. Similarly, a total of four signals S10 are input to an OR gate circuit 72, and a total of four signals S11 are input to an OR gate circuit 73.

In the OR gate circuit 71, four signals S0
1 is "1", the output signal Sv
pp1 becomes "1", and if all four signals S01 are "0", the output signal Svpp1 becomes "0".

When the signal Svpp1 is "1", it means that there is a memory cell whose threshold voltage is set to Vth2. Therefore, writing for setting the threshold voltage to Vth2 is performed on the memory cell corresponding to the writing.

On the other hand, when the signal Svpp1 is "0", it means that there is no memory cell for setting the threshold voltage to Vth2 among the data D1 to D8. Therefore, the writing for setting the threshold voltage to Vth2 is omitted, and the process proceeds to the next setting of the threshold voltage.

Similarly, in the OR gate circuit 72, if any one of the four signals S10 is "1", the output signal Svpp2 is "1", and all the four signals S10 are "0". , The output signal Svpp2 is “0”
Becomes

When the signal Svpp2 is "1", it means that there is a memory cell whose threshold voltage is set to Vth3, so that the threshold voltage for setting the threshold voltage to Vth3 is set in the memory cell corresponding to writing. Write.

On the other hand, when the signal Svpp2 is "0", it means that there is no memory cell for setting the threshold voltage to Vth3, so that writing for setting the threshold voltage to Vth3 is not performed.

Similarly, in the OR gate circuit 73, if any one of the four signals S11 is "1", the output signal Svpp3 is "1", and all the four signals S11 are "0". , The output signal Svpp3 is “0”
Becomes

Therefore, as described above, when the signal Svpp3 is "1", writing for setting the threshold voltage to Vth4 is performed on the memory cell corresponding to the writing.

When the signal Svpp3 is "0", writing for setting the threshold voltage to Vth3 is not performed as described above.

As described above, in the third embodiment, the signal Sv
Whether writing is performed or not is determined depending on whether the levels of pp1 to Svpp3 are “1” or “0”. For this reason, there is an advantage that the writing time can be shortened because there is a case where writing is not performed.

Further, in order to set a memory cell to a predetermined threshold voltage, when electrons are injected into the floating gate of the set memory cell, the voltage of the memory cell becomes higher than that of the memory cell.
For the floating gate of the memory cell set to a high threshold voltage,
By simultaneously injecting electrons, the writing time can be further shortened.

Fourth Embodiment FIG. 19 shows a schematic configuration of an 8-bit output nonvolatile semiconductor memory device as a fourth embodiment. In the conventional example shown in FIG. 33, a source potential circuit that supplies a high voltage to the source of a memory cell when erasing data and supplies a reference potential (0 V) when reading and writing data,
Although provided in common for each of the eight output bits, in the fourth embodiment, as shown in FIG.
.., 81-8 are output bits (I / O).
Line).

The source potential circuits 81-1 and 8-1 of this embodiment
.., 81-8 perform the same operation as that of the related art at the time of data erasing and data reading, but supply the potential corresponding to the data to be written to the source of the memory cell at the time of data writing. In this embodiment, at the time of data writing, memory cell arrays 11-1, 11-2,..., And 11-8 corresponding to respective output bits (each of which has a two-dimensional matrix arrangement of memory cells as shown in FIG. 4). ., 81-8 are supplied with predetermined potentials independently from each other. That is, the lowest potential (Vs3 in FIG. 13) is supplied to the memory cell array of the memory cells whose threshold voltage is desired to be set to the highest (Vth4 in FIG. 13), and data is written. When it is desired to set the threshold voltage Vth3 next to Vth4, a potential of Vs2 higher than Vs3 by a predetermined potential is supplied. An electric potential is supplied. The source potential is set to a predetermined voltage in accordance with the data to be written, and writing is performed simultaneously on each memory cell. Therefore, if the potential of the control gate is VcG, (VcG-Vs
3)>(VcG-Vs2)> (VcG-Vs1), so that the potential difference between the source and the control gate of the memory cell can be increased in the order of increasing the threshold voltage, that is, the amount of electrons injected into the floating gate The writing is performed by increasing the potential difference between the source and the control gate of the memory cell in the order in which the threshold voltage needs to be increased, so that the potential difference can be adjusted to the optimum potential corresponding to the threshold voltage to be set. Since the accuracy can be improved and writing can be performed simultaneously on each memory cell, the writing time can be reduced.

FIG. 20 shows the write and verify read operations of this embodiment until the memory cell reaches a predetermined threshold voltage.
It shows a state of repeating. When writing data, the source of the memory cell is set to a predetermined voltage corresponding to the data to be written (threshold voltage). If the verify reading indicates that the memory cell has reached the predetermined threshold voltage, the application of the voltage to the drain of the memory cell is stopped,
Writing of data to another bit whose memory cell has not reached the predetermined threshold voltage is continued.

Next, a specific configuration of source potential circuit 81 will be described.

FIG. 21 shows a first example of the source potential circuit 81, and FIG. 22 shows the logical level of each signal. When writing data, the signal S7 is set to "0", the inverted signal / S7 of the signal S7 is set to "1", and the N-channel transistor T
9 and the P-channel transistor T10 are turned off to disconnect the erase circuit 83 from the memory cell MC. Memory cell M
When setting the source potential of C to the highest voltage VS1, the signal S1 is set to "0" to turn on the P-channel transistor T1. Further, the signal S2 is set to “1”,
3 to "0" to turn on the transistor T2 and turn off the transistor T3. For this reason, the potential at the connection point between the resistors R1 and R2 is set to
5 gates. Further, the signal S4 is set to "0" to turn on the P-channel transistor T4. Signal S5
To "1", the signal S6 to "0", and the transistor T
7 is turned on and the transistor T8 is turned off. Therefore, the source of the memory cell is connected to the connection point between the transistor T5 and the transistor T6 via the transistor T7.

When writing is performed on a memory cell, a current flows through the memory cell and the transistor T7
And discharged to the reference potential via the transistor T6.
When a current flows, the drain of the transistor T6, that is, the source potential of the memory cell increases due to the resistance of the transistor T6. The rise in potential is caused by resistances R1 and R
When the potential of the transistor T5 approaches the potential obtained by subtracting the threshold voltage of the transistor T5 from the potential of the connection point of the transistor 2, the potential of the connection point between the transistor T4 and the transistor T5, that is, the gate potential of the transistor T6 Rises and a large amount of current flows through the transistor T6, so that the source potential of the memory cell is stabilized at a potential slightly lower than the potential obtained by subtracting the threshold voltage of the transistor T5 from the potential at the connection point between the resistors R1 and R2. I do.

The source potential of the memory cell is changed to the next higher voltage V
When setting to S2, the signal S2 is set to “0” and the signal S3 is set to “0”.
To “1” to turn off the transistor T2 and turn on the transistor T3. For this reason, the potential at the connection point between the resistors R2 and R3, which is lower than the potential at the connection point between the resistors R1 and R2 by a predetermined value, changes to the transistor T5
Is supplied to the gate. Therefore, the source potential of the memory cell is determined from the potential of the connection point between the resistors R2 and R3 by the transistor
It stabilizes at a potential slightly lower than the potential obtained by subtracting the threshold voltage of 5.

The source potential of the memory cell is set to the lowest voltage V
When setting to S3, the signal S5 is set to "0" and the signal S6 is set to "1". Therefore, the transistor T7 turns off and the transistor T8 turns on. If the resistance value of the transistor T8 when the transistor T8 is turned on is sufficiently small, a potential close to the reference potential can be obtained as VS3. At this time, both the signal S1 and the signal S4 are "1".
If the transistor T1 and the transistor T4 are turned off in this way, current consumption can be reduced.

At the time of reading data, signals S1,
S4 is set to "1", and P-channel transistors T1, T
Turn 4 off. Further, the signal S5 is set to “0” and the signal S6 is set to “0”.
Is set to "1", the transistor T7 is turned off, the transistor T8 is turned on, and the source of the memory cell is connected to the reference potential via the transistor T8.

When erasing data, the signals S5 and S6 are set to "0", and the transistors T7 and T8 are turned off. The signal S7 is set to "1" and the signal / S7
Is set to “0”, and the transistors T9 and T
Then, the high voltage output from the erasing circuit is supplied to the source of the memory cell via the transistors T9 and T10 to erase data.

The P-channel transistor T0 to which the signal S4 is input to the gate shown by the broken line does not need to be particularly provided, but the source potentials of the memory cells are VS1 and VS
If it is turned on when it is set to 2, the source potential of the memory cell becomes more stable. That is, since electrons are injected into the floating gate of the memory cell to change the current flowing in the memory cell, this P-channel transistor T0 is provided, and if a current is supplied from here, the P-channel transistor T0 is connected through the transistors T6 and T7. This is because the ratio of the change in the total current to the change in the current flowing in the memory cell becomes smaller because the current flowing to the reference potential increases.

FIGS. 23 and 24 show a second example of the source potential circuit 81. FIG. In this example, the source potential of the memory cell is changed by changing the resistance value of the transistor connected between the memory cell and the reference potential in accordance with the data to be written to the memory cell, that is, the threshold voltage of the memory cell to be set. Set. Note that the transistors T9 and T10 are the same as those in FIG. 21 and are off when writing and reading data.

When the source potential of the memory cell is set to the highest voltage VS1 as shown in FIG. 24, the signal S8 is set to "1". The signal S9 and the signal S10 are set to “0”. Therefore, the transistors T11, T1
2 and T13, only the transistor T11 is turned on, and the current flowing from the memory cell to the reference potential via the transistor T11 causes the potential difference between the drain and source of the transistor T11 to be VS1.

When setting the next higher potential VS2, the signals S8 and S9 are set to "1" to turn on the transistors T11 and T12. Since the resistance value between the source of the memory cell and the reference potential is reduced by the amount of time when the transistor T12 is turned on, the source potential of the memory cell is reduced by that amount.

When the potential VS3 is set to the lowest potential, the signals S8, S9 and S10 are all set to "1" to turn on the transistors T11, T12 and T13. Therefore, at this time, the source of the memory cell is set to the lowest potential.

When reading data, the transistors T11, T12, and T13 are all turned on to read the data so that the source potential of the memory cell becomes lowest. When erasing data, the transistor T1
1, T12 and T13 are turned off, and a high voltage from the erasing circuit 83 is supplied to the source of the memory cell via the transistors T9 and T10 which are turned on at this time to erase data.

FIGS. 25 and 26 show a third example of the source potential circuit 81. FIG. In this example, the source potential of the memory cell is set according to the data to be written to the memory cell using the threshold voltage of the transistor, that is, the threshold voltage of the memory cell to be set. Also in this embodiment, the transistors T9 and T10 are the same as those in FIG. 21 and are off when writing and reading data.

When the source potential of the memory cell is set to the highest VS1 as shown in FIG. 26, signal S11 is set to "1".
And the signals S12 and S13 are set to "0". For this reason, the transistors T18 and T19 are turned off, the transistor T16 is turned on, and the source potential of the memory cell is connected to the reference potential via the transistor T14 and the transistor T15 whose gates and drains are respectively connected. And approximately the sum of the threshold voltages of the transistor T15.

When setting to the next higher potential VS2, the signals S11 and S12 are set to "1" to turn on the transistors T16 and T18. For this reason, the source of the memory cell is connected to the reference potential via the transistor T17 whose gate and drain are connected.
The threshold voltage is set to seventeen. The sum of the threshold voltages of the transistor T14 and the transistor T15
17, the transistor T14,
15 does not operate substantially. Therefore, the signal S11 is set to "0".
To turn off the transistor T16.

When the lowest potential VS3 is set, the signals S11, S12 and S13 are all set to. "1" to turn on the transistors T16, T18, T19. Since the transistor T19 is turned on, the source of the memory cell is set to almost the reference potential. Therefore, at this time, the source of the memory cell is set to the lowest potential. At this time, since the transistors T14, T15, and T17 do not substantially operate, the signals S11 and S12 may be set to "0" to turn off the transistors T16 and T18.

When reading data, all of the transistors T16, T18, T19 may be turned on, but as described above, the transistors T14, T15,
Since T17 does not substantially operate, the transistor T19
Data may be read by turning ON only. When erasing data, the transistors T16, T18 and T19 are turned off, and the transistors T9 and T10 which are turned on at this time.
To supply the high voltage from the erasing circuit 83 to the source of the memory cell to erase the data.

FIG. 27 shows an example of the erase circuit 83. The erase circuit 83 is conventionally connected directly to the source of the memory cell, but in the present embodiment, it is connected via the transistors T9 and T10 as described above. At the time of data erasure, the signal E becomes "1", and the high voltage Vpp is output to the memory cell to erase the data. When reading and writing data, the signal E is set to "0" and the output of the erase circuit 83 is connected to the reference potential. Also at the time of data erasing, verify reading is performed after erasing, and if erasing is not sufficient, erasing is performed again. When erasing and verify reading are repeated and a predetermined threshold voltage is reached, erasing is terminated.

In this embodiment, the erasing circuits 83 are provided in the source potential circuits 81 provided for each memory cell array for each output bit. However, one erasing circuit 83 may be provided in common. . FIG. 28 shows a circuit diagram in this case. This shows an example applied to the source potential circuit of FIG. .., 81-8 connected to the memory cell arrays corresponding to I / O1 to I / O8, respectively, and one erase circuit 83 is commonly used. Provided. Note that S8-1, S
9-1 and S10-1 etc. are signals S8 and S10 in FIG.
9, S10, S8-1, S9-1, S
10-1 is determined according to data to be written to I / O1, and S8-2, S9-2, and S10-2 are determined according to data to be written to I / O2.

As described above, according to the fourth embodiment, the time for writing data to a memory cell can be reduced, and even if a plurality of bits of data are stored in one memory cell, the threshold voltage can be set accurately. A non-volatile semiconductor memory device that can be obtained is obtained.

In the present embodiment, 2-bit data is stored in the memory cell. In this case, the same address may be given to these two bits, or a different address may be given to each bit.

FIG. 19 shows a configuration in which one memory cell array corresponds to one I / O.
A configuration in which a plurality of memory cells correspond to one I / O may be employed. For example, in the example shown in FIG. 29, eight memory cell arrays 11-1 to 11-8 constitute a memory cell array unit, and one of the plurality of memory cell array units is selected by a column decoder. Data read from each of the memory cell arrays 11-1 to 11-8 of the selected memory cell array section is output from I / O1 to I / O8.

[0193]

As described above, according to the present invention, according to the present invention, the difference between the read speeds of the selected memory cells can be made as small as possible, and the write data of the nonvolatile semiconductor memory device can be reduced. It is possible to provide a verification method, a nonvolatile semiconductor memory device capable of shortening a write time for writing data stored by a plurality of types of threshold voltages as much as possible, and a data writing method of the nonvolatile semiconductor memory device.

[Brief description of the drawings]

FIG. 1 is a waveform chart showing an operation of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a change in word line potential at the time of data writing in the nonvolatile semiconductor memory device according to the first embodiment of the present invention;

FIGS. 3 (A) and 3 (B) respectively show a first embodiment of the present invention.
FIG. 10 is a diagram showing a relationship between a reference potential and a bit line potential of the nonvolatile semiconductor memory device according to the embodiment.

FIG. 4 is a configuration diagram schematically showing a configuration of a nonvolatile semiconductor memory device;

FIG. 5 is a configuration diagram showing a sense amplifier included in the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a relationship between an output of a sense amplifier and stored data.

FIG. 7 is a diagram showing an output buffer included in a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 8 is a circuit diagram of the output buffer shown in FIG. 7;

9 is a diagram showing the level of a signal input to the output buffer shown in FIG. 8 for each mode.

FIGS. 10A to 10D are waveform diagrams showing output waveforms at the time of data output of the nonvolatile semiconductor memory device according to the second embodiment of the present invention.

11A and 11B are diagrams showing a memory cell; FIG. 11A is a diagram showing a cross section of a memory cell without an offset gate portion; FIG. 11B is a diagram showing a cross section of a memory cell having an offset gate portion; FIG.

FIG. 12 is a diagram showing a relationship between a threshold voltage and stored data.

FIG. 13 is a view showing a relationship among a write voltage, a threshold voltage, and stored data of a nonvolatile semiconductor memory device according to a third embodiment of the present invention.

FIG. 14 is a configuration diagram schematically showing a configuration of a nonvolatile semiconductor memory device according to a third embodiment of the present invention;

FIG. 15 is a waveform chart showing changes in a drain potential and a word line potential of a memory cell at the time of writing according to a third embodiment of the present invention.

FIG. 16 is a waveform chart showing changes in a drain potential and a word line potential of a memory cell during writing according to a modification of the third embodiment.

FIG. 17 is a circuit diagram of a detection circuit included in the nonvolatile semiconductor memory device according to the third embodiment.

FIG. 18 is a circuit diagram of a control circuit included in the nonvolatile semiconductor memory device according to the third embodiment.

FIG. 19 is a circuit diagram showing a schematic configuration of a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 20 is an operation waveform diagram when writing and verify reading are repeatedly performed in the fourth embodiment.

FIG. 21 is a circuit diagram of a first example of a source potential circuit according to a fourth embodiment;

FIG. 22 is a diagram showing logical levels of signals of the source potential circuit of FIG. 21;

FIG. 23 is a circuit diagram of a second example of the source potential circuit according to the fourth embodiment.

FIG. 24 is a diagram showing logical levels of signals of the source potential circuit of FIG. 23;

FIG. 25 is a circuit diagram of a third example of the source potential circuit according to the fourth embodiment;

FIG. 26 is a diagram showing logical levels of signals of the source potential circuit of FIG. 25;

FIG. 27 is a circuit diagram of a first example of an erasing circuit included in the source potential circuit according to the fourth embodiment;

FIG. 28 is a circuit diagram showing a modification of the fourth embodiment.

FIG. 29 is a circuit diagram showing another modification of the fourth embodiment;

FIG. 30 is a configuration diagram schematically showing a configuration of a nonvolatile semiconductor memory device;

FIGS. 31A and 31B are diagrams showing a relationship between a conventional reference potential and a bit line potential, respectively.

FIG. 32 is a configuration diagram showing a conventional sense amplifier.

FIG. 33 is a diagram showing a relationship between an output of a sense amplifier and stored data.

FIG. 34 is a circuit diagram showing a configuration of a conventional source potential circuit.

[Explanation of symbols]

1,1-1,1-2,1-3,1-4 ... memory cell array, 2 ... row decoder, 3 ... column decoder, 4,4-1,4-2,4-3,4-4 ... column Selector, 5,5-1, 5-2, 5-3, 5-4 read-out circuit, 6 output node, 7, 7-1, 7-2, 7-3, 7-4 write-in circuit , 11, 12, 13 ... sense amplifier, 20 ... package, 21 ... nonvolatile semiconductor memory device chip, 22 ... output buffer, 23 ... pad, 24 ... outer lead terminal, 31, 33, 36, 39, 40, 42, 43 ... PMO
S, 32, 34, 35, 37, 38, 41, 44 ... NMO
S, 51, 51-1, 51-2, 51-3, 51-4 ... detection circuit, 61, 62, 63 ... NOR gate circuit, 71, 72, 73 ... OR gate circuit.

Claims (42)

[Claims] A charge storage unit electrically connected to the row line; a column line; a drain and a source electrically connected to the column line; and a control gate electrically connected to the row line. A memory cell that stores a plurality of bits of data by changing an amount of charge stored in a storage unit; a sense amplifier that detects data stored in the memory cell using a plurality of predetermined reference potentials; After writing the data to the memory, a read is performed to check the charge accumulation state of the charge accumulation unit after the write, and when it is determined that the desired data has been written by the read, the write is terminated. When it is determined by reading that the desired data has not been written, the writing and reading are performed until it is determined that the desired data has been written. And a program means for repeating the above. The data read from the memory cell is output to the outside at the time of normal reading, which is performed at the time of reading by the program means. A non-volatile semiconductor memory device, which is performed at a time later than the time at which the non-volatile semiconductor memory is performed. 2. The reading by the program means,
2. The nonvolatile semiconductor memory device according to claim 1, wherein the operation is performed using the sense amplifier. 3. The method according to claim 2, wherein the plurality of reference potentials are set higher during the readout by the program means with respect to the corresponding reference voltages than during the normal readout. The nonvolatile semiconductor memory device according to claim 1. 4. The data of the plurality of bits is binary data of at least two bits, and the plurality of reference potentials are at least three reference potentials having different potentials, respectively. Is the first combination of binary data of 2 bits, the potential of the column line at the time of normal reading becomes a potential lower than the lowest reference potential of the three reference potentials When the threshold voltage of the memory cell is set as described above, and when the storage data of the memory cell is the second combination of binary data of two bits, the potential of the column line during normal reading is three The threshold voltage of the memory cell is set to be a potential between a reference potential of the lowest one of the three reference potentials and a reference potential of an intermediate potential among the three reference potentials. When the storage data of the recell is the third combination of binary data of 2 bits, the potential of the column line at the time of normal reading is equal to the reference potential of an intermediate potential among the three reference potentials. The threshold voltage of the memory cell is set so as to be a potential between the highest reference potential of the three reference potentials, and the storage data of the memory cell is the fourth binary data of two bits. In the case of the combination of the above, the threshold voltage of the memory cell is set such that the potential of the column line at the time of normal reading is higher than the highest reference potential of the three reference potentials. At the time of writing data to the memory cell, the voltage supplied to the row line is set to a higher value when writing the third combination of data than when writing the second combination of data. When writing the data of the fourth combination, the voltage supplied to the row line is controlled to be set to a higher value than when writing the data of the third combination. The nonvolatile semiconductor memory device according to claim 1. 5. The method according to claim 3, wherein at the time of said reading by said program means, when the potential of said column line becomes higher than the corresponding reference potential, writing of data to said memory cell is stopped. 3. The nonvolatile semiconductor memory device according to 1. 6. The method according to claim 1, wherein when data is written to the memory cell, a voltage supplied to a control gate of the memory cell is controlled so as to change in accordance with the write data. Nonvolatile semiconductor memory device. 7. A method according to claim 1, wherein, when writing data to said memory cell corresponding to said write data, a change amount of a voltage supplied to a control gate of said memory cell is substantially equal to a difference between threshold voltages of said memory cells to be set, 7. The nonvolatile semiconductor memory device according to claim 6, wherein the difference is one of the corresponding differences in the reference potential. 8. The data writing to the memory cells by the program means is performed simultaneously on a plurality of memory cells connected to the same row line, and at least two different threshold voltages are applied to the plurality of memory cells. When setting the threshold voltage, first, a threshold voltage is set to the memory cell corresponding to the lower threshold voltage, and after this setting, a threshold voltage is set to the memory cell corresponding to the higher threshold voltage, In order to set a threshold voltage for the plurality of memory cells corresponding to the threshold voltage, when injecting charge into the charge storage portion of the corresponding memory cell, the charge of the memory cell set to the higher threshold voltage is set. 7. The non-volatile semiconductor memory device according to claim 1, wherein control is performed so that charges are simultaneously injected into the storage unit. 9. The method according to claim 2, wherein when the data is read out by the program means and the data is output to the outside, the charging / discharging time of the external output terminal is set longer than in the normal reading. 3. The nonvolatile semiconductor memory device according to 1. 10. (a) Write data of a desired value is
(B) writing data written in the memory cell to a bit line, and (c) writing data written in the memory cell to the bit line. Comparing the bit line potential with a reference potential; (d) determining whether the desired write data has been written based on the result of the comparison; and (e) performing the steps (a) to (d). And repeating until the desired write data is written. Here, the step (d) is performed at the time of normal reading after a lapse of time at which the read data is output to the outside. A method for verifying write data in a semiconductor memory device. 11. (a) Write data of a desired value
(B) writing data written in the memory cell to a bit line, and (c) writing data written in the memory cell to the bit line. Comparing the bit line potential with a reference potential; (d) determining whether the desired write data has been written based on the result of the comparison; and (e) performing the steps (a) to (d). It repeats until the desired write data is written. Here, the speed of outputting the write data to the outside in the procedure (d) is lower than the speed of outputting the read data at the time of the normal reading to the outside. A method of verifying write data in a nonvolatile semiconductor memory device. 12. A read circuit for reading storage data stored in a rewritable nonvolatile memory cell to a bit line, and a bit line potential after the storage data is read to the bit line. A comparison circuit for comparing with a reference potential; and an output circuit for outputting detection data detected based on the result of the comparison to the outside, wherein the output circuit is connected in series between power supply voltages inside the integrated circuit. And first and second insulated gate FETs for electrically connecting an output to an external terminal, and one of the first and second insulated gate FETs performed according to the detection data. Charge and discharge speed of the other gate are made slower at the time of reading to check write data performed after writing than at the time of normal reading, and Of the time required for charging and discharging, the than during reading for checking the write data, the usual non-volatile semiconductor memory device and setting longer than the time of reading. 13. At least three first, second and third data are distinguished by at least two reference potentials of a first reference potential and a second reference potential at a level different from the first reference potential. Storing the first data with a first threshold voltage, storing the second data with a second threshold voltage higher than the first threshold voltage, and storing the third data with the second threshold voltage. Storing by a third threshold voltage higher than the threshold voltage, storing by at least three threshold voltages,
What is claimed is: 1. A data writing method for a nonvolatile semiconductor memory device having a plurality of data rewritable nonvolatile memory cells, wherein the first memory cell set to the first threshold voltage includes:
Setting the first threshold voltage, applying a first write voltage to a gate of a second memory cell set to the second threshold voltage, and applying the second threshold voltage to the second memory cell A voltage is set, and a difference between the second threshold voltage and the third threshold voltage, and a difference between the first reference potential and the third reference voltage are applied to a gate of a third memory cell set to the third threshold voltage. The second threshold voltage is applied to the third memory cell by applying a second write voltage whose voltage is higher than the first write voltage by an amount corresponding to one of the differences from the second reference potential. A data writing method for a nonvolatile semiconductor memory device, comprising setting a voltage. 14. The first data is stored by a first threshold voltage, the second data is stored by a second threshold voltage higher than the first threshold voltage, and the third data is stored by the second threshold voltage.
A memory cell array in which a plurality of non-volatile data rewritable memory cells are stored based on a third threshold voltage higher than the threshold voltage and stored with at least three threshold voltages, based on write data. A write circuit for controlling a voltage applied to a column line of a memory cell array to write the write data to the memory cell; detecting whether the write data is the second data or the third data; 2, the voltage applied to the row line of the memory cell array is the first write voltage, and the write data is the third write voltage.
, The voltage applied to the row line is changed to the first
The writing voltage of the second threshold voltage and the difference between the first reference potential and the second reference potential, the voltage is equal to one of the difference between the second threshold voltage and the third threshold voltage. And a write data detection circuit for outputting a control signal for increasing the second write voltage. 15. The first data is stored according to a first threshold voltage, the second data is stored according to a second threshold voltage higher than the first threshold voltage, and the third data is stored according to the second threshold voltage.
At least 3 of a third threshold voltage higher than the threshold voltage of
A data writing method for a non-volatile semiconductor memory device having a plurality of data rewritable non-volatile memory cells storing data at one threshold voltage and writing data to a plurality of memory cells at the same time, comprising: In a first memory cell set to a voltage,
After setting the first threshold voltage, the gate of the second memory cell set to the second threshold voltage and the gate of the third memory cell set to the third threshold voltage are respectively A first write voltage is applied to shift the threshold voltage of each of the second and third memory cells from the first threshold voltage to the second threshold voltage. After setting the second threshold voltage,
Applying a second write voltage to a gate of a third memory cell set to the third threshold voltage, the threshold voltage of which is shifted from the first threshold voltage to the second threshold voltage; And setting a third threshold voltage in the third memory cell. 16. The first, second, and third data are each distinguished by at least two reference potentials, a first reference potential and a second reference potential at a level different from the first reference potential, The second write voltage is the difference between the second threshold voltage and the third threshold voltage with respect to the first write voltage and the difference between the first reference potential and the second reference potential. 16. The data writing method for a nonvolatile semiconductor memory device according to claim 15, wherein the voltage is increased by an amount corresponding to one of the differences. 17. When at least one of the second and third data does not exist in write data to a plurality of memory cells to which data is written at the same time,
17. The data writing method for a nonvolatile semiconductor memory device according to claim 15, wherein writing of the non-existent data is omitted. 18. The first data is stored by a first threshold voltage, the second data is stored by a second threshold voltage higher than the first threshold voltage, and the third data is stored by the second threshold voltage.
At least 3 of a third threshold voltage higher than the threshold voltage of
A memory cell array in which a plurality of data rewritable nonvolatile memory cells are stored by two threshold voltages, and a voltage applied to a column line of the memory cell array based on write data is controlled, and the write data is stored in the memory cell array. A plurality of write circuits for writing to a memory cell; and detecting, for each of the write data input to the plurality of write circuits, whether the write data is the second data or the third data. When there is at least one data, the row line of the memory cell array is set to a first write voltage in order to write the second data,
When there is at least one third data in the write data, a row line of the memory cell array is set to a second write voltage in order to write the third data, and the second and third write voltages are applied to the write data. And a write control circuit for outputting a control signal for omitting writing of the non-existent data when at least one of the data does not exist. 19. Each of the first, second, and third data is distinguished by at least two reference potentials, a first reference potential and a second reference potential at a level different from the first reference potential, The second write voltage is the difference between the second threshold voltage and the third threshold voltage with respect to the first write voltage and the difference between the first reference potential and the second reference potential. 19. The non-volatile semiconductor memory device according to claim 18, wherein the voltage is increased according to any of the differences. 20. A multi-bit data storage system comprising a row line and a column line, arranged in a matrix, each having a drain, a source, a floating gate, and a control gate, and storing different amounts of electrons in the floating gate. The control gates of the memory cells in the same row are commonly connected to one of the row lines, and the drains of the memory cells in the same column are commonly connected to one of the column lines. And a source potential setting unit that varies the potential of the source in accordance with the data to be stored when writing data to the memory cell injecting charges into the floating gate. A nonvolatile semiconductor memory device characterized by the above-mentioned. 21. The source potential setting means is a transistor having a drain connected to a source of the memory cell and a source connected to a reference potential, and when writing the data, the source potential setting means corresponds to the data to be stored. 21. The nonvolatile semiconductor memory device according to claim 20, wherein a resistance value changes. 22. The nonvolatile semiconductor memory device according to claim 20, wherein the plurality of bits of data stored in the memory cell are data of different addresses. 23. The nonvolatile semiconductor memory device according to claim 20, wherein the data of a plurality of bits stored in the memory cell is a plurality of output bits. 24. The nonvolatile semiconductor memory device according to claim 20, wherein a plurality of bits of data stored in said memory cell have the same address. 25. The nonvolatile semiconductor memory device according to claim 20, wherein a plurality of said memory cell arrays are provided. 26. The memory cell array according to claim 2, wherein the plurality of memory cell arrays have the same bit output data.
6. The nonvolatile semiconductor memory device according to 5. 27. The nonvolatile semiconductor memory device according to claim 25, wherein data is written to said plurality of memory cell arrays simultaneously. 28. A memory cell having a drain, a source, a floating gate, and a control gate, and storing a plurality of bits of data by storing different amounts of electrons in the floating gate; and the memory cells are arranged in a matrix. The control gates of the memory cells on the same row arranged in a matrix are commonly connected to one of a plurality of row lines, and the drains of the memory cells on the same column are commonly connected to one of a plurality of column lines. ,
A memory cell array including a plurality of memory cell blocks formed by connecting the sources of the memory cells in common; and writing data to the memory cells provided for each of the memory cell blocks and injecting a charge into the floating gate. And a source potential setting unit that varies the potential of the source in accordance with the data to be stored. 29. The nonvolatile semiconductor memory device according to claim 28, wherein the data of a plurality of bits stored in the memory cell are data of different addresses. 30. The nonvolatile semiconductor memory device according to claim 28, wherein the plurality of bits of data stored in the memory cell are a plurality of output bits. 31. The nonvolatile semiconductor memory device according to claim 28, wherein a plurality of said memory cell arrays are provided. 32. The nonvolatile semiconductor memory device according to claim 31, wherein the corresponding memory cell blocks of the plurality of memory cell arrays have the same bit output data. 33. The nonvolatile semiconductor memory device according to claim 28, wherein data is simultaneously written to a plurality of memory cell blocks in said memory cell array. 34. A semiconductor device comprising a row line and a column line, arranged in a matrix, storing a plurality of bits of data by changing a threshold voltage according to an amount of charge in a charge storage unit,
Each having a memory cell having a drain, a source, the charge storage portion and a control gate, wherein the control gates of the memory cells on the same row are commonly connected to one of the row lines and the memory cells on the same column Write data simultaneously to a memory cell array commonly connected to one of the column lines, and at least two memory cells connected to the same row line, and write at least two to the at least two memory cells. When setting different types of threshold voltages, a threshold voltage is first set for the memory cell corresponding to the lower threshold voltage, and after this setting, a threshold voltage is set for the memory cell corresponding to the higher threshold voltage. When injecting charge into the charge storage unit of the corresponding memory cell to inject charge into the charge storage unit of the memory cell corresponding to the lower threshold voltage, A non-volatile semiconductor memory device, comprising: program means for controlling to simultaneously inject charge into the charge storage portion of the memory cell set to the higher threshold voltage. 35. The nonvolatile semiconductor memory according to claim 34, wherein said program means supplies a voltage corresponding to the data to be written to a control gate of said memory cell when writing data to said memory cell. apparatus. 36. A data erasing device, further comprising: after setting data stored in the memory cell to a predetermined value by the data erasing device, selectively writing data to the memory cell by the program device. Claim 3
The nonvolatile semiconductor memory device according to claim 4 or claim 35. 37. When setting a threshold voltage for the memory cell corresponding to a lower threshold voltage, the program means supplies a first voltage to the row line and sets the memory cell to the lower threshold voltage. Charge is simultaneously injected into the charge storage unit of the memory cell and the charge storage unit of the memory cell set to the higher threshold voltage, and after setting the threshold voltage of the memory cell corresponding to the lower threshold voltage, When setting a threshold voltage for the memory cell to be set to the higher threshold voltage, a second voltage having a voltage value larger than the first voltage is supplied to the row line, and the higher threshold voltage is set. 35. The nonvolatile semiconductor memory according to claim 34, wherein a charge is injected into a charge storage portion of the memory cell set to a voltage, and a threshold voltage is set to the memory cell corresponding to the higher threshold voltage. apparatus. 38. A semiconductor device comprising a row line and a column line, arranged in a matrix, and storing a plurality of bits of data by changing a threshold voltage according to an amount of charge of a charge storage unit.
Each having a memory cell having a drain, a source, the charge storage portion and a control gate, wherein the control gates of the memory cells on the same row are commonly connected to one of the row lines and the memory cells on the same column A memory cell array section including a plurality of memory cell arrays commonly connected to one of the column lines; and an output circuit provided corresponding to the plurality of memory cell arrays, for outputting storage data of the memory cells to the outside. And simultaneously writing data to the memory cells in the plurality of memory cell arrays in accordance with write data to the memory cells, and setting at least two different threshold voltages for the memory cells in the plurality of memory cell arrays. At first, a threshold voltage is first set to the memory cell corresponding to the lower threshold voltage, and after this setting, the threshold voltage is set to the higher threshold voltage. Setting a threshold voltage to the memory cell, and injecting a charge into a charge storage unit of the corresponding memory cell to set a threshold voltage to a memory cell corresponding to the lower threshold voltage; And a program means for controlling to simultaneously inject electric charge into the electric charge accumulating portion of the memory cell which is set to the threshold voltage of the non-volatile semiconductor memory device. 39. The nonvolatile semiconductor memory device according to claim 38, wherein corresponding row lines of said plurality of memory cell arrays are connected to each other. 40. The method according to claim 38, wherein the program means supplies a voltage corresponding to the data to be written to the control gate of the memory cell when writing data to the memory cell. 14. The nonvolatile semiconductor memory device according to claim 1. 41. When the program means sets a threshold voltage for the memory cell corresponding to the lower threshold voltage, the control means controls the memory cell corresponding to the lower threshold voltage to a first voltage. Supplying the gate and the control gate of the memory cell corresponding to the higher threshold voltage;
The charge is simultaneously injected into the charge storage unit of the memory cell set to the lower threshold voltage and the charge storage unit of the memory cell set to the higher threshold voltage, and the charge corresponding to the lower threshold voltage is set. When setting a threshold voltage for the memory cell corresponding to the higher threshold voltage after setting the threshold voltage of the memory cell, a second voltage having a voltage value larger than the first voltage is set to the higher voltage. The memory cell corresponding to the higher threshold voltage is supplied to the control gate of the memory cell corresponding to the threshold voltage, and charge is injected into a charge storage portion of the memory cell set to the higher threshold voltage. 41. The non-volatile semiconductor storage device according to claim 38, wherein a threshold voltage is set for the non-volatile semiconductor memory device. 42. A data erasing unit, further comprising: after setting data stored in the memory cell to a predetermined value by the data erasing unit, selectively writing data to the memory cell by the program unit. Claim 3
The nonvolatile semiconductor memory device according to any one of claims 8 to 41.