JP2008262626A - Nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology capable of improving data holding characteristics in a nonvolatile semiconductor memory having a MONOS (Metal-oxide-Nitride-Oxide-Silicon) type memory cell, in which an electric charge accumulating layer is formed of a nitride film. <P>SOLUTION: When the data are erased ("1" program), a weak writing operation (Post-Weak-Write) is carried out after normal erasing operation (Erase). The weak writing operation means an operation for writing by an applied voltage lower than that for the normal writing operation, or the operation for writing by applying the voltage in a short period, and so on. For instance, voltage of 12V is applied to a gate during 1ms period as for the normal write-in, voltage of -10v is applied to the gate during 1ms period as for the erase, and voltage of 4-6V is applied to the gate during 0.1ms period as for the weak write-in. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory, and more particularly, to a nonvolatile semiconductor memory having a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type memory cell using a nitride film as a charge storage layer.

  As a technique studied by the present inventors, for example, the following techniques can be considered in a nonvolatile semiconductor memory.

  Non-volatile memory cells such as EEPROMs and flash memories include, for example, floating (floating) gate type that stores charges in conductive polycrystalline silicon surrounded by an oxide insulating film, and charges in trapping centers in silicon nitride films. There is a MONOS type to store.

  A floating gate type nonvolatile memory cell uses a transistor having a two-layer gate electrode in which a control gate is superimposed on a floating gate. By applying a high voltage to the control gate, electrons are injected from the substrate into the floating gate to hold the charge.

  The MONOS type nonvolatile memory cell has a gate having a MONOS (metal / oxide film / nitride film / oxide film / silicon) structure. Electrons or holes are injected into trap levels existing in the oxide film / nitride film / oxide film (tunnel oxide film) structure, and charges are accumulated and held. The MONOS type is advantageous in terms of miniaturization because it uses a thinner oxide film than the oxide film thickness between the floating gate and the silicon substrate in the floating gate type. In addition, since the charge trapping centers in the silicon nitride film are spatially discrete, charges of electrons and holes are accumulated locally.

In addition, as a technique regarding such a non-volatile semiconductor memory, the technique etc. which are described in patent documents 1-4 are mentioned, for example.
Japanese Unexamined Patent Publication No. 1-111397 JP 60-95794 A JP 2006-24309 A JP-A-2005-332502

  By the way, as a result of examination of the nonvolatile memory technology as described above by the present inventors, the following has been clarified.

  For example, as an erasing / writing method for an IC card equipped with a two-transistor MONOS memory cell, there is an example of a two-element / bit nonvolatile memory of a MONOS memory cell and a switch MOS transistor. In this method, when a low threshold voltage of a nonvolatile memory having two levels of threshold voltages is desired, a voltage for making the threshold voltage low is applied to the gate electrode. Alternatively, when a high threshold voltage is desired, a voltage for setting a high threshold voltage is applied to the gate electrode. The low threshold voltage is a depletion mode in which the threshold voltage of the memory cell transistor is a negative voltage, but the threshold voltage of the switch MOS transistor is an enhancement mode in which the threshold voltage is a positive voltage. Since the current is cut off, overcurrent does not cause a problem even when the non-selection voltage applied to the gate electrode of the memory cell transistor is 0V. Therefore, it is possible to apply a voltage for setting a low threshold voltage to the gate electrode for a time sufficient for the memory cell transistor to enter the depletion mode. However, in a single element / bit type nonvolatile memory having only MONOS type memory cells, an overcurrent flows not only during selective reading but also during non-selection in the depletion mode. It is impossible to perform selective reading by applying.

  Further, there is a technique described in Patent Document 1 as an erasing method for a one-element / bit type nonvolatile memory. Patent Document 1 relates to a threshold voltage setting method for a floating gate type nonvolatile semiconductor memory having two levels of threshold voltages. When a low threshold voltage is desired, a voltage application for a high threshold voltage is performed before voltage application for a low threshold voltage. Alternatively, when a higher threshold voltage is desired, voltage application for lower threshold voltage is performed before voltage application for higher threshold voltage. However, in this method, the memory element is a floating gate element, and the threshold voltage of two levels is limited to the enhancement mode in order to apply 0 V to the gate electrode as a non-selection voltage.

  Further, there is a technique described in Patent Document 2 as a voltage setting method at the time of reading from a one-element / bit type nonvolatile memory. The technique described in Patent Document 2 is a 1 element / bit type nonvolatile memory, and when an erased bit is in a depletion mode, a voltage (negative voltage) lower than the threshold voltage is applied to a non-selected read word line, This prevents overcurrent from flowing. However, when the erasing operation (the voltage applying operation for setting the threshold voltage of the memory cell transistor to a low threshold voltage) is continuously performed, the threshold voltage gradually decreases and falls below the unselected read word line potential. There is a possibility, but it does not mention how to avoid this.

  Further, there is a technique described in Patent Document 3 as a program method for a one-element / bit type nonvolatile memory. The technology described in Patent Document 3 is a 1 element / bit type non-volatile memory, and a short write (Pre-Write) is performed before erasure so that the threshold voltage does not decrease even if erasure is continuously performed. It is a program system. Thereby, it is possible to solve the problem of the technique described in Patent Document 2. However, since the Pre-Write operation is added, the program time becomes longer.

  Moreover, there exists a technique of patent document 4 as Flash-Single-MONOS. The technique described in Patent Document 4 is applied between a non-selected data line and a well within a range in which erroneous writing does not occur because the transistor of the non-selected memory cell is turned on to prevent erroneous erasure of the non-selected memory cell. The voltage to be minimized. However, there is no mention of improvement of retention characteristics or the need for Pre-Write.

  Accordingly, an object of the present invention is to provide a technique capable of improving data retention characteristics in a nonvolatile semiconductor memory having a MONOS type memory cell using a nitride film as a charge storage layer.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, the nonvolatile semiconductor memory according to the present invention performs a weak write operation (Post-Weak-Write) after a normal erase operation when erasing data. The weak write operation refers to an operation of performing writing with an applied voltage lower than that in normal writing, or an operation of performing writing by applying a voltage in a short time.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) Data retention characteristics on the erase side are improved by weak writing after the erase operation.

  (2) Due to weak writing after the erasing operation, fluctuations in the threshold voltage when the erasing operation is continuously performed can be suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  1 is a cross-sectional view showing a schematic configuration of a MONOS type memory cell in a nonvolatile semiconductor memory according to an embodiment of the present invention, FIG. 2 is an energy band diagram of the MONOS type memory cell, and FIG. 3 is a write to the MONOS type memory cell. It is a figure which shows the drain current characteristic of a state and an erased state.

  First, an example of a schematic configuration of a MONOS type memory cell in the nonvolatile semiconductor memory according to the present embodiment will be described with reference to FIG. The nonvolatile semiconductor memory according to the present embodiment is a nonvolatile semiconductor memory such as an EEPROM or a flash memory. This nonvolatile semiconductor memory is formed on a single semiconductor chip by a well-known semiconductor manufacturing technique, and a plurality of MONOS type memory cells as shown in FIG. 1 are arranged in a matrix to form a memory array. Each memory cell is connected to a word line and a bit line, and is controlled by a peripheral circuit such as an address decoder arranged at the periphery of the memory array, and data writing / erasing and reading are performed on each memory cell. Is called.

This MONOS type memory cell has a cross-sectional structure as shown in FIG. 1, for example, a gate 101 such as polycrystalline silicon (Poly-Si), a top oxide film (Top-SiO ₂ ) 102, discrete trapping centers. Field-effect transistor comprising a silicon nitride film (Tapping-Si ₃ N ₄ ) 103 having a gate electrode, a tunnel oxide film (Tunnel-SiO ₂ ) 104, an n-type diffusion layer 105 serving as a source / drain, a channel formation region 106, and the like (FET). In this MONOS memory cell, an n-type diffusion layer 105 and a channel formation region 106 are formed on a p-well 107 formed on a semiconductor substrate such as silicon. A tunnel oxide film 104 having a thickness of 2 nm or less is formed on the channel formation region 106. A silicon nitride film 103 in which electrons / holes are accumulated is formed on the tunnel oxide film 104. A top oxide film 102 for insulating the silicon nitride film 103 and the gate 101 is formed on the silicon nitride film 103. On the top oxide film 102, a gate 101 for controlling data writing / erasing and reading is formed. The total thickness of the top oxide film 102, the silicon nitride film 103, and the tunnel oxide film 104 is about 20 nm, and has a very thin structure as compared with the floating gate type memory cell. Further, the tunnel oxide film 104 is very thin as about 1.8 nm, and as shown in FIG. 2, both electrons and holes are locally trapped in the silicon nitride film 103, and the electrons and holes hardly move.

  Data writing / erasing in the MONOS type memory cell is performed by injecting charges (electrons / holes) from the p-well 107 side through the tunnel oxide film 104 by an electric field applied between the gate 101 and the p-well 107, and a silicon nitride film. Charges are trapped in the spatial discrete trap centers in 103. Electrons are injected into the silicon nitride film 103 by applying a positive voltage to the gate 101 in the write operation, and holes are injected into the silicon nitride film 103 by applying a negative voltage to the gate 101 in the erase operation. The As shown in FIG. 3, the data read is performed by maintaining the gate 101 and the p-well 107 at 0 V bias, detecting the presence or absence of a channel current flowing between the source and drain, and writing state “0” and erasing state “1”. Is determined. That is, when the silicon nitride film 103 traps electrons or holes, the threshold voltage of the memory cell having the FET structure changes, and the change in the threshold voltage is read by the channel current.

  There are two types of writing methods for the memory cell, a method using an FN tunnel phenomenon and a method using a hot carrier, and either of them may be used. A method using the FN tunnel phenomenon is a method in which a voltage is applied between the gate 101 and the p-well 107 or between the gate 101 and the source or drain (n-type diffusion layer 105) to use the FN tunnel phenomenon to form silicon. This is a method of changing the threshold voltage by injecting or releasing electrons / holes into the nitride film 103. On the other hand, in the method using hot carriers, hot carriers (electrons / holes) generated in the channel by flowing current between the source and drain (n-type diffusion layer 105) with a high voltage applied to the gate 101 are converted into silicon. In this method, the threshold voltage is changed by being injected into the nitride film 103.

  In the nonvolatile semiconductor memory according to the present embodiment, a weak write operation (Post-Weak-Write) is performed after a normal erase operation when erasing data. The weak write operation refers to an operation of performing writing with an applied voltage lower than that in normal writing, or an operation of performing writing by applying a voltage in a short time.

  That is, a negative voltage is applied to the gate 101 in the erase operation and holes are injected into the silicon nitride film 103, and then a positive voltage lower than normal writing is applied to the gate 101, and the threshold voltage does not change excessively. Weak writing is performed, and electrons are injected into the silicon nitride film 103. For example, for normal writing, a voltage of 12 V is applied to the gate 101 for 1 ms, for erase, a voltage of −10 V is applied to the gate 101 for 1 ms, and for weak writing, a voltage of 4 to 6 V is applied to the gate 101 for 0.1 ms.

  FIG. 4 is a diagram showing changes in the threshold voltage of the memory cell when weak writing is performed after erasing and when only erasing is performed. In FIG. 4, the vertical axis indicates the threshold voltage (Vth) of the memory cell, and the horizontal axis indicates the standing time (s). Further, the erase voltage application is -10 V, 1 ms, one shot, and the weak write voltage application is 4 V, 0.1 ms, one shot. As shown in FIG. 4, compared with the case where only erasing is performed and left unattended, when weak writing (Post-Week-Write) is performed after erasing, the initial threshold voltage becomes a low voltage as an absolute value, but is reversed at a certain time. However, the fluctuation of the threshold voltage is reduced, and as a result, the shelf life is extended by about two digits, and the data retention characteristics are improved.

  Next, the reason why the data retention characteristic is improved when the weak write (Post-Weak-Write) is performed after erasing to reduce the variation of the threshold voltage.

5A and 5B are diagrams showing charge distribution and trap density in the silicon nitride film, where FIG. 5A shows the case where the charge is an electron (after writing), and FIG. 5B shows the case where the charge is a hole (after erasing). . In FIG. 5 (a), the amount _(n e) of an electronic ordinate trapped (Trapped-electrons), the horizontal axis is the distance from the tunnel oxide film interface of the silicon nitride film, _{t c} is injection centroid (Charge -Centroid). In FIG. 5B, the vertical axis represents the amount (n _h ) of trapped holes (trapped-holes), and the horizontal axis represents the distance from the tunnel oxide film interface in the silicon nitride film.

  After writing, as shown in FIG. 5A, the electrons are distributed in a box shape in the silicon nitride film and trapped deep. On the other hand, after erasing, as shown in FIG. 5B, the holes are distributed in the interface local (exp) type in the silicon nitride film and are trapped only in a shallow place.

  FIG. 6A is a diagram showing a charge distribution model in the silicon nitride film in the case of conventional erasing only (no weak writing after erasing), and FIG. 6B is a diagram after erasing in the present embodiment. It is a figure which shows the distribution model of the electric charge in a silicon nitride film in case with weak writing.

  As shown in FIG. 6A, in the case of only erasing, it is uncertain whether holes are accumulated in the vicinity of the tunnel oxide film 104 interface in the silicon nitride film 103 and electrons are accumulated in the silicon nitride film. is there. When left in this state for a long time, holes are spontaneously emitted by the self electric field of the holes. Alternatively, since the electric field strength applied to the tunnel oxide film 104 is relatively high, electrons generated in the channel formation region 106 are injected into the silicon nitride film due to the FN tunnel phenomenon, and holes and electrons are electrically neutralized.

  On the other hand, as shown in FIG. 6B, when weak writing (Post-Weak-Write) is performed after erasing, electrons penetrate deep into the silicon nitride film 103 and are trapped. The electron Coulomb attractive force suppresses the release of holes in the silicon nitride film 103. Further, since the Coulomb repulsive force of electrons in the silicon nitride film 103 and the electric field strength applied to the tunnel oxide film 104 are alleviated, electrons in the p well 107 enter the silicon nitride film 103 and recombine with holes. To be prevented. Therefore, even if the initial threshold voltage is shallow, the data retention characteristic (retention characteristic) when left for a long time is improved. As described above, in the MONOS type nonvolatile memory in which both electrons and holes are accumulated in the charge accumulation layer, since the trap distribution of electrons and holes is different, it is possible to extend the neglected life. Such a phenomenon is a phenomenon that cannot be seen in a floating gate type nonvolatile memory using polycrystalline silicon as a charge storage layer.

  Next, an effect of avoiding the over-erase problem in continuous erasure (continuous “1” program) by adding weak writing after erasing will be described.

  FIG. 7 is a diagram showing a sequence of writing (“0” program) and erasing (“1” program) of a nonvolatile memory according to the conventional method, and FIG. 8 shows applied voltage pulses for continuous erasure (continuous “1” program). FIG.

  As shown in FIG. 7, writing (“0” program) of the conventional nonvolatile memory is realized by a two-stage sequence by performing writing (Write) after erasing (Erase). In addition, the conventional method of erasing the nonvolatile memory ("1" program) is realized in a two-stage sequence after erasing (erasing) and then performing write-inhibiting (not erasing and writing). Was. However, in this method, as shown in FIG. 8, when erasure (“1” program) is continued, the threshold voltage gradually decreases and the problem of over-erasure occurs.

  FIG. 9 is a diagram showing a sequence of writing (“0” program) and erasing (“1” program) of a nonvolatile memory to which programming before erasing (Pre-Write) is added in order to avoid the problem of over-erasing. FIG. 10 is a diagram showing applied voltage pulses for continuous erasure (continuous “1” program).

  As shown in FIGS. 9 and 10, by adding writing (Pre-Write) before erasing, the problem of over-erasing due to continuous erasing is avoided. In other words, writing (“0” program) is performed in a three-stage sequence by writing (Pre-Write), erasing (Erase), and then writing (Write). In the erase ("1" program), after writing (Pre-Write), erasing (Erase) is performed, and then writing-inhibiting (Write-inhibit) is performed (not erased and written). This sequence is realized. Therefore, even if erasure (“1” program) continues as shown in FIG. 10, the threshold voltage falls below a predetermined voltage because writing (Pre-Write) is performed before erasing (Erase). This eliminates the problem of over-erasing. This is because the amount of electrons injected into the silicon nitride film 103 is limited in accordance with the voltage intensity applied to the tunnel oxide film 104 immediately before performing pre-write. The voltage application in this case is, for example, writing (Write) at a voltage of 12 V, time 1 ms, writing (Pre-Write) at a voltage of 12 V, time of 0.1 ms, and erasing (Erase) at a voltage of -10 V, and time of 1 ms.

  FIG. 11 is a diagram showing fluctuations in threshold voltage Vth (comparison of presence / absence of Pre-Write) due to continuous erasure. In FIG. 11, the vertical axis represents the threshold voltage Vth, and the horizontal axis represents the number of erases. A waveform 1101 indicates a case where there is no writing (Pre-Write) before erasing, and a waveform 1102 indicates a case where there is a writing before erasing (Pre-Write). As shown in FIG. 11, in the case of the conventional method without the pre-erase write (Pre-Write) shown in FIGS. 7 and 8, the threshold voltage Vth gradually decreases as the erase (Erase) continues. To go. However, when the pre-erase write (Pre-Write) shown in FIGS. 9 and 10 is present (1102), the threshold voltage Vth does not drop below a predetermined voltage even if erase is continued.

  As described above, by adding writing before erasing (Pre-Write), it is possible to avoid the problem of over-erasing of continuous erasing (continuous “1” program) of the nonvolatile memory. The total time (total program time) will increase.

  Therefore, in this embodiment, weak writing after erasing is performed without performing writing before erasing (Pre-Write).

  FIG. 12 shows a sequence of writing (“0” program) and erasing (“1” program) of a nonvolatile memory that performs weak writing (Post-Week-Write) after erasing in order to avoid the problem of over-erasing. FIGS. 13 and 13 are diagrams showing applied voltage pulses for continuous erasure (continuous “1” program).

  As shown in FIGS. 12 and 13, by performing weak writing (Post-Weak-Write) after erasing at the time of erasing (“1” program), the problem of over-erasing due to continuous erasing can be avoided. . That is, the write (“0” program) is realized in a two-stage sequence by performing write (Write) after performing erase (Erase). In addition, erasure (“1” program) is realized in a two-stage sequence by performing erasure (Erase) and then performing weak write (Post-Weak-Write).

  As a specific control, when erasing (“1” program) is performed on all of the plurality of memory cells connected to the word line, writing (Write) to the word line is performed as weak writing (Post-Weak-Write). This can be done by applying a voltage lower than that in the case of performing writing, or by applying it for a shorter time than in the case of performing writing at a voltage comparable to the case of performing writing (Write). Alternatively, the same voltage as that for writing may be applied to the word line for the same time, and a period during which write-inhibit is not performed and a period during which write is blocked may be provided during the application period.

  In addition, when control is performed so that a part of the memory cells connected to the word line is written (Write) and the remaining memory cells are not written (Write), the word line During the period in which the voltage for performing writing is applied, a period in which write inhibition (write-inhibit) is not performed and a period in which write inhibition is performed may be provided for the remaining memory cells to which writing is not performed. Electrons are also injected into the silicon nitride film 103 of the remaining memory cells where writing is not performed during a period when writing is not blocked, but the silicon nitride film 103 of the memory cell where writing is performed is included by including the period during which writing is blocked. Since electrons smaller than the amount of electrons injected into the substrate are injected, weak writing can be realized.

  Therefore, even if erasure (“1” program) continues as shown in FIG. 13, the threshold voltage does not drop because weak write (Post-Week-Write) is performed after erase (Erase). This eliminates the problem of over-erasing. Further, since it is realized by a two-stage sequence, the total time for writing and erasing is the same as that of the conventional method. The reason why the threshold voltage does not decrease is as described above. The voltage application in this case is, for example, writing (Write) at a voltage of 12V, time of 1 ms, weak writing (Post-Weak-Write) at a voltage of 4 to 6 V, time of 0.1 ms, and erasing (Erase) at a voltage of -10 V, time. 1 ms.

  FIG. 14 is a diagram showing fluctuations in threshold voltage Vth (comparison between presence / absence of pre-write and presence / absence of post-weak-write) due to continuous erasure. In FIG. 14, the vertical axis represents the threshold voltage Vth, and the horizontal axis represents the number of erases. Waveform 1401 indicates that there is no write before erasure (Pre-Write) or weak write after erasure (Post-Wake-Write). Waveform 1402 indicates that there is write before erasure (Pre-Write). Waveform 1403 indicates that after erasure. The case where there is a weak write (Post-Weak-Write) is shown. As shown in FIG. 14, in the case of the conventional method shown in FIG. 7 and FIG. 8 (1401), the threshold voltage Vth gradually decreases as erasing continues. However, in the case of the non-volatile semiconductor memory according to the present embodiment (1403), during erase (“1” program), weak write (Post-Wake-Write) is performed after erase (Erase). Even if it continues, the threshold voltage Vth does not continue to decrease and maintains a constant value.

  Therefore, according to the non-volatile semiconductor memory of the post-erase weak write (Post-Weak-Write) method according to the present embodiment, the total write / erase time (program time) remains the same as that of the conventional method, and the threshold value at the time of continuous erase A decrease in voltage can be suppressed.

  Therefore, according to the nonvolatile semiconductor memory of the present embodiment, the following operations and effects can be obtained. In the case of a MONOS type memory cell, holes are accumulated in the ONO film (oxide film-nitride film-oxide film) on the erasing side, data is retained, and the threshold voltage fluctuates by leaving these holes when left unattended. . If the release of the holes is delayed, the data retention characteristics are improved. When writing is performed so as to prevent the threshold voltage from rising excessively after erasing and the electrons are accumulated, the Coulomb attraction by the electrons slows the detachment of holes, and the data retention characteristics are increased. Improve. In addition, the Coulomb repulsion of electrons in the silicon nitride film prevents electrons in the substrate from entering the silicon nitride film and recombining with holes, thereby improving data retention characteristics.

  In addition, this weak writing after erasing (Post-Weak-Write) can suppress the fluctuation of the threshold voltage even if the erasing is performed continuously or without the writing before the erasing (Pre-Write).

  Although the invention made by the present inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the scope of the invention. Needless to say.

  The present invention is effective for a semiconductor memory, particularly a nonvolatile memory, and is particularly effective for a MONOS nonvolatile memory, a microcomputer equipped with a MONOS nonvolatile memory, and the like.

1 is a cross-sectional view showing a schematic configuration of a MONOS type memory cell in a nonvolatile semiconductor memory according to an embodiment of the present invention. It is an energy band figure of a MONOS type memory cell. It is a figure which shows the drain current characteristic of the write-in state and erasure | elimination state to the MONOS type | mold memory cell in the non-volatile semiconductor memory by one Embodiment of this invention. It is a figure which shows the change of the threshold voltage of a memory cell when weak writing is performed after erasing and when only erasing is performed. (A), (b) is a figure which shows the electric charge distribution and trap density in the silicon nitride film of a MONOS type | mold memory cell, (a) is a case where an electric charge is an electron (after writing), (b) is an electric charge positive. The case of holes (after erasure) is shown. (A) is a figure which shows the distribution model of the electric charge in the silicon nitride film of the MONOS type | mold memory cell in the case of only the conventional erasing (there is no weak writing after erasing), (b) is one Embodiment of this invention 3 is a diagram showing a charge distribution model in a silicon nitride film of a MONOS type memory cell in the case where there is weak writing after erasing in FIG. It is a figure which shows the sequence of the writing ("0" program) and the erasure | elimination ("1" program) of the non-volatile memory by a conventional system. It is a figure which shows the applied voltage pulse of the continuous erase (continuous "1" program) of the non-volatile memory by a conventional system. FIG. 10 is a diagram showing a sequence of writing (“0” program) and erasing (“1” program) of a nonvolatile memory to which writing before erasing (Pre-Write) is added in order to avoid the problem of over-erasing. It is a figure which shows the applied voltage pulse of continuous erasure | elimination (continuous "1" program) of the non-volatile memory which added the write (Pre-Write) before erasure in order to avoid the problem of over erasure. It is a figure which shows the fluctuation | variation (comparison of the presence or absence of Pre-Write) of the threshold voltage Vth by continuous erasure | elimination of a non-volatile memory. In one embodiment of the present invention, writing (“0” program) and erasing (“1” program) of a non-volatile memory that performs weak writing (Post-Weak-Write) after erasing in order to avoid the problem of over-erasing FIG. In one embodiment of the present invention, an applied voltage pulse for continuous erasure (continuous “1” program) of a non-volatile memory that performs weak write (Post-Weak-Write) after erasure in order to avoid the problem of over-erasure. FIG. It is a figure which shows the fluctuation | variation (comparison with / without Pre-Write, with Post-Weak-Write) of the threshold voltage Vth by continuous erasure | elimination of a non-volatile memory.

Explanation of symbols

101 Gate 102 Top oxide film (Top-SiO ₂ )
103 Silicon nitride film (Tapping-Si ₃ N ₄ )
104 Tunnel oxide film (Tunnel-SiO ₂ )
105 n-type diffusion layer 106 channel formation region 107 p-well

Claims (5)

A nonvolatile semiconductor memory including a memory cell having a nitride film as a charge storage layer,
When writing data, a first voltage is applied to the gate electrode of the memory cell for a first time;
During data erasing, a second voltage lower than the first voltage is applied to the gate electrode of the memory cell for a second time, and then a third voltage lower than the first voltage and higher than the second voltage. A nonvolatile semiconductor memory, wherein a voltage is applied to the gate electrode of the memory cell for a third time. The nonvolatile semiconductor memory according to claim 1,
The first voltage and the third voltage are positive voltages;
The non-volatile semiconductor memory, wherein the second voltage is a negative voltage. The nonvolatile semiconductor memory according to claim 1,
The memory cell is a field effect transistor formed on a semiconductor substrate,
A source electrode, a drain electrode, and a channel formation region between the source electrode and the drain electrode,
The charge storage layer is disposed on the channel formation region,
The non-volatile semiconductor memory, wherein the gate electrode is disposed on the charge storage layer. The nonvolatile semiconductor memory according to claim 1,
The non-volatile semiconductor memory, wherein the third time is shorter than the first time. The nonvolatile semiconductor memory according to claim 1,
The non-volatile semiconductor memory, wherein the second voltage is applied to the gate electrode of the memory cell before the first voltage is applied to the gate electrode of the memory cell during the data writing.

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