JPH1055689A - Erasing method for flash memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce damage for a tunnel oxide film and to reduce dispersion of threshold voltage after erasing without reducing allowance on design of cell constitution, in an erasing method for a stack type flash memory. SOLUTION: After the prescribed high voltage is applied to a source electrode 2 and electrons (e) accumulated in a floating gate 5 is extracted in a state in which a drain electrode 3 is opened and a control gate 7 is grounded, that is, after FN erasing, drain voltage VD at the normal write is applied to the drain electrode 3 in a state in which the source electrode 2 is grounded, also writing voltage Vpp being lower than voltage at the normal write is applied to a control gate 7, and electrons (e) (hot electron) is injected to the floating gate 5. As injection of hot electron is performed with less damage for a tunnel oxide film and for comparatively a short time, an over-erasing cell can be relieved without reducing allowance on design of cell construction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an erasing method for a flash memory which is a read-only memory which can be electrically erased in a batch, and more particularly to an improvement in an erasing method suitable for use in a stack type flash memory.

[0002]

2. Description of the Related Art At present, a stack type flash memory which does not use a select gate is mainly used as such a flash memory. FIG. 6 shows an outline of a cell (transistor) structure of the stack type flash memory.

That is, in FIG. 6, FIG. 6A shows a cross-sectional structure of a stack type flash memory viewed from the gate length direction, and FIG. 6B shows the same stack type flash memory viewed from the gate width direction. 2 shows a cross-sectional structure of a memory.

[0006] As shown in FIG. 6, in the stack type flash memory, basically, two gate electrodes called a floating gate and a control gate substantially overlap each other via an insulating film. It is deposited and formed on a semiconductor substrate. The specific structure will be described below.

A P-type single crystal silicon substrate 1 as a semiconductor substrate has a source region (source electrode) 2 composed of an N + type impurity diffusion region and a drain region (drain electrode) also composed of an N + type impurity diffusion region. 3) are formed for each cell. Although not shown in FIG. 6, the source region 2 of each cell is electrically connected in common.

A floating gate (floating gate electrode) 5 made of polycrystalline silicon is formed on the silicon substrate 1 via a thin silicon oxide film (tunnel oxide film) 4 as an insulating film. As shown in FIG. 6A, the floating gate 5 extends in a rectangular shape in such a manner that a part of the floating gate 5 extends to both the source region 2 and the drain region 3 when viewed from the length direction of the gate. Is established. In addition,
The silicon oxide film (tunnel oxide film) 4 shown in FIG.
As shown in (b), it is connected to the LOCOS oxide film.

On the other hand, a band-like control gate (control gate electrode) 7 also made of polycrystalline silicon is provided on the floating gate 5 via a silicon oxide film (inter-gate insulating film) 6 as an insulating film. Deposits are formed. As described above, the control gate 7 is formed so as to substantially overlap the floating gate 5 as viewed from the length direction of the gate.

Then, including the periphery of the control gate 7,
A silicon oxide film 8 as an insulating film is deposited and formed on a silicon substrate 1, and the drain region 3 is electrically connected to a wiring made of aluminum or the like through a contact hole (not shown) opened in a part thereof. Will be done.

Next, the principle of the write operation and the erase operation of the stack type flash memory having such a cell structure will be described with reference to FIGS. 7 and 8, respectively.

In the stack type flash memory,
As shown in FIG. 7, the write operation is performed while the source electrode 2 is grounded and the drain electrode 3 and the control gate 7 are connected.
And the voltage VD and the voltage Vpp are applied simultaneously, respectively.
This is performed by injecting electrons into the floating gate 5.

That is, at this time, the drain voltage V
By applying D and a write voltage (gate voltage) Vpp, hot electrons generated in the vicinity of the drain region 3 are injected into the floating gate 5, and writing is performed.

At this time, the above voltage is applied as a pulse signal having a fixed time width, and the write operation is terminated when the threshold voltage Vt of the cell reaches a predetermined voltage. When a large number of memory cells are arranged, such a write operation is performed for each bit (each cell).

On the other hand, in the stack type flash memory, as shown in FIG. 8, the erase operation is performed on the source electrode 2 with the drain electrode 3 electrically open and the control gate electrode 7 grounded. F generated between the source region 2 and the floating gate 5 when a predetermined high voltage is applied
This is performed using N (Fowler-Nordheim) current.

That is, at this time, the electrons accumulated in the floating gate 5 are released by the flow of the FN current, and the erasing is performed. At this time, the threshold voltage Vt of the cell decreases. In a flash memory, such an erasing operation is performed collectively for all bits or in units of blocks.

FIG. 9 shows an erasing method generally used in such a stack type flash memory. That is, in the same erasing method, erasing is performed for all bits at once or in units of blocks by performing the following processing. (1) Before erasing, first, as shown in the process of step S200, all-bit writing is performed to reduce the variation in the threshold voltage Vt. That is, the threshold voltages Vt of all the cells are aligned in a high state. (2) Thereafter, step S201 and step S202
As shown in the above processing, the erasing using the FN current and the erase verify (verification) are repeated, and the electrons accumulated in the floating gate 5 are gradually extracted. (3) As a result, when the threshold voltage Vt of the slowest erased cell in the memory cell array reaches the set value, the erase is completed.

[0016]

As described above, in the case of a flash memory, the above erasing operation is performed for all bits at once.
Alternatively, it is performed in block units. By abandoning erasing in units of bits or bytes, a cell size similar to that of an ultraviolet-erasable EPROM with one transistor / cell has been realized, and the unit cost per bit has been significantly reduced.

However, in the stack type flash memory having a simple cell structure, the threshold voltage Vt of each cell at the time of performing the above-mentioned batch erasure greatly varies, which is an important subject in recent years.

In particular, a cell in an over-erased state which is normally on becomes a fatal defect, and when a cell on a bit line is read, if such an over-erased cell is present on the bit line, a write operation is performed. A cell in a state, ie, an off state, is erroneously determined to be an on state. This is because current flows through the over-erased cells.

In such a stack type flash memory, it has been found that the cause of the variation in the threshold voltage Vt after erasing is a variation in the ease with which the FN current flows.

In order to suppress the formation of an oxide film ridge (phosphorus deflection formed at the interface between the tunnel oxide film and the floating gate) which directly causes the variation of the threshold voltage Vt, Lower the temperature of the heat treatment. Reducing the phosphorus concentration in the polycrystalline silicon forming the gate; For example, although optimization of process conditions has been proposed, as the miniaturization progresses further, there is naturally a limit to the effect of suppressing the variation of the threshold voltage Vt only by optimizing such process conditions.

On the other hand, even if there is an over-erased cell, the following method is used to remedy it.
To inject avalanche hot carriers (Nikkei Microdevices February 1992, 85-91).
Page, The Institute of Electronics, Information and Communication Engineers IEICE technical report ICD93
-20, pp. 27-34, JP-A-7-161853). (Ii) FN erasing (electron erasure by FN current) for extracting electrons from the floating gate and FN injection (FN writing) for injecting electrons to the floating gate are performed in two stages (IEICE IEICE, IEICE). Technical report ICD93-29
Pages 35-41). Various methods have been conventionally proposed. According to these erasing methods, after the erasing is completed, the threshold voltage Vt
It has also been reported that the variation of is also suitably suppressed.

However, in the case of the above method (i), since the injection of hot holes (holes) into the floating gate cannot be avoided, damage to the tunnel oxide film cannot be ignored. Such damage to the tunnel oxide film greatly impairs the reliability of rewriting as a flash memory.

In the method (ii) described above, although the damage to the tunnel oxide film is small, the precision requirement for the cell structure when shortening the erasing time is extremely severe. That is, the margin in the cell structure design decreases with the speeding up of the erase operation.

The present invention has been made in view of such circumstances, and it is desirable to reduce the threshold voltage variation after erasing without reducing the damage to the tunnel oxide film and reducing the margin in designing the cell structure. It is an object of the present invention to provide a flash memory erasing method that can be reduced.

[0025]

In order to achieve the above object, according to the present invention, there is provided a semiconductor device, comprising: (a) opening the drain region and grounding the control gate with the control gate grounded; A first step of applying a predetermined high voltage to a region to extract electrons accumulated in the floating gate; (B) After that, while the source region is grounded, a predetermined voltage set so as to obtain a lower threshold voltage than at the time of normal writing is applied to the drain region and the control gate to inject electrons into the floating gate. The second step to be performed. Basically, the stack type flash memory is erased through two steps.

Here, the first step is a conventional erasure by the FN current. Conventionally, as described above, only erasing by the FN current has been performed.
As described above, only the erasing by the FN current causes a large variation in the threshold voltage of each cell, and an excessively erased cell is generated.

Therefore, in the first aspect of the present invention, the over-erased cells are relieved by executing the second step together. According to the second step of injecting hot electrons (channel hot electrons) into the floating gate by applying a voltage set so as to obtain a threshold voltage lower than that during normal writing to the drain region and the control gate, Since the hot hole injection is not performed as in the method (i), damage to the tunnel oxide film is small. -Since the writing speed is faster than the FN injection by the method (ii), the total erasing time can be easily reduced. In other words, the margin in the cell structure design does not decrease with the speeding up of the erase operation. With the advantages described above, it is possible to reduce the threshold voltage variation after the erasure.

Further, in the second step, unlike the collective erasing of all bits or blocks by the FN current, access in word units of 8 bits or 16 bits can be performed through the writing operation such as the injection of hot electrons. It becomes possible. Therefore, even when the over-erased cells are relieved, the influence of the characteristic variation between bits can be minimized, and the controllability of the threshold voltage is excellent.

According to the second aspect of the present invention, (b1) the voltage applied to the drain region in the second step is a drain voltage at the time of normal writing, and the control gate is supplied to the control gate in the second step. The applied voltage is set to a voltage lower than the writing voltage in normal writing. According to this method, by adjusting only the voltage applied to the control gate, it is possible to set a voltage relationship for obtaining a threshold voltage lower than that in the normal writing.

Still further, according to the invention described in claim 3, (b11) the voltage applied to the control gate in the second step includes a write characteristic and a write time of the memory element, and a voltage during the normal write. It is determined based on the threshold voltage after erasure aimed at as a lower threshold voltage. According to such a method, the optimal voltage application condition for suppressing the threshold voltage variation after erasing the memory cell, that is, the hot electron injection condition, is determined for each memory element, and higher accuracy is achieved. Threshold voltage control is realized.

On the other hand, according to the invention of claim 4, (c) applying a predetermined write voltage to each of the drain region and the control gate with the source region grounded before the first step. And adjusting the threshold voltages of all the memory cells to a high state. Such a method can also be adopted. Although the over-erased cells can be suitably rescued by the erasing method according to the first to third aspects, according to the erasing method having such steps, the generation of the over-erased cells to be remedied is minimized. Is expected to be suppressed.

[0032]

1 and 2 show an embodiment of a flash memory erasing method according to the present invention.

The erasing method of this embodiment is also applied to a stacked flash memory whose basic cell structure is illustrated in FIG. Hereinafter, a method of erasing the stacked flash memory according to the embodiment will be described in detail with reference to FIGS.

Now, even in the erasing method of the embodiment,
Prior to the erasing operation, first, all bits are written as the process of step S100. As described above, this all-bit writing is performed to keep the threshold voltages Vt of all the memory cells high.

When the writing of all bits is completed in this way, next, as the processing of steps S101 and S102, erasing and erasing verification (verification) are repeated, and electrons accumulated in the floating gate 5 are gradually extracted.

By the way, as shown in FIG. 2A, this erasing operation also electrically opens the drain electrode 3,
FN (Fowler-Nordheim) generated between the source region 2 and the floating gate 5 when a predetermined high voltage is applied to the source electrode 2 with the control gate electrode 7 grounded
This is done using current.

It is to be noted that such an erasing operation is performed collectively for all bits or in block units.
As described above, only the erasing by the N current causes a large variation in the threshold voltage Vt of each cell, and an excessively erased cell is generated.

Therefore, in the erasing method of the embodiment,
When the threshold voltage Vt of the slowest erased cell in the memory cell array reaches the set value, the low-voltage write and low-voltage write-verify are repeated as the processing in steps S103 and S104, to thereby overwrite the over-erased cells. Perform relief.

In this low-voltage writing, as shown in FIG. 2B, a threshold voltage Vt lower than that in normal writing is obtained in the drain electrode 3 and the control gate 7 with the source electrode 2 grounded. This is performed by applying a predetermined voltage set so as to allow hot electrons (channel hot electrons) to be injected into the floating gate 5.

At this time, in this embodiment, the voltage VD applied to the drain electrode 3 is set as the drain voltage at the time of normal writing, and the voltage Vpp applied to the control gate 7 is set.
Is set lower than the writing voltage at the time of normal writing, and a voltage relationship for obtaining a threshold voltage Vt lower than that at the time of normal writing is set. The manner of setting the voltage Vpp applied to the control gate 7 will be described in further detail with reference to FIG.

FIG. 3 shows that the drain voltage VD of one stack type flash memory device is set to 5.5 V.
(Volt), and the write characteristics when the write voltage (voltage applied to the control gate 7) Vpp is changed in the range of "9.0 to 12.5 V". In the graph of FIG. 3, the horizontal axis indicates the writing time, the right vertical axis indicates the threshold voltage Vt after writing, and the left horizontal axis indicates the difference between the threshold voltage after writing and before writing, that is, ΔVt. ΔVt = (threshold voltage Vt after writing) − (threshold voltage Vt before writing (= 2.0 V)). According to FIG. 3, it can be seen that the threshold voltage Vt after writing and the threshold voltage difference ΔVt after writing and before writing change almost linearly according to the value of the writing voltage Vpp.

In the erasing method of the embodiment, the voltage Vpp applied to the control gate 7 at the time of the low-voltage writing is used.
Is determined based on the write characteristics of such a memory element, the write time, and the value of the threshold voltage Vt after erasure aimed at as a threshold voltage lower than that in the normal write.

Assuming that the threshold voltage Vt after writing targeted at the time of normal writing is 6 to 8 V, the threshold voltage Vt after erasing aimed at as a threshold voltage lower than that at the time of normal writing is 1 to 4 V, that is, the normal. It is set to a value of about ８ to ／ of the threshold voltage Vt at the time of writing.

Therefore, in the element having the write characteristic illustrated in FIG. 3, the threshold voltage Vt after writing in the normal writing is selected to be, for example, "7 V".
Assuming that the write time is selected to be “20 μsec”, the write voltage Vpp is the voltage added as “A” in FIG. 3, that is, “Vpp = 12.0
V ".

On the other hand, the threshold voltage after writing at the time of the low-voltage writing, that is, the threshold voltage Vt after erasing is aimed at a value of, for example, 3 V, and the writing time is selected to be 2 μsec. As shown in FIG.
The voltage added as “B” therein, that is, “Vpp = 9.
0V "will be selected.

When the low voltage writing was actually performed under these conditions after the erasing by the FN current,
Conventionally, as shown in FIG. 4, when only the erasing by the FN current is performed, as shown in FIG. 4, the variation of the threshold voltage Vt which was about 2.0 V is shown in FIG. 5 after the execution of the low voltage writing. As described above, the voltage was suppressed to about 0.6V.

Further, since the operation related to the low-voltage writing is performed in units of words of 8 bits or 16 bits, unlike the batch erasing of all bits or blocks by the FN current, it is caused by the characteristic variation between bits. The controllability of the threshold voltage Vt is excellent, for example, the influence can be minimized. In other words, it can be said that the erasing method of the embodiment in which the over-erased cells are relieved through the low-voltage writing is an erasing method that is more advantageously applied as the memory capacity of the flash memory becomes larger.

In the erasing algorithm illustrated in FIG. 1, if sufficient erasure is ensured by the erasing by the FN current, the erasing verification in step S102 may be omitted.

Similarly, if the above-described low-voltage writing sufficiently guarantees the repair of the over-erased cells, an algorithm may be used in which the low-voltage writing verification in step S104 is omitted.

As described above, according to the erasing method of the flash memory according to the embodiment, (a) the relief of the over-erased cells by the low-voltage writing is also performed, so that the threshold voltage Vt after erasing is reduced. Is greatly suppressed. (B) Since the low voltage writing is performed by hot electron injection, damage to the tunnel oxide film 4 (see FIG. 6) by the method (i) is small. (C) Further, this hot electron injection is performed by the method (i).
Since the writing speed is faster than the FN injection by the method i), the total erasing time can be easily reduced. In other words, the margin in the cell structure design does not decrease with the speeding up of the erase operation. (D) Moreover, unlike the collective erasing of all bits or blocks by the FN current, the low-voltage writing is performed in word units of 8 bits or 16 bits.
The threshold voltage Vt after erasing can be controlled with high controllability. (E) In addition, the above-mentioned low voltage writing condition is determined by the control gate 7
Is set through adjustment of only the write voltage Vpp applied to. (F) Further, the write voltage Vpp for the low-voltage write is determined based on the write characteristics of the memory element, the write time, and the threshold voltage Vt after erasure which is aimed at as a threshold voltage lower than that in normal write. Thus, the over-erased cells can be relieved more accurately. Many excellent effects can be achieved.

In this embodiment, the control gate 7
The low voltage write condition is set by adjusting the write voltage Vpp applied to the drain voltage. The following conditions are set: (1) The drain voltage VD is adjusted. Adjust both the write voltage Vpp and the drain voltage VD. And so on. In short, the drain electrode 3
And the drain voltage V in a relationship such that a lower threshold voltage Vt is obtained in the control gate 7 than in normal writing.
It is sufficient that D and the write voltage Vpp are applied.

Further, according to the erasing method of the same embodiment, an extra erasing time is required for performing the above-described low-voltage writing as compared with the conventional erasing method shown in FIG. In the case of the erasing method of FIG.
The process for writing all bits indicated as 00 can be omitted.

That is, even if there are over-erased cells, they can be suitably rescued through the low-voltage writing process, so that even if the process related to the all-bit writing is omitted, the cells are substantially eliminated. Can maintain the same threshold voltage variation suppression effect. In this case, the erasing time can be reduced appropriately.

However, if the processing related to the all-bit writing is performed prior to the erasing operation, it is expected that the generation of the over-erased cells to be repaired will be minimized.

The erasing algorithm shown in FIG. 1 can be registered in advance in a flash memory chip to which the erasing algorithm is applied as an automatic erasing program. By employing such an erasing structure, the operation load of an external processor accessing the erasing structure is suitably reduced, and the smooth processing of the entire system is maintained.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating an embodiment of a flash memory erasing method.

FIG. 2 is an exemplary diagram schematically showing an erasing mode according to the embodiment;

FIG. 3 is a graph showing an example of write characteristics of a flash memory element.

FIG. 4 is a graph showing a distribution of a threshold voltage Vt according to a conventional erasing method.

FIG. 5 is a graph showing a distribution of a threshold voltage Vt according to the erasing method of the embodiment.

FIG. 6 is a sectional view showing a general cell structure of a stack type flash memory.

FIG. 7 is a schematic diagram schematically showing a writing mode of the stack type flash memory.

FIG. 8 is a schematic diagram schematically showing an erasing mode of the stack type flash memory.

FIG. 9 is a flowchart showing a conventional erasing method of the flash memory.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate (P type single crystal silicon substrate), 2 ... Source region (source electrode), 3 ... Drain region (drain electrode), 4 ... Tunnel oxide film (silicon oxide film), 5 ... Floating gate (Floating gate electrode) ), 6: inter-gate insulating film (silicon oxide film), 7: control gate (control gate electrode),
8. Insulating film (silicon oxide film).

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor ▲ Kuzu ▼ Takeshi Hara 1-1-1, Showa-cho, Kariya-shi, Aichi Prefecture Nippon Denso Co., Ltd.

Claims (4)

[Claims] A unit memory cell includes a source region and a drain region formed in a surface layer portion of a semiconductor substrate, and a floating gate and a control gate sequentially deposited on the surface of the semiconductor substrate via an insulating film. In the data erasing method for a flash memory configured, a predetermined high voltage is applied to the source region in a state where the drain region is opened and the control gate is grounded, and electrons accumulated in the floating gate are extracted. A first step, after which, while the source region is grounded, a predetermined voltage set so as to obtain a lower threshold voltage than at the time of normal writing is applied to the drain region and the control gate, and the floating gate is applied to the floating gate. 2. A method for erasing a flash memory, comprising: a second step of injecting electrons. 2. The method according to claim 2, wherein the voltage applied to the drain region in the second step is a drain voltage during normal writing.
2. The erasing method of a flash memory according to claim 1, wherein in the second step, a voltage applied to the control gate is lower than a writing voltage in normal writing. 3. A voltage applied to the control gate in the second step includes a write characteristic of the memory element, a write time, and a threshold voltage after erasing targeted as a threshold voltage lower than that in the normal write. 3. The method of erasing a flash memory according to claim 2, wherein the method is determined based on the following. 4. The erasing method for a flash memory according to claim 1, wherein prior to said first step, a predetermined voltage is applied to each of said drain region and said control gate with said source region being grounded. A method of erasing a flash memory, further comprising the step of applying a write voltage to adjust the threshold voltages of all memory cells to a high state.