CN1649115A - 一种多芯片集成电路封装方法及其结构 - Google Patents

一种多芯片集成电路封装方法及其结构 Download PDF

Info

Publication number
CN1649115A
CN1649115A CNA2004100159724A CN200410015972A CN1649115A CN 1649115 A CN1649115 A CN 1649115A CN A2004100159724 A CNA2004100159724 A CN A2004100159724A CN 200410015972 A CN200410015972 A CN 200410015972A CN 1649115 A CN1649115 A CN 1649115A
Authority
CN
China
Prior art keywords
chip
substrate
silicon chip
silicon
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2004100159724A
Other languages
English (en)
Other versions
CN100570844C (zh
Inventor
崔巍
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai high pass Semiconductor Co., Ltd
Original Assignee
JITONG DIGITAL SCIENCE AND TECHNOLOGY Co Ltd SHANGHAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JITONG DIGITAL SCIENCE AND TECHNOLOGY Co Ltd SHANGHAI filed Critical JITONG DIGITAL SCIENCE AND TECHNOLOGY Co Ltd SHANGHAI
Priority to CNB2004100159724A priority Critical patent/CN100570844C/zh
Publication of CN1649115A publication Critical patent/CN1649115A/zh
Application granted granted Critical
Publication of CN100570844C publication Critical patent/CN100570844C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明公开了一种多芯片集成电路封装方法及其结构，方法包括步骤：采用金属引脚框架作为多芯片封装的载体；采用硅片作为基板以形成硅片基板，在基板上设置芯片互连的布线；在金属引脚框架上置放硅片作为基板；在基板上叠放所要封装的多个芯片；将所要封装的多个芯片采用金线互连或连接到硅片基板上；再用金线将硅片基板和金属引脚框架相连接；将芯片、基板、金属引脚框架塑封于一体。依此方法而得到相应地封装结构突破了多芯片在系统封装只能采用球栅阵列封装形式的现状，实现了金属引脚的封装形式。同时也降低了对基板的生产工艺要求和封装成本，还灵活地拓宽了封装后的多芯片集成电路的功能。

Description

一种多芯片集成电路封装方法及其结构
技术领域
本发明涉及集成电路芯片的封装，更具体地指一种多芯片集成电路封装方法及其结构。
背景技术
目前，在对集成电路芯片封装中，将多个裸芯片互连为系统，并组装在单个封装内的“系统封装(SIP)”方案日益受到重视。虽然“片上系统(SOC)”方案能将多个芯片功能设计并制造在单个裸片上，也同样具有“系统封装(SIP)”在提供电路板安装密度和可靠性方面的优点，但与“系统封装(SIP)”相比，“片上系统(SOC)”方案存在设计周期长，研发费用高，难以将高频、高压等电路整合进去的局限，因此“系统封装(SIP)”由于不存在以上缺点而得迅速发展。
“系统封装”大多整合有CPU、’RAM、ROM、I/O等多个功能，系统内多芯片之间的复杂互连必须通过基板来实现，基板的作用与常见的安装电子元器件的印刷电路板完全相同。
在芯片封装中，迄今“系统封装”的基板均采用环氧树脂印刷电路板，只是比常见印刷线路板更小、更薄，布线更精细。在现有的数十种常用封装技术中，大致可分为二类：
第一类是采用金属(铜、镍)引脚框架的方案，如DIP、TSOP、QFP、PLCC等，此类方案，以金属引脚框架作为芯片载体，芯片1通过金线2与金属引脚框架3相联并向外引出(见图1)，塑封材料4将其密封。
第二类是采用非金属引脚的方案，如球栅阵列(BGA)，此类方案以微型印刷线路板作为芯片载体，芯片1通过金线2与印刷线路板5相连，并通过底部的焊球6引出(见图2)，并用塑封材料4将其密封。其优点是引出焊球分布在底面积上，与框架引脚只能在侧边上引出相比，具有密度高、尺寸小，能安排大量引脚。
多芯片封装中，出于温度系数匹配的限制，金属框架之上只能放置硅片，而不允许放置微型印刷线路板。因此迄今“系统封装”由于采用微型印刷线路板为互连基板，就只有采用球栅阵列(BGA)封装形式(图4中1为芯片，2为连接的金线，5为印刷线路板，6为焊球，4为塑封材料)，而不允许采用金属引脚封装形式。这就局限了“系统封装”芯片的应用范围，其局限在于很多能装配金属引脚芯片的整机厂并不具备安装采用球栅阵列封装的芯片的设备和能力；同时大量的低端电子产品出于降低安装密度、芯片成本和生产工艺要求的考虑，也不希望采用球栅阵列封装的芯片。如何解决多芯片的封装中存在的上述问题，一直困扰着业界人士。
发明内容
本发明的目的是针对多芯片封装存在的上述均采用微型印刷线路板为基板，只能实现球栅阵列封装的问题，提出一种多芯片集成电路封装方法及其结构，以使多芯片封装后的集成电路适用范围更加广阔。
为了实现上述目的，本发明采用如下技术方案：
该多芯片集成电路封装方法包括以下步骤：
a，采用金属引脚框架作为多芯片封装的载体；
b，采用硅片作为基板以形成硅片基板，并在硅片基板上设置芯片互连的布线；
c，在金属引脚框架上置放硅片基板；
d，在硅片基板上叠放所要封装的多个芯片；
e，将所要封装的多个芯片采用金线互连或连接到硅片基板上；
f，再用金线将硅片基板和金属引脚框架相连接；
g，将芯片、硅片基板、金属引脚框架塑封于一体。
该多芯片集成电路封装结构包括多个芯片、基板、金属引脚框架、塑封材料，所述的基板采用硅片材料形成硅片基板，在硅片基板设置芯片互连的布线，硅片基板置于金属引脚框架内；所述多个芯片置于硅片基板上，芯片与芯片之间、芯片与硅片基板之间通过金线相连接；所述的硅片基板与金属引脚框架之间也通过金线相连接；所述的塑封材料将多个芯片、硅片基板、金属引脚框架封装于一体。
在本发明的上述技术方案中，将硅片作为基板置入于金属引脚框架，而在硅片基板上叠放所要封装的多个芯片，多个芯片采用金线连接到基板上，再用金线将硅片基板和金属引脚框架相连接，并将芯片、硅片基板、金属引脚框架塑封于一体。由此所得到的多芯片集成电路封装结构，与传统采用球栅阵列封装结构相比，具有以下优点：
1、突破了多芯片在系统封装只能采用球栅阵列封装形式的现状，实现了金属引脚的封装形式。
2、也大大降低了对基板的生产工艺要求。
3、采用硅片做基板可以实现印刷线路板难以达到的更为复杂的系统互连。
4、采用硅片作为基板的成本要远低于常规用印刷线路板作为基板成本。
5、通过增加掩膜层数来灵活地拓宽了封装后的多芯片集成电路的功能。
附图说明
图1a和图1b分别为传统金属引脚框架单芯片封装结构剖视和仰视示意图。
图2a和图2b分别为传统的球栅阵列单芯片封装结构剖视和仰视示意图。
图3为传统的球栅阵列多芯片封装结构剖视示意图。
图4为本发明的多芯片的封装结构剖视示意图。
具体实施方式
本发明的多芯片集成电路封装方法包括以下步骤：
a，采用金属引脚框架作为多芯片封装的载体；
b，采用硅片作为基板以形成硅片基板，并在硅片基板上设置芯片互连的布线；
c，在金属引脚框架上置放硅片基板；
d，在硅片基板上叠放所要封装的多个芯片；
e，将所要封装的多个芯片采用金线互连或连接到硅片基板上；
f，再用金线将硅片基板和金属引脚框架相连接；
g，将芯片、硅片基板、金属引脚框架塑封于一体。
所述的步骤d中，在硅片基板上叠放多个芯片时，可将多个芯片叠放一层或几层。
当硅片基板上叠放的多个芯片叠放为一层时，在将同一层的芯片用金线相互连接，或将芯片用金线连接到硅片基板上；
当硅片基板上叠放的多个芯片叠放为几层时，上一层芯片均采用金线连接到硅片基板上或下层的芯片上。
硅片基板上共叠放多少层芯片、每一层放置多少芯片以及芯片之间的连接关系视所需要制作的具体集成电路而定。但一般来说，芯片连接后均要接到硅片基板上，然后再通过金线将硅片基板与金属引脚框架连接起来。
依本发明的上述方法所封装的多芯片集成电路封装结构请参阅图5所示，在该结构中，包括多个芯片1、金属引脚框架3、塑封材料4、基板7，所述的基板7采用硅片材料以形成硅片基板，在硅片基板7上设置芯片互连的布线，硅片基板7置于金属引脚框架3内；所述多个芯片1置于硅片基板7上，芯片1与硅片基板7之间通过金线2相连接；硅片基板7与金属引脚框架3之间也通过金线2相连接；所述的塑封材料4将多个芯片1、金属引脚框架3、硅片基板7封装于一体。
所述的多个芯片1呈一层或几层叠置于硅片基板7上。
当硅片基板7上叠置的多个芯片为一层时，同一层的芯片1通过金线相互连接，或将芯片1通过金线2连接到硅片基板7上；
当硅片基板7上叠置的多个芯片1叠放为几层时，上一层芯片1采用金线2连接到硅片基板7上或下层的芯片1上。
本发明上述方法和结构的优点叙述如下：
采用硅片作为“系统封装”的基板，从而使“系统封装”突破了只能采用球栅阵列封装形式的现状，实现了金属引脚的封装形式。
采用硅片作为基板，不仅使“系统封装”实现了金属引脚封装形式，也大大降低了对基板的生产工艺要求。基板目前采用的微型印刷线路板实际上和常见安装电子元器件的电路板属于相同的工艺和技术，其常规工艺所能做到的线宽和线距为4密尔(100um)，而基板对线宽和线距的要求为3密尔(75um)以下，已超过印刷线路板的工艺极限，因此其成本和工艺难度都大大增加了，通常其成本要占球栅阵列封装总成本的40％-50％。而硅片常规工艺所能做到的线宽和线距为0.6um(6寸晶圆)到1.2um(4寸晶圆)，即使硅片基板线宽和线距的密度比印刷线路板提高了50倍减到1.5um，也有极大的工艺富裕度，故可轻易地保证极高的合格率。同时由于硅片的布线密度比印刷线路板提高50倍以上，因此采用硅片做基板可以实现印刷线路板难以达到的更为复杂的系统互连。
在基板成本方面，虽然一般认为硅片单位面积成本要高于印刷线路板，但实际上，对芯片封装用的基板而言，微型印刷线路板成本要远高于常规印刷线路板，同时采用硅片做基板的成本要远低于常规集成电路，芯片成本是根据加工时掩膜的层数递增的，对于基板用硅片，只需双层布线，包括层间金属过孔和保护层只需4层掩膜即可，因此用于基板的硅片比微型印刷线路板实际要便宜一半以上。此外在基板成本允许时，可通过增加掩膜层数来灵活地增加基板功能，如加入电阻、简单逻辑或高电压转换等。
为了能更清楚地说明两者的差别，还可参阅下表，以进行基板分别采用微型印刷线路板与采用硅片后的性能对比：
  基板  金属引脚封装  常规工艺  基板实际工艺要求   工艺难度   布线密度   成本   增加功能
印刷线路板     NO   100um     75um   难   低 高   NO
硅片     YES   0.6um     1.5um   易   高 低   YES
在具体封装结构中，正如前述所知，硅片基板上共叠放多少层芯片、每一层放置多少芯片以及芯片之间的连接关系视所需要制作的具体集成电路而定。在图5所示意的实施例中，硅片基板上共叠放了二层芯片，上一层芯片有三块，与基板相邻的一层有两块，与硅片基板相邻的一层芯片各自均有金线连接到硅片基板上。上一层三块块芯片之间先相互连接，然后再用金线连接到基板上。可以很容易地理解，不同的集成电路的封装结构应该包括不同的功能和数量的芯片，以及芯片叠放于硅片基板上的层数和各芯片之间的连接关系。本发明主要核心是采用硅片作为基板来承载各种芯片并进行封装。本技术领域中的普通技术人员应当认识到，以上的实施例仅是用来说明本发明，而并非用作为对本发明的限定，只要在本发明的实质精神范围内，对以上所述实施例的变化、变型都将落在本发明权利要求书的范围内。

Claims (6)

1、一种多芯片集成电路封装方法，其特征在于，该方法包括以下步骤：
a，采用金属引脚框架作为多芯片封装的载体；
b，采用硅片材料作为基板以形成硅片基板，并在硅片基板上设置芯片互连的布线；
c，在金属引脚框架上置放硅片基板；
d，在硅片基板上叠放所要封装的多个芯片；
e，将所要封装的多个芯片采用金线互连或连接到硅片基板上；
f，再用金线将硅片基板和金属引脚框架相连接；
g，将芯片、硅片基板、金属引脚框架塑封于一体。
2、如权利要求1所述的多芯片集成电路封装方法，其特征在于：
所述的步骤d中，在硅片基板上叠放多个芯片时，可将多个芯片叠放一层或几层。
3、如权利要求1或2所述的多芯片集成电路封装方法，其特征在于：
当硅片基板上叠放的多个芯片叠放为一层时，在将同一层的芯片用金线相互连接，或将芯片用金线连接到硅片基板上；
当硅片基板上叠放的多个芯片叠放为几层时，上一层芯片均采用金线连接到硅片基板上或下层的芯片上。
4、一种多芯片集成电路封装结构，该封装结构包括多个芯片、基板、金属引脚框架、塑封材料，其特征在于：
所述的基板采用硅片材料形成硅片基板，在硅片基板设置芯片互连的布线，硅片基板置于金属引脚框架内；所述多个芯片置于硅片基板上，芯片与芯片之间、芯片与硅片基板之间通过金线相连接；硅片基板与金属引脚框架之间也通过金线相连接；塑封材料将多个芯片、硅片基板、金属引脚框架封装于一体。
5、如权利要求4所述的多芯片集成电路封装结构，其特征在于：所述的多个芯片呈一层或几层叠置于硅片基板上。
6、如权利要求4或5所述的多芯片集成电路封装方法，其特征在于：
当硅片基板上叠置的多个芯片为一层时，同一层的芯片通过金线相互连接，或将芯片通过金线连接到硅片基板上；
当硅片基板上叠置的多个芯片叠放为几层时，上一层芯片均采用金线连接到硅片基板上或下层的芯片上。
CNB2004100159724A 2004-01-19 2004-01-19 一种多芯片集成电路封装方法 Expired - Fee Related CN100570844C (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2004100159724A CN100570844C (zh) 2004-01-19 2004-01-19 一种多芯片集成电路封装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2004100159724A CN100570844C (zh) 2004-01-19 2004-01-19 一种多芯片集成电路封装方法

Publications (2)

Publication Number Publication Date
CN1649115A true CN1649115A (zh) 2005-08-03
CN100570844C CN100570844C (zh) 2009-12-16

Family

ID=34868165

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100159724A Expired - Fee Related CN100570844C (zh) 2004-01-19 2004-01-19 一种多芯片集成电路封装方法

Country Status (1)

Country Link
CN (1) CN100570844C (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102074540A (zh) * 2010-11-26 2011-05-25 天水华天科技股份有限公司 矩阵式dip引线框架、该框架的ic封装件及其生产方法
CN102368484A (zh) * 2011-10-11 2012-03-07 常熟市广大电器有限公司 一种多芯片集成电路封装结构
CN102944709A (zh) * 2011-08-16 2013-02-27 北京天中磊智能科技有限公司 多芯片系统级封装技术实现的电表模块结构及其封装方法
WO2013127035A1 (zh) * 2012-02-28 2013-09-06 Liu Sheng 扇出晶圆级半导体芯片三维堆叠封装结构及工艺
CN105097719A (zh) * 2014-05-21 2015-11-25 三菱电机株式会社 半导体装置、半导体装置的制造装置及半导体装置的制造方法、以及半导体模块
CN105895588A (zh) * 2014-12-30 2016-08-24 华天科技（西安）有限公司 一种多元件、铜框架和基板混装的封装结构及其制备方法
US9818727B2 (en) 2015-03-09 2017-11-14 Mediatek Inc. Semiconductor package assembly with passive device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102074540A (zh) * 2010-11-26 2011-05-25 天水华天科技股份有限公司 矩阵式dip引线框架、该框架的ic封装件及其生产方法
CN102074540B (zh) * 2010-11-26 2013-01-09 天水华天科技股份有限公司 矩阵式dip引线框架、该框架的ic封装件及其生产方法
CN102944709A (zh) * 2011-08-16 2013-02-27 北京天中磊智能科技有限公司 多芯片系统级封装技术实现的电表模块结构及其封装方法
CN102368484A (zh) * 2011-10-11 2012-03-07 常熟市广大电器有限公司 一种多芯片集成电路封装结构
WO2013127035A1 (zh) * 2012-02-28 2013-09-06 Liu Sheng 扇出晶圆级半导体芯片三维堆叠封装结构及工艺
CN103296014A (zh) * 2012-02-28 2013-09-11 刘胜 扇出晶圆级半导体芯片三维堆叠封装结构及工艺
CN105097719A (zh) * 2014-05-21 2015-11-25 三菱电机株式会社 半导体装置、半导体装置的制造装置及半导体装置的制造方法、以及半导体模块
CN105097719B (zh) * 2014-05-21 2018-02-06 三菱电机株式会社 半导体装置、半导体装置的制造装置及半导体装置的制造方法、以及半导体模块
US10008430B2 (en) 2014-05-21 2018-06-26 Mitsubishi Electric Corporation Semiconductor device, manufacturing apparatus for semiconductor device and manufacturing method for semiconductor device, and semiconductor module
US11417578B2 (en) 2014-05-21 2022-08-16 Mitsubishi Electric Corporation Semiconductor device, manufacturing apparatus for semiconductor device and manufacturing method for semiconductor device, and semiconductor module
CN105895588A (zh) * 2014-12-30 2016-08-24 华天科技（西安）有限公司 一种多元件、铜框架和基板混装的封装结构及其制备方法
US9818727B2 (en) 2015-03-09 2017-11-14 Mediatek Inc. Semiconductor package assembly with passive device
US10497678B2 (en) 2015-03-09 2019-12-03 Mediatek Inc. Semiconductor package assembly with passive device

Also Published As

Publication number Publication date
CN100570844C (zh) 2009-12-16

Similar Documents

Publication Publication Date Title
US8089143B2 (en) Integrated circuit package system using interposer
CN1193424C (zh) 半导体装置
CN1063579C (zh) 半导体装置
CN1881578A (zh) 叠层型半导体封装
CN1897240A (zh) 多芯片器件及其制造方法
CN1885536A (zh) 半导体封装
CN1092397C (zh) 高性能低成本的多芯片组件封装件
CN1496213A (zh) 用于减少多层电路板的层数的技术
DE102008003156A1 (de) Mehrchip-Packung und Verfahren zu ihrer Ausbildung
CN1934704A (zh) 芯片层叠型半导体装置
CN1204153A (zh) 半导体集成电路器件
CN1929130A (zh) 多芯片堆叠式封装结构
CN2711906Y (zh) 一种多芯片集成电路封装结构
KR20170127061A (ko) 적층된 반도체 디바이스를 상호연결하는 방법
WO2020112504A1 (en) Double side mounted large mcm package with memory channel length reduction
CN1649115A (zh) 一种多芯片集成电路封装方法及其结构
CN101043033A (zh) 半导体集成电路装置
KR101123804B1 (ko) 반도체 칩 및 이를 갖는 적층 반도체 패키지
CN103872004B (zh) 芯片结构及多芯片堆迭封装
CN102157402B (zh) 系统级封装方法
CN2854807Y (zh) 集成电路装置
CN1808711A (zh) 封装体及封装体模块
CN201994292U (zh) 高密度系统级封装结构
CN2872796Y (zh) 电子组装体
CN1790693A (zh) 倒装芯片及线接合半导体封装件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20170324

Address after: 200001 room B609 (3), Beijing East Road, Huangpu District, No. 666,

Patentee after: Shanghai high pass Semiconductor Co., Ltd

Address before: Shanghai City 200233 Tianzhou Road No. 99 Xin'an building room 1001

Patentee before: Jitong Digital Science and Technology Co., Ltd., Shanghai

TR01 Transfer of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20091216

Termination date: 20200119

CF01 Termination of patent right due to non-payment of annual fee