CN1647270A - 电子器件的制造方法以及电子器件 - Google Patents
电子器件的制造方法以及电子器件 Download PDFInfo
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- CN1647270A CN1647270A CNA038081172A CN03808117A CN1647270A CN 1647270 A CN1647270 A CN 1647270A CN A038081172 A CNA038081172 A CN A038081172A CN 03808117 A CN03808117 A CN 03808117A CN 1647270 A CN1647270 A CN 1647270A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 229910000679 solder Inorganic materials 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 14
- 239000004020 conductor Substances 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 43
- 238000007789 sealing Methods 0.000 claims description 18
- 238000009413 insulation Methods 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 239000004411 aluminium Substances 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000001816 cooling Methods 0.000 claims description 2
- 238000010257 thawing Methods 0.000 claims description 2
- 230000008901 benefit Effects 0.000 abstract description 6
- 238000005538 encapsulation Methods 0.000 abstract description 4
- 230000008021 deposition Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 16
- 230000005611 electricity Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 230000002349 favourable effect Effects 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000003292 glue Substances 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 235000011121 sodium hydroxide Nutrition 0.000 description 2
- 229920003002 synthetic resin Polymers 0.000 description 2
- 239000000057 synthetic resin Substances 0.000 description 2
- 229920001169 thermoplastic Polymers 0.000 description 2
- 239000004416 thermosoftening plastic Substances 0.000 description 2
- -1 aluminium iron chloride Chemical compound 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000011900 installation process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract
本发明涉及一种制造半导体器件(10)的方法,由此电子元件(11)附着在载体板(4)上或上方,该半导体器件包括第一材料的第一层(5)和不同于第一材料的第二导电材料的第二层,其是导电的,并具有小于该第一层(5)的厚度,且其中形成至少延伸到第一层(5)的腔体(6)。该元件(11)与载体板(4)的部分(2)在第一连接区域(1)上电连接,且在该元件(11)周围和腔体(6)中沉积包封。接着,除去大部分载体板(4)的第一层(5)以到达该腔体(6),借此由载体板(4)的剩余部分形成第二连接导体(2)。根据本发明,在沉积包封(3)之前,至少一个另外的腔体(7)在由腔体(6)环绕的一部分载体板(4)中形成,该另外的腔体(7)在包封(3)沉积的过程中基本上至少由一部分包封(3)所填充,且在第二连接区域(2)内,将其一部分(2A)与其剩余部分(2B)分离,该部分(2A)的最小尺寸选择为比每个第二连接区域(2)的剩余部分(2B)的最小尺寸更小。因此,可以轻易地为该部分(2A)提供具有比第二连接区域(2)的剩余部分中的焊料(8B)更小厚度的焊料(8A)。例如在器件(10)的表面安装的情况中,这是一个优点。优选地,该第一连接区域(1)与连接区域(2)的部分(2A)相连接。
Description
本发明涉及一种电子器件的制造方法,该电子器件包括具有第一连接区域和电绝缘包封的电子元件,该方法包括在载体板的第一表面中提供凹槽的步骤,所述板按顺序包括第一材料的第一层和不同于第一材料的第二导电材料的第二层,该凹槽从第一表面上穿过第二层至少延伸到该第一层;在该载体板的表面上或上方提供电子元件;电连接第一连接区域至位于凹槽内的部分第二层;采用绝缘包封环绕该电子元件,该绝缘包封至少基本上填满该载体板中的凹槽;并从该载体板的背离该第一表面的第二表面除去该载体板,至少达一定程度,以便到达由一部分包封所填充的凹槽,借此,由存在于该凹槽内的第二层的部分来形成第二连接区域。
本发明还涉及一种半导体器件,包括具有第一连接区域的电子元件,还包括具有第一侧面和与其背离的第二侧面的第二连接区域,该第二连接区域在第一侧面上提供有到第一连接区域的电连接,并且在第二侧面上提供有电连接件以便设置在基板上,该电子元件由至少延伸到第二连接区域的电绝缘包封所环绕。
这种方法特别适合于除其他以外的廉价半导体器件的制造。其中的电子元件是一个电子元件,例如(半)分立式晶体管或二极管,集成电路,存储器电路等等。通过这种方法制造的器件而且特别紧凑,其提供了很多应用中所一直需求的先进小型化的可能性。
这种方法和这种半导体器件可以从欧洲专利EP 1160858A2中了解。这里描述的是如何将半导体IC(=集成电路)以紧凑的形式包封(envelope)。IC被紧固在载体板上或上方。IC的第一连接区域与载体板的部分直接或通过电导线来连接。载体板包括连续的两个金属层,其中毗连IC的上层具有小于下层的厚度。该载体板提供有凹槽,该凹槽从第二层的表面延伸入第一层并环绕该载体板的部分,由其形将成包封的IC的第二连接区域。在IC形成在该载体板上或上方后,电绝缘(和钝化)包封围绕IC设置并背对载体板。借此,该凹槽大部分由部分包封填充。随后,除去载体板的尽可能大的部分,特别是其第一层的主要部分,这样到达了由一部分包封所填充的该凹槽。由此,包封IC的第二连接区域由(剩余的)部分载体板形成。这样IC就准备好例如用于最后的表面安装或紧固至焊接框。
已知方法的缺点在于,为最后安装而在第二连接区域上作为焊料凸块提供的焊料,在必要的加热后会流出到整个连接区域上,具有相对小和基本上均匀的厚度,且由此在固化后也仍存在。可以通过在第二连接区域上提供抗焊料层来避免该情况,该层可以通过光刻来提供开口,在该开口中提供所述焊料凸块。然而,这样使得该方法更加复杂。这是因为,所述光刻步骤必须在装配过程中,即包封步骤后进行。然而,这种装配过程通常在没有光刻设备的工厂中进行。而且,光刻步骤需要精确度和时间持续,这在装配期间是无法获得的。第二连接区域尺寸的替代性减小也不能提供解决方案,因为这样将引起IC与外界连接的电和热性质恶化。这同样是不理想的。
因此,本发明的第一个目的是提供一种不具有上述缺点的方法,或至少达到更低的程度,并且该方法还简单并且相应的成本低。
根据本发明,开篇段落中提及的该种方法就是为了上述目的,其特征在于凹槽在第一层中延伸,由此在腔体形成下,相对于第二层在第一层内发生底蚀,该腔体由绝缘包封来填充。
向下蚀刻至第一层中形成了第二层下方的腔体。该腔体由绝缘包封填充。第二连接区域的边缘从而带有由绝缘包封组成的保护层。当从第二表面除去该载体板时,所述保护层将成为表面。该第二连接区域相对所述表面凹陷。
根据本发明的方法具有的优点之一是,包封后光刻步骤不再是必须的;该第二连接区域实际上借助包封来构图成接触表面。通常包括合成树脂,例如环氧树脂或热塑性材料的电绝缘包封的性质是这样的,以便由此排斥焊料。随后施加到第二连接区域的焊料因此保持了对接触表面的限制。
根据本发明的另一个优点是,第二层可以保持很薄,特别是与第一层相比。这样的结果是,与现有技术中可能存在的情况相比,第二连接区域能够位于在更小的相互距离上。
最后,根据本发明方法的主要的优点是,该方法相对简单并且不需要额外的步骤。
在该方法的优选实施例中,在提供包封前,在由凹槽环绕的一部分载体板中提供至少一个另外的凹槽,该另外的凹槽在其提供期间基本上由一部分包封来填充。在相应的第二连接区域中设置所述另外的凹槽,这样其一部分从该第二连接区域的剩余部分被界定,所述部分的最小尺寸选择为比该第二连接区域的剩余部分的最小尺寸还小。当除去该载体板时,除去该载体板的程度以便到达该另外的凹槽。因此,所形成的每个第二连接区域由所存在的一部分包封局部地中断。通常包括合成树脂,例如环氧树脂或热塑性材料的电绝缘包封的性质使得由此排斥焊料。事实是,当提供在第二连接区域的中断一侧时,焊料凸块在第二连接区域的整个剩余部分之上熔化期间会流出,但是固化后它会以更大的厚度剩余于其最小尺寸是最大的该部分连接区域中。这种焊料的局部抬升是特别有利的,例如,对于半导体器件的最后表面安装。此外,因为整个第二连接区域的表面很难由其局部中断而制作的更小,因此该电子元件与外界连接的电和热性质保持优异,且同时由此形成的第二连接区域的(两)部分之间的电和热质量也保持优异。这非常重要,特别是对于相对紧凑的半导体器件,即使其绝对功率耗散并不大,但因为功率密度在这种器件中增加。
因此,在根据本发明方法的一个优选实施例中,在除去大量的载体板以便到达凹槽和另外的凹槽,以及形成了第二连接区域后,在每个第二连接区域的至少一部分上提供焊料颗粒。优选地,焊料颗粒在其施加后熔化,使得每个第二连接区域整体上浸润,并且由于冷却而使焊料固化后,使得在每个第二连接区域的所述部分中的焊料高度比其在每个第二连接区域的剩余部分中的高度更小。
在主要的实施例中,该第一连接区域与第二连接区域的所述部分相连接。结果,在所完成的器件最后装配的过程中,凭借每个第二连接区域剩余部分的较厚的焊料,第一和第二连接区域之间的连接不会再次断裂或机械负荷。而且,优选地,该凹槽和该另外的凹槽同时在一个和相同的过程步骤中形成。根据本发明的该方法与已知方法的情况相比不再复杂和高成本。使用适应后的掩膜能够获得令人满意的效果。
优选地,该另外的凹槽在该载体板中形成为一个或几个凹槽,这些凹槽定位在将要形成的相应第二连接区域中,这样它们与该凹槽内边缘的一部分一起界定每个第二连接区域的一部分,其最小尺寸比其剩余部分的最小尺寸更小。该部分的最小尺寸与第二连接区域的剩余部分的最小尺寸的比率优选地选择为小于1/2,更优选在1/3和1/6之间。当选择铝用于该载体板第一层的材料,以及选择铜用于该载体板第二层的材料时,会获得非常满意的效果。这些材料,特别是铜,具有良好的电和热性质,并且此外即使相对于彼此选择性地蚀刻,例如在使用湿法化学蚀刻剂时还能够非常良好。载体板主要部分的除去也能够通过CMP(=化学机械抛光)非常好地实现。
当该载体板第一层的厚度选择在10到300μm之间,优选在大约30μm时,以及第二层的厚度选择在2到20μm之间,优选在10μm时,可以获得良好的效果。在提供了包封后,整体除去载体板的第一层是有利的。除了可能使用CMP,对于铝来说很好的蚀刻剂由热钠碱液形成。根据本发明的方法特别适合具有分立或半分立电子元件的半导体器件的制造,如用于例如,移动电话。本发明还涉及根据本发明的方法获得的半导体器件。
本发明的第二个目的是提供一种第二段中提及类型的半导体器件,该器件能够以低成本的方式制造,并且其中所述第二连接区域可以有效地被保护。
所述第二个目的是如此获得的,即包封延伸到第二连接区域的第二侧面,这样该第二连接区域在包封的凹槽中可触及用于设置在基板上。根据本发明半导体器件中的该第二连接区域存在于包封的凹槽中,即,相对于该半导体器件表面凹陷。由此,该半导体器件符合基板上布局的要求,同时还不需要为此有额外的层。
半导体器件中的电连接优选由凸块形成,但是该电连接还可以选择用焊料、接合线或各向异性导电胶来实现。此外以非接触的方式来实现连接也是可能的,例如通过电容耦合,特别是对于输入和输出信号的数量以及功率消耗相对受到限制的电子元件,诸如用于识别目的的元件。
基板上布局的连接件优选是焊料凸块。可选择地,也可以使用各向异性导电胶或其它连接件。
在优选的实施例中,该器件具有变化尺寸的第二连接区域,当在其上施加焊料凸块作为电连接件时,该焊料凸块会具有取决于相应第二连接区域大小的高度。实践中发现,变化高度焊料凸块的使用是非常期望的包封的性质。由于包封相对于焊料的排斥行为,可以在根据本发明的器件中通过简单的方式来实现。
现在将参照实施例和附图来更加详细地描述本发明,其中
图1概略地并以透视图示出根据本发明的方法制造的半导体器件,
图2示出图1的器件沿线II-II在厚度方向的概略横截面视图,和
图3到图9以沿着线II-II在厚度方向上的概略横截面视图,示出根据本发明方法的实施例制造的连续步骤的图1的器件。
上述图都并非真正按比例,为了更加清晰,一些区域已经刻意夸大。尽可能多的相应区域或部件已经被给予相同的附图标记。
图1是根据本发明方法制造的半导体器件的概略透视图。图2也示出图1的器件,沿线II-II在厚度方向上的概略横截面视图。图2到图5是图1中的器件在图1中沿线II-II在厚度方向上的概略横截面视图,该器件通过根据本发明方法的实施例以连续的步骤制造。该器件10包括电子元件11(见图2),其具有多个第一连接区域1,在本例中是三个,图2中描述了其中两个,并且该电子元件由包封3环绕,在该实例中该包封由环氧树脂材料制成。对于每个第一连接区域1的第二连接区域2存在于包封3上,并且通过焊料12与此相连接。该实例中的电子元件11包括双极晶体管11,并相应地具有三个第二连接区域2,正如在上侧所看到的。所述区域提供有焊料8。
该第二连接区域2由包封3的部分6所环绕,该包封3的部分7存在于第二连接区域2内。焊料8在每个整体第二连接区域2上延伸,但是局部地具有更大的厚度(见图2)。由于第二连接区域2的部分2A通过包封3的部分7和包封3的部分6的一部分内部边缘,与第二连接区域2的剩余部分2B划界,然而在融化后位于第二连接区域2的焊料凸块8实际上已经润湿了整个第二连接区域2,在该焊料8固化后,位于部分2A上的焊料8的部分8A的厚度会比位于剩余部分2B上焊料8的部分8B的厚度更小。这也是由于部分2A的最小尺寸比第二连接区域剩余部分的最小尺寸更小的缘故。焊料8厚度的这种差异对该器件10的表面安装是有利的。
图3到9是沿线II-II在图1中所示的厚度方向的横截面概略视图,示出了由根据本发明方法的一个实施例制造的连续步骤中的图1中的器件。
参照图3,该方法以包含第一层的载体板4开始,该实例中第一层是铝且为30μm厚。导电材料的第二层2位于其上,在该实例中第二层是铜,并且具有小于第一层5的厚度,在这里是10μm。参考图4,在该装配中,借助光刻和蚀刻来开始形成凹槽6和另外的凹槽7,即两个另外的圆形凹槽7。所使用的蚀刻剂可以是,例如,相对于铝或多或少可选择地蚀刻铜的氯化铁。随后,参考图5,由于蚀刻了载体板4的第一层5而可以继续形成凹槽6和另外的凹槽7。相对铜可以选择性地蚀刻铝,例如通过钠碱液。这样相对于铜层2的2A,2B部分,底蚀了第一层5的铝。
随后,参照图6,电子元件11,在该实例中是双极晶体管11,紧固在载体板4之上或上方,在该实施例中是在载体板4之上。这里通过焊料12来实现,借助其电子元件11通过其连接区域11紧固到该载体板4的部分2A,2B上。该电子元件11可以以任选的方式紧固到载体板4上,例如借助电子绝缘胶。因而,优选将元件11的连接区域1翻转,以便背离载体板4,并且通过导线与载体板4的2A,2B部分电连接。
随后,参考图7,器件10设置在模具中(没有示出),以及在该实例中包括环氧树脂材料的包封3提供在元件11的周围,并借助注入模塑相对该载体板4按压。凹槽6和另外的凹槽7由此由包封3的部分6,7填充。随后,参考图8,在该实例中通过CMP(=化学机械抛光)除去载体板4的主要部分。该步骤一直继续到达到由包封3的部分填充的凹槽6和另外的凹槽7。在本实例中,仍然存在于包封3的部分6和7之间的第一层5的最后剩余物,在蚀刻过程中被除去,例如借助上述提到对铝的选择性蚀刻剂。
这样,根据本发明,较小的部分2A-至少关于最小尺寸—在每个第二连接区域2内与每个第二连接区域的较大的剩余部分2B划界。该2A部分的界定一方面由环绕第二连接区域2的包封3的部分6的内边缘来形成,而另一方面由部分7来形成,这里,包封3的两个部分形成在该第二连接区域2内。
参照图9,在焊料凸块8设置在第二连接区域2的部分2B上以后,例如,并且已经熔化后,该焊料8会在由于冷却而再次固化前流出到整个第二连接区域2之上,但是该第二连接区域2的2A部分中焊料8A的厚度会比其2B部分的厚度更小。该2A,2B部分的电和热性质在这里基本上与包封3的部分7没有存在于每个第二连接区域2内的情况相同。事实是,特别是由于包封3的部分6和7部分延伸在第二连接区域2的上方,这样其表面区域不会或至少基本上不减小。结果是特别紧凑的半导体器件10,其非常适合表面安装,以及也具有非常令人满意的电和热性质。特别的优点在于,该实例中的元件1的第一连接区域1与第二连接区域2的部分2A相连接,其中焊料的厚度最小。需要注意的是,图9示出了和图2所示相同的装配,但是图9已经关于图2在附图的平面中旋转了180°。这与参考图3到9所描述的器件10的制造有关,这使得所描述的具有逻辑性。
下面将根据上面所描述制造的器件10的尺寸来说明。电子元件11的尺寸是350×350μm2。其厚度大约是200μm。整个器件10的尺寸是1000×800×230μm3。该整个器件10比元件11更大这一事实的优点是,该器件能够通过定位机器更容易地定位,例如在最后的安装过程中。焊料8A的厚度是例如30μm,且焊料8B的厚度是150μm。部分2A和每个第二连接区域2的剩余部分2B的最小尺寸分别大约是30到180μm。这些是本实例中沿图1中的线II-II测量的尺寸。此外,部分2A大约是方形的,且每个第二连接区域的剩余部分2B的最大尺寸大约是600μm。
本发明并不限制于该实施例所描述的方法,因为对于本领域的技术人员来说多种变化和改进也可以包括在本发明的范围内。这样器件可以以不同的几何形状和/或不同的尺寸来制造。也可以选择使用的材料,特别是对于载体板。
还需要注意的是根据本发明的方法能够同时制造大量的器件,尽管上述实施例只描述和说明了单个器件的制造。这样,单个半导体器件可以通过机械分离技术,例如切片,切割,或断开等来获得。在引人关注的变型中,另一个凹槽形成在载体板的两个相邻的器件之间。当在元件上以滴液的形式提供包封时,该滴体会润湿载体板和元件直到该另一个凹槽的边缘。随后该液体可以固化。当除去载体板时,单个器件就会自动地分开。
除了如本例中具有分立元件的半导体器件外,更小的半分立IC,例如包括1到100个有源和/或元源元件,也可以选择来制造。对更大更复杂的IC的应用也会是有利的。另一个有利的可能性是使用滤波器或一个或几个无源元件作为电子元件。
最后需要注意的是,可以赋予该第二连接区域与实例中示出的不同的几何形状。这样,所述区域的该部分和剩余部分可以具有大致环形的几何形状,该环形由一个或几个更狭窄的部分来相互连接。在该实例中很明显,第二连接区域剩余部分和该部分的最小尺寸与第二连接区域的剩余部分和相应部分的直径是相等的。该另外的凹槽不必是如实例中的圆形,而是可以具有一些其它的几何形状。
Claims (11)
1.一种制造电子器件(10)的方法,该器件包括提供有第一连接区域(1)和电绝缘包封(3)的电子元件(11),其中该方法包括步骤:
-在载体板(4)的第一表面上提供凹槽(6),所述板(4)按顺序包括第一材料的第一层(5)和不同于第一材料的第二导电材料的第二层(2),该凹槽(6)从第一表面延伸穿过第二层(2)至少到第一层(5);
-在载体板(4)的表面上或上方提供电子元件(11);
-电连接第一连接区域(1)与位于该凹槽(6)内的第二层(2)的部分(2A,2B);
-通过至少基本上填充载体板(4)中的凹槽(6)的绝缘包封(3)来环绕电子元件(11);以及
-从载体板(4)的背离第一表面的第二表面除去该载体板(4),达到至少一定程度,以便到达由包封(3)的一部分填充的凹槽(6),由此第二连接区域(2)由位于该凹槽(6)中的第二层(2)的部分(2A,2B)来形成,
-其特征在于,该凹槽(6)延伸到第一层(5)中,使得在腔体的形成之下,相对于第二层(2)在第一层(5)内发生底蚀,该腔体由绝缘包封(3)来填充。
2.如权利要求1所述的方法,其特征在于,在提供包封(3)之前,在由凹槽(6)环绕的一部分载体板(4)中提供至少一个另外的凹槽(7),在其施加过程中该另外的凹槽(7)大部分由包封(3)的一部分填充,且该另外的凹槽(7)定位于每个第二连接区域(2)内,这样其一部分(2A)与第二连接区域(2)的剩余部分(2B)划界,所述部分(2A)的最小尺寸选择为比第二连接区域(2)的剩余部分(2B)的最小尺寸更小,且除去大部分载体板(4)以便也到达所述另外的凹槽(7)。
3.如权利要求1所述的方法,其特征在于
在除去大部分载体板(4)以便到达凹槽(6)和另外的凹槽(7),并形成了第二连接区域(2)之后,在每个第二连接区域(2)的至少一部分上提供焊料颗粒(8)。
4.如权利要求3所述的方法,其特征在于在施加焊料颗粒(8)后其融化,使得每个第二连接区域(2)整体上被润湿,且由于其冷却而使焊料(8)固化后,使得在每个第二连接区域(2)的所述部分(2A)中焊料(8A)的高度比每个第二连接区域(2)的剩余部分(2B)中的焊料(8B)高度更小。
5.如权利要求2所述的方法,其特征在于该第一连接区域(1)与该第二连接区域(2)的所述部分(2A)相连接。
6.如权利要求2所述的方法,其特征在于该凹槽(6)和该另外的凹槽(7)在一个相同的工艺步骤中形成。
7.如权利要求2所述的方法,其特征在于该另外的凹槽(7)在载体板(4)中以一个或几个凹槽(7)的形式制造,其在形成之下定位于每个第二连接区域(2)内,使得它们与凹槽(6)的内边缘部分一起环绕每个第二连接区域(2)的一部分(2A),该部分(2A)的最小尺寸比每个第二连接区域(2)的剩余部分(2B)的最小尺寸更小。
8.如权利要求2,7或8所述的方法,其特征在于部分(2A)的最小尺寸与第二连接区域(2)的剩余部分(2B)的最小尺寸的比率优选地选择在为小于1/2,更优选地在1/3和1/6之间。
9.如前述任一权利要求所述的方法,其特征在于选择铝作为载体板(4)的第一层(5)的材料,且选择铜为该载体板(4)的第二层(2)的材料。
10.一种半导体器件(10),包括具有第一连接区域(1)的电子元件(11),还包括具有第一侧面和具有与其背离的第二侧面的第二连接区域(2),该第二连接区域(2)每个在其第一侧面提供有与第一连接区域(1)的电连接,且能够在该第二侧面上提供有连接件,用于设置在基板上,该电子元件(11)由至少延伸到该第二连接区域(2)的电绝缘包封(3)环绕,其特征在于该包封延伸到每个第二连接区域(2)的第二侧面,使得该第二连接区域在包封(3)的凹槽中可接触,用于设置在基板上。
11.一种如权利要求10中所述的半导体器件(10),并具有变化尺寸的第二连接区域(2),在其上当焊料凸块(8)用作电连接件时,所述凸块(8)会具有取决于相应的第二连接区域(2)的尺寸的高度。
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JPH08335653A (ja) * | 1995-04-07 | 1996-12-17 | Nitto Denko Corp | 半導体装置およびその製法並びに上記半導体装置の製造に用いる半導体装置用テープキャリア |
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