CN1643499A - 在多线程网络处理器中的线程信令 - Google Patents
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Abstract
描述一种基于硬件的并行多线程处理器。处理器包括协调系统功能的通用处理器以及支持程序线程的多个微引擎。处理器还包括存储器控制系统,该控制系统具有第一存储器控制器和第二存储器控制器,所述第一存储器控制器根据把存储器访问引导到偶数存储体还是奇数存储体而对存储器访问进行分类;第二存储器控制器根据存储器访问是读出访问或写入访问而使存储器访问最优化。还描述用于分组处理的程序线程通信方案。
Description
背景
本发明涉及网络分组处理。
在计算处理中,并行处理是同时发生事件的信息处理的有效形式。对比于顺序处理,并行处理要求在计算机中同时执行许多程序。在并行处理器的情况中,并行论包括同时做一件以上的事情。在串行范例中,在单个站或在特定站处执行任务的流水线机器上顺序地执行所有的任务,与串行范例不同,并行处理提供多个站,每个站能够执行所有的任务。即,一般地,在问题的相同的或共同的要点上,所有站或多个站同时和独立地工作。某些问题适合于通过应用并行处理而解决。
概要
根据本发明的一个方面,一种处理网络分组的方法包括接收网络分组,以及用多个程序线程在网络分组上操作,以影响所述分组的处理。
附图简述
图1是使用基于硬件的多线程处理器的通信系统的方框图。
图2是图1的基于硬件的多线程处理器的详细方框图。
图3是在图1和2的基于硬件的多线程处理器中使用的微引擎功能单元的方框图。
图4是存储器控制器的方框图,用于在基于硬件的多线程处理器中所使用的增强带宽操作。
图5是存储器控制器的方框图,用于在基于硬件的多线程处理器中所使用的有限等待时间的操作。
图6是在图1处理器中的通信总线接口的方框图,描绘在程序线程信令中所使用的硬件。
图7A-7B是对于理解读出即清零寄存器的程序线程信令有用的图形表示和流程图。
图8是线程间信令方案的流程图。
图9是程序线程状态报告过程的流程图。
说明
结构
参考图1,通信系统10包括并行的基于硬件的多线程处理器12。把基于硬件的多线程处理器12耦合到诸如外围设备互连(PCI)总线14、存储器系统16和第二总线18之类的总线。系统10对于可以断成并行子任务或功能的任务是特别有用的。基于硬件的多线程处理器12对于与带宽有关的而不是与等待时间有关的任务是特别有用的。基于硬件的多线程处理器12具有多个微引擎22,每个微引擎22具有可根据任务同时动作和独立地工作的多个受硬件控制的程序线程。
基于硬件的多线程处理器12还包括中央控制器20,对于基于硬件的多线程处理器12的其它资源,所述中央控制器有助于装载微代码控制,并执行其它通用计算机型功能,诸如处理协议、异常、用于分组处理的额外支持,其中,微引擎传递出用于诸如在边界条件中更详情处理的分组。在一个实施例中,处理器20是基于Strong Arm(Arm是英国ARM有限公司的注册商标)的结构。通用微处理器20具有操作系统。微处理器20可以通过操作系统调用功能,以在微引擎22a-22f上操作。处理器20可以使用任何支持的操作系统,最好是实时操作系统。对于作为Strong Arm结构而实施的核心处理器,可以使用诸如微软NT实时、VXWorks和μCUS、可在互联网上得到的免费软件操作系统之类的操作系统。
基于硬件的多线程处理器12还包括多个微引擎22a-22f。每一个微引擎22a-22f含有在硬件中的多个程序计数器,以及与程序计数器相关联的状态。实际上,在每个微引擎22a-22f上可以同时有相应的多个程序线程组工作,但是实际上在任何一段时间中只有一个进行操作。
在一个实施例中,有六个微引擎22a-22f,每一个具有处理四个硬件程序线程的能力。六个微引擎22a-22f与共享资源一起操作,所述共享资源包括存储器系统16和总线接口24和28。存储器系统16包括同步动态随机存取存储器(SDRAM)控制器26a和静态随机存取存储器(SRAM)控制器26b。一般使用SDRAM存储器16a和SDRAM控制器26a来处理大量的数据,例如,处理来自网络分组的网络有效负载。在短等待时、快访问任务的网络实施(例如,访问查找表、访问用于核心处理器20的存储器等)中,使用SRAM控制器26b和SRAM存储器16b。
硬件上下文交换使具有唯一程序计数器的其它上下文在相同的微引擎中的执行成为可能。硬件上下文交换还使任务的完成同步。例如,两个程序线程可以请求相同的共享资源,例如SRAM。这些独立功能单元的每一个,例如FBUS接口28、SRAM控制器26a以及SDRAM控制器26b,当它们完成来自微引擎程序线程上下文之一所请求的任务时,就返回报告操作完成的标志信令。当微引擎接收到该标志时,微引擎可以确定要接通哪个程序线程。
作为网络处理器(例如路由器),基于硬件的多线程处理器12连接到诸如媒体访问控制器装置(例如,10/100BaseT八进制MAC 13a或千兆位以太网装置13b)之类的网络装置。一般地,作为网络处理器,基于硬件的多线程处理器12连接到接收/发送大量数据的任何类型的通信装置或接口。以并联方式在装置13a、13b中间按选择路由传递网络分组的网络应用中,网络处理器可以具有如同路由器10这样的功能。可以用基于硬件的多线程处理器12对每个网络分组独立地进行处理。
处理器12包括把处理器耦合到第二总线18的总线接口28。在一个实施例中,总线接口28把处理器12耦合到所谓的FBUS 18(FIFO(先进先出)总线)。FBUS接口28负责控制处理器12并把它连接到FBUS 18。FBUS 18是64位宽FIFO总线,作为到媒体访问控制器(MAC)装置的接口。处理器12包括第二接口(例如,PCI总线接口24),它把驻留在PCI 14总线上的其它系统部件耦合到处理器12。
把功能单元连接到一个或多个内部总线。内部总线是双向、32位总线(即,一条总线用于读出而一条总线用于写入)。还构成基于硬件的多线程处理器12,致使在处理器12中的内部总线的带宽总和超过耦合到处理器12的外部总线的带宽。处理器12包括内部核心处理器总线32,例如,ASB总线(高级系统总线),它把处理器核心20耦合到存储器控制器26a、26b以及耦合到下述ASB翻译器30。ASB总线是所谓的AMBA总线的子集,所述AMBA总线是与Strong Arm处理器核心一起使用的。处理器12还包括专用总线34,它把微引擎单元耦合到SRAM控制器26b、ASB翻译器30以及FBUS接口28。存储器总线38把存储器控制器26a、26b耦合到总线接口24和28以及存储器系统16,所述存储器系统16包括用于引导程序操作等的快闪ROM(只读存储器)16c。
参考图2,每个微引擎22a-22f包括一个仲裁器,该仲裁器检查标志,以判定操作所根据的可用程序线程。来自微引擎22a-22f的任何程序线程可以访问SDRAM控制器26a和SDRAM控制器26b,每一个包括多个队列,以存储未确认的存储器访问请求。队列或是保留存储器访问的次序,或是安排存储器访问,以使存储器带宽最优化。
如果存储器子系统16实质上充满独立的存储器请求,则处理器12可以执行存储器访问分类。存储器访问分类减少随着对SRAM的访问而发生的停滞时间或冒泡。存储器访问分类允许处理器12对到存储器的访问进行组织,致使写入的长字符串可以跟随读出的长字符串。
访问分类有助于保持并联的硬件上下文程序线程。访问分类允许隐藏从一个SDRAM存储体到另一个的预加载。如果把存储器系统16b组织成奇数存储体和偶数存储体,则存储器控制器26b可以开始预加载偶数存储体。如果在奇数和偶数存储体之间轮流进行存储器访问,则预加载是可能的。通过对存储器访问进行排序,以轮流访问相对着的存储体,处理器12改进了SDRAM带宽。此外,可以使用其它最优化。例如,在存储器访问之前,在可以融合最优化的操作处融合最优化,通过检查地址融合打开页面最优化,已打开页面不重新打开,可以使用链接存储,它允许邻接的存储器访问和刷新机构的特殊处理。
FBUS接口28支持MAC装置支持的每个端口的发送和接收标志,以及表示何时保证业务的一个中断标志。FBUS接口28还包括控制器28a,它执行来自FBUS 18的输入分组的标头处理。控制器28a取出分组标头,并执行在SRAM中的微可编程源/目的地/协议散列查找(用于地址平滑)。如果没有成功地解答散列,则把分组标头发送到处理器核心20进行另外的处理。FBUS接口28支持下列内部数据处理事务:
FBUS单元 (共享总线RAM) 到/从微引擎
FBUS单元 (经由专用总线) 从SDRAM单元写入
FBUS单元 (经由Mbus) 读到SDRAM
FBUS 18是标准的工业总线,并包括数据总线,例如64位宽和对于地址的边带控制和读出/写入控制。FBUS接口28使用一系列输入和输出FIFO29a-29b提供输出大量数据的能力。微引擎22a-22f从FIFO 29a-29b取得来自SDRAM控制器26a的数据,或命令SDRAM控制器26a把数据从接收FIFO(其中,数据来自总线18中的一个装置)转移到FBUS接口28。通过直接存储器访问,可以通过存储器控制器26a把数据发送到SDRAM存储器16a。类似地,微引擎可以把数据从SDRAM 26a转移到接口28,经过FBUS接口28输出到FBUS 18。
在微引擎当中分发数据功能。到SRAM 26a、SDRAM 26b和FBUS 28的连接是通过命令请求的。命令请求可以是存储器请求或FBUS请求。例如,命令请求可以把数据从位于微引擎22a中的一个寄存器转移到一个共享资源,例如SDRAM存储单元、SRAM存储单元、快闪存储器或某些MAC地址。把命令送出到每个功能单元以及共享资源。然而,共享资源不需要保持数据的局部缓冲。而是,共享资源访问位于微引擎内部的分发数据。这使微引擎22a-22f能局部访问数据,而不是对在总线上的访问进行仲裁和有风险地竞争总线。用这个特征,对于等待微引擎22a-22f内部的数据存在0循环停转。
核心处理器20还可以访问共享资源。核心处理器20经过总线32到SDRAM控制器26a、到总线接口24以及到SRAM控制器26b可以直接进行通信。为了访问微引擎22a-22f和位于微引擎22a-22f中任何一个处的传送寄存器,核心处理器20通过总线34上的ASB翻译器30访问微引擎22a-22f。ASB翻译器30执行FBUS微引擎传送寄存器存储单元和核心处理器地址(即,ASB总线)之间的地址翻译,以致核心处理器20可以访问属于微引擎22a-22f的寄存器。
虽然微引擎22可以使用寄存器组来交换数据,但是还提供暂时存储器27,以允许微引擎把数据写到存储器供其它微引擎读出。把暂时存储器27耦合到总线34。
微引擎
参考图3,图中示出微引擎22a-22f的一个示例。微引擎包括控制存储器70,在一个实施例中,控制存储器70包括具有1024个32位字的RAM。RAM存储可通过核心处理器20装载的微引擎。微引擎22f还包括控制器逻辑72。控制器逻辑包括指令解码器73和程序计数器(PC)单元72a-72d。把四个微程序计数器72a-72d保留在硬件中。微引擎22f还包括上下文事件切换逻辑74。上下文事件逻辑74从例如SRAM 26a、SDRAM 26b或处理器核心20、控制和状态寄存器等共享资源中的每一个接收消息(例如,SEQ_#_EVENT_RESPONSE;FBI_EVENT_REPONSE;SRAM_EVENT_RESPONSE;SDRAM_EVENT_RESPONSE;以及ASB_EVENT_RESPONSE)。这些消息提供是否已经完成所请求功能的信息。根据是否已经完成程序线程请求的功能和发出完成信号,程序线程需要等待该完成信号,如果启动程序线程操作,则使程序线程安排一个可用程序线程清单(未示出)。例如,微引擎22f最多可得到4个程序线程。
除了对于执行程序线程是局部的事件信号之外,微引擎22还使用全局性的信令状态。用信令状态,执行程序线程就可以向所有微引擎22广播信号状态。在微引擎中的任何程序线程可以按这些信令状态转移。可以使用这些信令状态来判定资源的可用性或资源是否应该服务了。
上下文事件逻辑74具有对于四(4)个程序线程的仲裁。在一个实施例中,仲裁是一种循环式的机构。可以使用其它技术,包括优先级队列或加权公平队列。微引擎22f还包括执行盒(EBOX)数据路径76,它包括算术逻辑单元76a和通用寄存器组76b。算术逻辑单元76a执行算术和逻辑功能以及移位功能。寄存器组76b具有数目相当多的通用寄存器。在这个实施中,在第一存储体,存储体A,中有64个通用寄存器,在第二存储体,存储体B,中有64个。给通用寄存器设置窗口,以致它们是相对地和绝对地可寻址的。
微引擎22f还包括写入传送寄存器堆栈78以及读出传送堆栈80。也给这些寄存器设置窗口,以致它们是相对地和绝对地可寻址的。写入传送寄存器堆栈78是查找到资源的写入数据处。类似地,读出寄存器堆栈80是为了从共享资源返回的数据。在数据到达之后或与数据到达同时,将把来自例如SRAM控制器26a、SDRAM控制器26b或核心处理器20等的各个共享资源的事件信号提供给上下文事件仲裁器74,然后,上下文事件仲裁器74将向程序线程发出可得到数据或已经发送数据的警报。通过数据路径把传送寄存器存储体78和80两者连接到执行盒76。在一种实施中,读出传送寄存器具有64个寄存器,并且写入传送寄存器具有64个寄存器。
每个微引擎22a-22f支持四个上下文的多线程执行。一个原因是为了允许一个程序线程正好是在另一个程序线程发出存储器访问以后开始执行和必须等待直到在做更多工作之前完成访问。这个特性对于保持微引擎的有效硬件执行是关键性的,因为存储器等待时间是很重要的。换句话说,如果只支持单个程序线程执行,则微引擎将空转相当多数目的周期,坐等访问返回,从而降低了全面计算总处理能力。多线程的执行允许微引擎通过执行数个程序线程上的有用的独立工作而隐藏存储器等待时间。为了允许程序线程发出SRAM或SDRAM访问,提供两个同步的机构,然后,当该访问完成时,接着准时同步到位。
一个机构是立即同步。在立即同步中,微引擎发出访问和立即换出该上下文。当相应的访问完成时,将发出该上下文的信号。一旦发出信号,将返回换入当上下文交换事件发生时执行的上下文交换,并且轮到它运行。因此,从单个上下文的指令流的观点,在发出存储器访问之后,直到完成访问才执行微字。
第二个机构是延迟同步。在延迟同步中,微引擎发出访问,并继续执行与访问无关的某些其它有用的工作。一段时间以后,可能在进一步执行工作之前变得需要使程序线程的执行流与所发出的访问的完成同步。此时,执行同步微字,或是换出当前程序线程,并在较后时间当已经完成访问时返回换入程序线程,或是因为已经完成访问而继续执行当前程序线程。使用两种不同的信令方案来实施延迟同步:
如果使存储器访问与一个传送寄存器相关联,则当设置或清除相应的传送寄存器有效位时,产生触发程序线程的信号。例如,当设置传送寄存器A的有效位时,将对于放置数据到传送寄存器A中的SRAM读出发出信号。如果使存储器访问与代替传送寄存器的传送FIFO或接收FIFO相关联,则当在SDRAM控制器26a中完成访问时,产生信号。在微引擎调度程序中只保存每个上下文的一个信号,因此在这种方案中只可以存在一个未完成的信号。
参考图4,SDRAM存储器控制器26a包括存储器访问队列90,这里,从各微引擎22a-22f来的存储器访问请求到达。存储器控制器26a包括仲裁器91,它选择下一个微引擎访问请求,以转向任何功能单元。如果微引擎之一正在提供访问请求,则访问请求将通过在SDRAM控制器26a内部的地址和命令队列90。如果访问请求具有称之为“最优化MEM位”的位设置,则将把输入访问请求分类成偶数存储体队列90a或奇数存储体队列90b。如果存储器访问请求没有存储器最优化位设置,则缺省值将转向排序队列90c。SDRAM控制器26a是FBUS接口28、核心处理器20以及PCI接口24之间共享的资源。SDRAM控制器26a还保持一个状态机,用于执行读出-修改-写入原子操作。SDRAM控制器26a还对于来自SDRAM的数据的请求执行字节调整。
排序队列90c保持来自微引擎的访问请求的排序。具有一系列奇数和偶数存储体访问,可以要求只在完成奇数和偶数存储体两者的存储器访问请求的序列时,才返回一个信号。如果微引擎22f把存储器访问请求分类成奇数存储体和偶数存储体访问,并且存储体之一,例如偶数存储体,在奇数存储体之前排空了存储器访问,但是在最后的偶数访问上确立了信号,则SDRAM控制器26a可以想象地把已经完成存储器请求的信号发送回微引擎,即使未曾对奇数存储体服务。这种情况可能导致相关的问题。排序队列90c允许微引擎具有多个存储器访问,其中未完成的只是它最后的存储器访问需要发出完成的信号。
SDRAM控制器26a还包括高优先级队列90d。在高优先级队列90d中,来自微引擎之一的输入存储器访问直接转向高优先级队列,并且是按比其它队列中的其它存储器访问较高的优先级而操作的。所有这些队列,偶数存储体队列90a、奇数存储体队列90b、排序队列90c以及高优先级队列,是在单个RAM结构中实施的,把所述单个RAM结构局部地分段成四个不同的窗口,每个窗口具有它自己的头和尾指针。由于填充和排出只是单个输入和单个输出,所以可以把它们安排在相同的RAM结构中,以增加RAM结构的密度。
SDRAM控制器26a还包括核心总线接口逻辑,即ASB总线92。ASB总线接口逻辑92把核心处理器20连接到SDRAM控制器26a。如果存在从核心处理器20经过ASB接口92来的输入数据,则可以把数据存储在MEM ASB装置98中,并接着从MEM ASB装置98取出,通过SDRAM接口11O到SDRAM存储器16a。虽然未示出,但是对于读出可以提供相同的队列结构。SDRAM控制器26a还包括核心程序97,以从微引擎和PCI总线获得数据。
另外的队列包括保持许多请求的PCI地址队列94和ASB读出/写入队列96。经过多路复用器106把存储器请求发送到SDRAM接口110。SDRAM仲裁器91控制多路复用器106,所述SDRAM仲裁器91检测每个队列的完整性以及请求的状态,并从完整性和状态根据存储在优先级服务控制寄存器100中的可编程值判定优先级。
参考图5,图中示出用于SRAM的存储器控制器26b。存储器控制器26b包括地址和命令队列120。根据存储器操作的类型(即读出或写入)使存储器控制器26b最优化。地址和命令队列120包括高优先级队列120a、读出队列120b(它是SRAM执行的主要存储器访问功能)以及排序队列120c(一般它包括到SRAM的所有写入和读出,未被最优化)。虽然未示出,但是地址和命令队列120还可以包括写入队列。
SRAM控制器26b还包括核心总线接口逻辑,即ASB总线122。ASB总线接口逻辑122把核心处理器20连接到SRAM控制器26b。SRAM控制器26b还包括核心程序127,以从微引擎和PCI总线获得数据。
经过多路复用器126把存储器请求发送到SRAM接口140。SDRAM仲裁器131控制多路复用器126,所述SDRAM仲裁器131检测每个队列的完整性以及请求的状态,并从完整性和状态根据存储在优先级服务控制寄存器130中的可编程值判定优先级。一旦到多路复用器126的控制选择一个存储器访问请求,就把存储器访问请求发送到解码器138,在那里对它进行解码和产生一个地址。
SRAM单元保持对存储器映射的芯片外SRAM和扩展ROM进行控制。例如,SRAM控制器26b可以进行16兆字节的寻址,例如,8兆字节用于对SRAM16b的映射,并保留8兆字节用于特定功能,包括经过快闪只读存储器16c的引导程序空间;以及用于MAC装置13a、13b的控制台端口访问和到相关联的(RMON)计数器的访问。把SRAM使用于局部查找表和队列管理功能。
SRAM控制器26b支持下列处理事务:
微引擎请求 (经过专用总线) 到/从SRAM
核心处理器 (经过ASB总线) 到/从SRAM
地址和命令队列120还包括读出锁定失效队列120d。使用读出锁定失效队列120d来保存因一部分存储器上存在锁定而失效的读出存储器访问请求。
参考图6,示出微引擎22和FBUS接口逻辑(FBI)之间的通信。在网络应用中的FBUS接口28可以执行来自FBUS 18的输入分组的标头处理。FBUS接口执行的关键功能是取出在SRAM中的分组标头,以及微可编程源/目的地/协议散列查找表。如果没有成功地解得散列,则设法通过核心处理器28对分组标头进行更复杂的处理。
FBI 28包括发送FIFO 182、接收FIFO 183、散列单元188以及FBI控制和状态寄存器189。这四个单元通过到SRAM总线的时间多路复用的访问而与微引擎22进行通信,所述SRAM总线38是连接到微引擎中的传送寄存器78、80的。即到和从微引擎的所有通信都是经过传送寄存器78、80的。FBUS接口28包括在SRAM不使用SRAM数据总线(总线38的一部分)的时间周期期间把数据推入传送寄存器的推入状态机200;以及从在相应的微引擎中的传送寄存器得到数据的拉出状态机202。
散列单元包括一对FIFO 188a、188b。散列单元判定FBI 28接收到FBI_hash请求。散列单元从调用微引擎22得到散列密钥。在得到密钥并使之散列之后,把标记返回传递到调用微引擎22。在单个FBI_hash请求之下执行多达3个散列。总线34和38的每一个是单向的:SDRAM_push/pull_data以及Sbus_push/pull_data。这些总线的每一个需要控制信号,所述控制信号将把读出/写入控制提供给合适的微引擎22传送寄存器。
一般地,传送寄存器需要来自控制它们的上下文的保护,以保证读出正确度。尤其,如果thread_1正在使用写入传送寄存器,以把数据提供给SDRAM16a,那么直到从SDRAM控制器26a返回的信号表示已经设法通过该寄存器而且现在可以再使用时才重写该寄存器。每个写入不需要从目的地返回表示已经完成该功能的信号,因为如果程序线程在具有多个请求的目的地处写入相同的命令队列,则保证在该命令队列中的完成的排序,因此只有最后的命令需要把信号发回程序线程。然而,如果程序线程使用多个命令队列(排序和读出),则把这些命令请求分裂成独立的上下文任务,以致通过上下文交换而保持排序。在本段开始处表示的例外情况是相当于某些操作类别的,这些操作对于FBUS状态信息使用从FBI到传送寄存器的不请求的PUSH(推入)。为了保护在传送寄存器上的读出/写入判定,当设置这些特定的FBI推入操作时,FBI提供特定的Push_protect信号。
使用FBI未经请求推入技术的任何微引擎22必须在访问传送寄存器同意的FBUS接口/微引擎之前测试保护标志。如果没有确立标志,则微引擎22可以访问传送寄存器。如果确立标志,则在访问寄存器之前上下文应该等待N个周期。通过正在推入的许多传送寄存器,加上前端保护窗口,先验地判定这个计数。微引擎测试这个标志,然后把数据从读出传送寄存器转移到在邻接周期中的GPR,所以推入核心程序不会与微引擎读出相碰撞。
用于分组处理的线程信令
对于分组处理,可使用诸如线程间通信之类传递状态的专门技术,允许程序线程自己分配任务的自毁寄存器210,以及提供全局程序线程通信方案的线程_完成(thread_done)寄存器212。自毁寄存器210和线程_完成寄存器212可以实施为控制和状态寄存器189。为了清楚起见,在标有CSR块的外部的FBUS接口28中示出它们。在网络处理器中使用多个程序线程(例如,上下文)实施网络功能,以处理网络分组。例如,可以在微引擎核心程序(例如22a)之一中执行调度程序线程,同时,在其余的核心程序(例如22b-22f)中可以执行处理程序线程。程序线程(处理或调度程序线程)使用线程间通信来传递状态。
向程序线程分配特殊任务,诸如接收和发送调度,接收处理以及发送处理等。通过具有特殊读出和写入特征的线程间的信令、寄存器(例如自毁寄存器210和线程_完成寄存器212、SRAM 16b以及从诸如位设置和位清除等操作产生的,存储在内部暂时存储器186中的数据(图6)),在程序线程之间传递任务分配和任务完成。
网络处理器10包括一般上下文通信信令协议,该协议允许任何上下文设置任何其它上下文可以检测的一个信号。这允许合作的程序线程使用信号量,因此使用受微代码控制的处理进行协调。
网络分组的处理可以使用多个程序线程。一般地,对于网络处理,存在接收调度程序、发送调度程序以及处理程序线程。调度程序(接收或发送)程序线程通过处理程序线程,对要完成的工作量和工作的序列进行协调。调度程序线程把任务分配给处理程序线程,在某些情况中,处理程序线程可以把任务分配给其它处理程序线程。例如,调度程序判定哪个端口需要服务,并通过并行地处理多个程序线程来分配和调度到处理程序线程的任务,以克服固有的存储器等待时间。
在某些例子中,用慢端口,处理程序线程可以在一部分分组上执行处理,而第二处理程序线程处理其余的分组,或在某些情况中,调度程序使用下一个可用程序线程。例如,用较快的端口(例如千兆位端口,其中极快地接收64字节分组),调度程序可以把M个分组分配给下一个可用程序线程。程序线程信号彼此按照程序线程已经处理的那一部分分组和它的状态。
可以分配程序线程,以处理分组的第一64字节。当程序线程完成时,程序线程具有设置信号以唤醒下一个程序线程的数据,已经分配下一个程序线程来处理下一64字节。程序线程可以写入一个寄存器以及在预-分配的存储器存储单元(例如暂时寄存器)中写入寄存器的地址。程序线程设置信号以唤醒下一个程序线程,所述下一个程序线程是已经分配在分组的下一个字节上工作的。
参考图7A-7B,自毁寄存器210允许一个调度程序线程S(在图7B中的230)请求来自提供所请求的服务的多个程序线程Pa-Pn的服务。第一程序线程(例如,访问自毁寄存器210的Pi(在图7B中的232))取得请求。“自毁寄存器”210在通过程序线程读出时清零,即清除(在图7B中的234)。能够对该请求进行服务的其它程序线程不再与活动的请求一起存在。例如,通过写入到自毁寄存器210,一个程序上下文可以请求一个任务,所述任务是分配给已准备好的第一上下文的。上下文通过读出“自毁寄存器”210而检查分配。如果自毁寄存器的值是0,则当前不可得到新的任务来分配给程序线程。这可以表示不存在新的任务,或另一程序线程可能已经被自分配任务并清除自毁寄存器210。如果值不是0,则对自毁寄存器的内容进行解译,以判定任务,并在上下文读出时清除寄存器。因此,读出这个用于分配的寄存器的上下文接着等待用下一个任务指令写入寄存器。
参考图8,对于网络应用,一般使用不同程序上下文来执行特定的系统任务。任务包括接收调度程序、接收处理上下文、发送仲裁器、发送调度程序、发送填充和处理器核心通信。
例如,接收调度程序通过把命令发送到FBI接口28而启动242输入64或128字节的数据的接收操作,所述FBI接口28指定取出数据的端口,并指定用于缓冲该数据的接收FIFO单元,以及指定一旦已经获取接收数据就要通知的微引擎上下文。
接收调度程序线程244把信号发送到激励指定的上下文的指定的微引擎程序线程。上下文读出FBI接收控制寄存器,以得到用于处理所必需的接收信息(例如,端口、接收FIFO单元存储单元、字节计数、分组的开始、分组的结束、误差状态)。如果表示是分组的开始,则接收调度程序线程负责确定在SDRAM中的何处存储数据,(即插入分组的输出队列),并把分组数据写入SDRAM中。如果这不是分组的开始,则接收程序线程确定这个分组的较早的数据存储在何处,以便继续进行对分组的处理246。当接收到分组结束的表示248时,(或在第一64字节部分之后,如果使接收以发送等待时间最优化),接收程序线程把分组添加到通过处理分组标头而确定的队列中。
程序线程还通过提供位矢量的位设置和位清除机构与共享资源进行通信。这个机构允许个别位的设置和清除,并在个别位上执行测试和设置,以控制共享资源。位矢量发出输出队列的非空的信号。当接收程序线程使分组排队时,接收调度程序设置一个位250。发送调度程序可以检查位矢量,以确定所有队列的状态。
在暂存RAM或SRAM中可以发生在位矢量上的位设置和位清除操作。如果调度程序正在相同微引擎22上的程序线程之间进行通信,则可以把位矢量存储在寄存器组中,因为每个上下文可以读出其它上下文的寄存器。例如,在内部暂存存储器中的位矢量支持每个输出队列的空状态或非空状态。当接收程序线程的队列有一个分组时,接收程序线程使用暂存位设置命令,以在队列状态位中设置一个位,表示现在队列具有至少一个输入。对于非空的队列(例如,设置了bitx),发送仲裁器对队列位矢量进行扫描270,以判定准备发送的分组。当从队列取出分组用于发送时272,如果队列空了274,则发送仲裁器发出276位清除命令到队列位矢量的相应的位。
参考图9,thread_done(线程_完成)寄存器也在FBI 28上,它是可以从不同程序线程设置位的一种寄存器。例如,每个程序线程可以使用两位来把它的状态传递到所有其它程序线程。还有一个调度程序线程可以读出292其所有处理程序线程状态。在完成接收任务时,282“接收”程序线程把完成代码写入284到“thread_done”寄存器中。在写入thread_done寄存器之后,接收程序线程变成非现用286。接收程序线程等待来自FBI的,表示已经分配其它接收任务的其它信号。程序线程1-16具有用于“thread_done_1”的2位字段,而程序线程17-24具有用于“thread_done_2”的2位字段。2位字段允许程序线程传递不同程度任务完成。
例如,调度程序可以使用两位状态“01”来表示把数据转移到SDRAM、仍在进行分组的处理以及被保存的指针;位10可以表示把数据转移到SDRAM、仍在进行分组的处理以及不保存的指针;而位11可以表示完成了分组处理。因此,当数据变成可得到时,接收调度程序线程可以使用状态296a来处理任务,而,当数据变成可得到时,接收调度程序可以使用状态296b分配297b相同的线程以继续进行处理。
调度程序线程调用的,在调度程序线程和处理程序线程之间的软件约定可以解决消息的确切解译。即,根据约定是否是用于以上接收、发送等,状态消息可以改变。一般地,状态消息包括“忙”、“不忙”、“不忙但是等待”。“不忙,但是等待”的状态消息发出表示当前的程序线程已经完成一部分分组的处理,并期望分配任务的信号,当可得到数据时,在分组上执行接着的任务。当程序线程正在期望来自端口的数据,并且尚未保存上下文,所以它应该处理该分组的其余部分时,可以使用。
调度程序线程读出“thread done”寄存器,以判定它分配给其它程序线程的任务的完成状态。实施“thread done”寄存器作为写入1以清除寄存器,允许调度程序在它刚识别字段时就进行清除。
其它实施例
可以理解,在已经连同本发明的详细说明描述本发明的同时,打算把上述说明作为示例而不是限制本发明的范围,通过所附的权利要求书来定义本发明的范围。其它方面、优点和修改都在下列权利要求书的范围内。
Claims (28)
1.一种用于网络分组处理的方法,包括:
接收网络分组;以及
用多个程序线程在所述网络分组上操作以影响所述分组的处理。
2.如权利要求1所述的方法,其特征在于,操作包括:
使用至少一个程序线程来检查所述分组的标头部分。
3.如权利要求1所述的方法,其特征在于,所述操作进一步包括:
由所述至少一个程序线程发出已经处理分组标头的信号。
4.如权利要求1所述的方法,其特征在于,所述多个程序线程是调度作处理的任务排序的调度程序线程以及根据调度程序线程所分配的任务分派对分组进行处理的处理程序线程。
5.如权利要求1所述的方法,其特征在于,每个程序线程把表示它当前状态的消息写入寄存器。
6.如权利要求5所述的方法,其特征在于,消息的解译由调度程序线程和被该调度程序线程调用的处理程序线程之间确定的软件约定所固定。
7.如权利要求5所述的方法,其特征在于,状态消息包括忙、不忙、不忙但等待。
8.如权利要求5所述的方法,其中,状态消息包括不忙、但等待,以及其中,不忙、但等待的状态发出信号,表示当前程序线程已经完成一部分分组的处理,当可以提供数据以继续程序线程的处理时,期望被分配对所述分组执行接续的任务。
9.如权利要求5所述的方法,其特征在于,所述寄存器是所有当前程序线程都能够作读出或写入的可全局存取的寄存器。
10.如权利要求4所述的方法,其特征在于,调度程序线程能够调度多个处理程序线程中的任何一个,以处置任务的处理。
11.如权利要求10所述的方法,其特征在于,对于多个处理程序线程,调度程序线程用相应于数据的存储位置的一个地址写入寄存器。
12.如权利要求11所述的方法,其特征在于,能够处置所述任务的多个处理程序线程中的所选一个处理程序线程读出寄存器以得到数据的存储位置。
13.如权利要求12所述的方法,其特征在于,多个处理程序线程中的所选一个处理程序线程读出寄存器以得到数据的存储位置,并分配它自己处理调度程序线程所请求的任务。
14.如权利要求12所述的方法,其特征在于,多个处理程序线程中的所选一个处理程序线程读出寄存器以得到数据的存储位置,同时通过程序线程读出寄存器而清除寄存器,以分配它自己处理该任务。
15.如权利要求13所述的方法,其特征在于,当多个处理程序线程中的可分配给所述任务的另一个处理程序线程试图读出已经被清除之后的寄存器时,给它设置一个零值,表示不存在当前可分配给处理程序线程的任务。
16.一种用于接收网络分组的基于硬件的并行多线程处理器,包括:
协调系统功能的一个通用处理器;以及
支持多个程序线程并用多个程序线程在网络分组上操作以影响所述分组的处理的多个微引擎。
17.如权利要求16所述的处理器,其特征在于,多个微引擎中的一个微引擎执行调度程序线程,并且其余一些微引擎执行处理程序线程。
18.如权利要求16所述的处理器,其特征在于,进一步包括一个全局线程状态寄存器,其中,每个程序线程把表示它当前状态的消息写入所述全局状态寄存器。
19.如权利要求18所述的处理器,其特征在于,消息的解译由调度程序线程与被调度程序线程调用的处理程序线程之间的软件约定固定。
20.如权利要求16所述的处理器,其特征在于,进一步包括:
一个一次读出寄存器,其中,对于多个处理程序线程,调度程序线程用相应于数据的存储位置的地址写入所述一次读出寄存器,并且当多个处理程序线程中的所选一个处理程序线程读出所述寄存器以得到数据的存储位置时,分配它自己处理被调度程序线程所请求的任务,同时通过程序线程读出所述寄存器而清除该寄存器。
21.如权利要求21所述的处理器,其特征在于,当多个处理程序线程中的可分配给任务的另一个处理程序线程试图读出已经被清除之后的所述一次读出寄存器时,给它设置一个零值,表示不存在当前可分配给处理程序线程的任务。
22.一种包括机读存储媒体的装置,所述媒体具有用于网络处理的可执行指令,所述指令使所述装置能够:
接收网络分组;以及
用多个程序线程在网络分组上操作以影响所述分组的处理。
23.如权利要求22所述的装置,其特征在于,操作的指令进一步包括以下的指令:
使用至少一个程序线程来检查分组的标头部分。
24.如权利要求22所述的装置,其特征在于,进一步包括提供调度作处理的任务的排序的调度程序线程和根据所述调度程序线程所分配的任务分派对分组进行处理的处理程序线程的指令。
25.如权利要求22述的装置,其特征在于,每个程序线程把表示它当前状态的消息写入寄存器。
26.如权利要求25所述的装置,其特征在于,寄存器是所有当前程序线程能够对其或写入的可全局访问的寄存器。
27.如权利要求22所述的装置,其特征在于,对于多个处理程序线程,所述调度程序线程用相应于数据的存储位置的一个地址写入寄存器;以及多个处理程序线程中能够处置任务的所选一个处理程序线程读出所述寄存器以得到数据的存储位置;以及在所述程序线程读出之后清除所述寄存器。
28.如权利要求27所述的装置,其特征在于,当多个处理程序线程中的可分配给任务的另一个处理程序线程试图读出已经被清除之后的寄存器时,该寄存器提供一个零值,表示不存在当前可分配给处理程序线程的任务。
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CN103955445A (zh) * | 2014-04-30 | 2014-07-30 | 华为技术有限公司 | 一种数据处理方法、处理器及数据处理设备 |
CN103955445B (zh) * | 2014-04-30 | 2017-04-05 | 华为技术有限公司 | 一种数据处理方法、处理器及数据处理设备 |
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CN111459630A (zh) * | 2020-03-24 | 2020-07-28 | 华东计算技术研究所(中国电子科技集团公司第三十二研究所) | 采用硬件多线程机制的网络处理器 |
CN111459630B (zh) * | 2020-03-24 | 2023-12-08 | 华东计算技术研究所(中国电子科技集团公司第三十二研究所) | 采用硬件多线程机制的网络处理器 |
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EP1242883B1 (en) | 2006-09-13 |
US20040098496A1 (en) | 2004-05-20 |
DE60030767T2 (de) | 2007-11-08 |
HK1046050A1 (en) | 2002-12-20 |
WO2001048606A3 (en) | 2002-07-11 |
SG145543A1 (en) | 2008-09-29 |
WO2001048606A2 (en) | 2001-07-05 |
ATE339724T1 (de) | 2006-10-15 |
EP1242883A2 (en) | 2002-09-25 |
DE60030767D1 (de) | 2006-10-26 |
US6625654B1 (en) | 2003-09-23 |
US20020013861A1 (en) | 2002-01-31 |
TW544629B (en) | 2003-08-01 |
US7111296B2 (en) | 2006-09-19 |
CN100351798C (zh) | 2007-11-28 |
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