CN1638104A - 混合集成电路装置及其制造方法 - Google Patents
混合集成电路装置及其制造方法 Download PDFInfo
- Publication number
- CN1638104A CN1638104A CNA2004101021533A CN200410102153A CN1638104A CN 1638104 A CN1638104 A CN 1638104A CN A2004101021533 A CNA2004101021533 A CN A2004101021533A CN 200410102153 A CN200410102153 A CN 200410102153A CN 1638104 A CN1638104 A CN 1638104A
- Authority
- CN
- China
- Prior art keywords
- circuitry substrate
- extension
- wire
- lead
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 41
- 229920005989 resin Polymers 0.000 claims abstract description 34
- 239000011347 resin Substances 0.000 claims abstract description 34
- 238000007789 sealing Methods 0.000 claims abstract description 33
- 238000000465 moulding Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 116
- 238000005452 bending Methods 0.000 claims 1
- 241000283216 Phocidae Species 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- -1 copper Chemical class 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49531—Additional leads the additional leads being a wiring board
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3405—Edge mounted components, e.g. terminals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
- H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/1034—Edge terminals, i.e. separate pieces of metal attached to the edge of the PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10742—Details of leads
- H05K2201/1075—Shape details
- H05K2201/10757—Bent leads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
- H05K2203/1305—Moulding and encapsulation
- H05K2203/1316—Moulded encapsulation of mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
- H05K3/3426—Leaded components characterised by the leads
Abstract
一种混合集成电路装置及其制造方法,可在模腔内部固定衬底的位置同时进行模制。混合集成电路装置(10)的制造方法包括:构成电路的工序,该电路由在电路衬底(16)表面上形成的导电图案(18)及与导电图案(18)电连接的电路元件(14)构成;在由沿电路衬底侧边配置的导电图案(18)构成的焊盘(18A)上相对于电路衬底16的面方向大致垂直地固定引线(11)前端部的工序;将电路衬底(16)收纳入模制模具(30)的模腔(31)内,通过由模制模具(30)夹持引线(11),使电路衬底16的背面接触模腔(31)底面的工序;在模腔(31)的内部封入密封树脂(12),使电路衬底(16)的背面露出到外部而进行密封的工序。
Description
技术领域
本发明涉及混合集成电路装置及其制造方法,特别是涉及使电路衬底的背面自密封树脂露出的混合集成电路装置及其制造方法。
背景技术
参照图10说明现有混合集成电路装置的结构(例如参照专利文献1)。图10(A)是混合集成电路装置100的立体图,图10(B)是图10(A)X-X’线的剖面图。
参照图10(A)及图10(B),现有的混合集成电路装置100具有如下结构,其包括:矩形衬底106;在设于衬底106表面上的绝缘层107上形成的导电图案108;被固定在导电图案108上的电路元件104;电连接电路元件104和导电图案108的金属线105;与导电图案108电连接的引线101。如上所述,混合集成电路装置100整体被密封树脂102密封。由密封树脂102密封的方法有使用热塑性树脂的注入模模制和使用热硬性树脂的传递模模制。
参照图11说明使用传递模进行树脂密封的工序。图11(A)及图11(B)是使用模型110进行树脂密封时的剖面图。
参照图11(A),在衬底106的表面上形成由电路元件104等构成的电路。该衬底106由上模110A及下模110B固定。通过将上模110A与下模110B扣合,形成作为密封树脂的空间的模腔。通过利用上模110A及下模110B夹持引线架110将引线架定位。在此,通过冲压等形成的引线架110的剖面形状有某种程度的误差。因此,在引线架110和下模110B之间形成某种程度的间隙。
参照图11(B),通过将上模110A及下模110B嵌合来固定引线架101。然后,通过向模腔内部封入树脂,使衬底106的背面露出到外部而进行模制的工序。
在由以上的工序密封后,经由使热硬性树脂的特性稳定的二次硫化工序等,混合集成电路装置作为产品完成。
专利文献1:特开平6-177295号公报(第四页、第一图)
但是,上述这样的混合集成电路装置的制造方法具有如下问题。
引线架101介由相对于衬底106面方向倾斜延伸的部分被固定在衬底106上,因此,通过由模具110夹持引线架101来作用向下方按压引线架101的外力时,在衬底106上作用下方向及横方向的外力。因此,如图11(B)所示,衬底106有可能在模腔内部倾斜。当在该状态下,直接进行密封工序时,不能在规定的位置固定衬底106的位置。另外,由于是在引线架101上作用有应力的状态下进行树脂密封,故也产生了引线架101和衬底106连接的位置可靠性降低的问题。另外,还有难于实现衬底106的背面从密封树脂露出的结构。
发明内容
本发明是鉴于上述问题点而开发的。因此,本发明的主要目的在于,提供一种混合集成电路装置及其制造方法,可在模腔内部使衬底位置固定同时进行模制。
本发明的混合集成电路装置包括:电路衬底;在上述电路衬底表面上形成的导电图案;电连接在上述导电图案上的电路元件;固定在由上述导电图案构成的焊盘上的引线,其中,上述引线的前端部相对于上述电路衬底的面方向大致垂直地固定在上述焊盘上。
本发明混合集成电路装置的制造方法包括:形成由在电路衬底表面上形成的导电图案及与上述导电图案电连接的电路元件构成的电路的工序;在由上述导电图案构成的焊盘上相对于上述电路衬底面方向大致垂直地固定引线前端部的工序;将上述电路衬底收纳于模制模具的模腔内,并通过由上述模制模具夹持上述引线使上述电路衬底的背面接触上述模腔底面的工序;通过向上述模腔内部封入密封树脂,使上述电路衬底背面露出到外部而进行密封的工序。
另外,本发明的特征在于,上述引线由第一延伸部和第二延伸部构成,其中,第一延伸部相对于上述电路衬底的面方向大致水平延伸,第二延伸部介由弯曲部与上述第一延伸部连接而相对于上述电路衬底的面方向大致垂直地延伸,由上述模具夹持上述第一延伸部。
本发明的特征在于,上述引线的自弯曲部附近到前端部的部分被弯曲成圆弧状,上述前端部的切线方向相对于上述电路衬底的面方向大致为直角。
本发明的特征在于,上述引线的前端部与上述电路衬底接触的角度在80度~100度的范围内。
另外,本发明的特征在于,通过由上述模具夹持上述引线,介由上述引线将上述电路衬底的背面按压在上述模腔的底面。
在本发明中,可得到以下所示的效果。
根据本发明的混合集成电路装置,引线的前端部相对于电路衬底垂直地延伸,而被固定在焊盘上。因此,可减小引线的固定所必要的焊盘,可将装置整体小型化。另外,引线和焊盘的连接部被密封树脂包覆。引线的连接可靠性由密封树脂提高。
根据本发明混合集成电路装置的制造方法,通过由模具夹持前端部相对于电路衬底大致垂直固定的引线,在模制的工序中,使电路衬底的背面接触模腔下面。因此,不会因固定引线而对电路衬底作用横向的外力,故在模制的工序中可防止电路衬底的背面自模腔的下面脱离.
附图说明
图1是本发明混合集成电路装置的立体图(A)、剖面图(B)、剖面图(C);
图2是说明本发明混合集成电路装置制造方法的平面图(A)、剖面图(B);
图3是说明本发明混合集成电路装置制造方法的平面图;
图4是说明本发明混合集成电路装置制造方法的平面图(A)、剖面图(B);
图5是说明本发明混合集成电路装置制造方法的剖面图(A)、剖面图(B)、剖面图(C);
图6是说明本发明混合集成电路装置制造方法的剖面图(A)、剖面图(B);
图7是说明本发明混合集成电路装置制造方法的剖面图;
图8是说明本发明混合集成电路装置制造方法的平面图;
图9是说明本发明混合集成电路装置制造方法的平面图;
图10是说明现有的混合集成电路装置的立体图(A)、剖面图(B);
图11是说明现有的混合集成电路装置制造方法的剖面图(A)、剖面图(B)。
具体实施方式
参照图1说明本发明混合集成电路装置10的结构。图1(A)是混合集成电路装置10的立体图,图1(B)是图1(A)X-X’线的剖面图。
本发明的混合集成电路装置10具有在表面上形成由导电图案18和电路元件14构成的电路的电路衬底16、和密封电路并至少覆盖电路衬底16表面的密封树脂12。以下说明这样的各构成要素。
电路衬底16是由铝或铜等金属构成的衬底。作为一例在电路衬底16采用由铝构成的衬底时,使电路衬底16和在其表面上形成的导电图案18绝缘的方法有两种。一个是对铝衬底表面进行防蚀处理的方法。另一个方法是在铝衬底的表面上形成绝缘层17,然后在绝缘层17的表面上形成导电图案18的方法。在此,为了使由被载置于电路衬底16表面上的电路元件14产生的热更好地排出到外部,而使电路衬底16的背面从密封树脂12露出到外部。
电路元件14被固定在导电图案18上,由电路元件14和导电图案18构成规定的电路。电路元件14采用晶体管或二极管等有源元件、及电容或电阻等无源元件。另外,也可以介由由金属构成的散热器将功率系半导体元件等发热量大的元件固定在电路衬底16上。在此,面朝上安装的有源元件等介由金属线15与导电图案18电连接。
导电图案18由铜等金属构成,且和电路衬底16绝缘。另外,在导出引线11的边上形成由导电图案18构成的焊盘18A。在此,在电路衬底16的一边附近设置多个对准排列的焊盘18A。另外,导电图案18被作为粘结剂的绝缘层17A粘结在电路衬底16的表面上。
焊盘18A由导电图案18的一部分构成,其是固定引线的部分。在本实施例中,相对于电路衬底16大致垂直延伸的第二延伸部11B的前端部接触焊盘18A。因此,焊盘18A的大小只要比引线11的剖面大一些即可。因此,可减小各焊盘18A,使装置整体小型化。
引线11被固定在设于电路衬底16周边部的焊盘18A上,具有例如与外部进行输入、输出的作用。在此,一边上设有多条引线11。引线11和焊盘18A的粘结介由焊锡(焊料)等导电性粘结剂进行。另外,也可以在电路衬底16的相对的边上设置焊盘18A,并在该焊盘上固定引线11。
参照图1(B),引线11由介由弯曲部11C连续的第一延伸部11A及第二延伸部11B构成。第一延伸部11A相对于电路衬底16的面方向大致水平地延伸。第二延伸部11B相对于电路衬底16的面方向大致垂直地延伸,且其前端部介由焊料19被固定在焊盘18A上。在本实施例中,最好使第二延伸部11B垂直地与电路衬底16面方向接触,但第二延伸部11B和电路衬底16面方向所形成的角度也可以在80度~100度之间。
参照图1(C),在此,引线11被弯曲成圆弧状,具体地说,第一延伸部11A相对于电路衬底16的面方向大致平行地延伸。而且,介由弯曲部11C描绘出圆弧状这样延伸的第二延伸部11B的前端部介由焊料19被固定在焊盘18A上。
密封树脂12利用使用热硬性树脂的传递模模制、或使用热塑性树脂的注入模模制形成。在此,形成密封电路衬底16及形成于其表面上的电路的密封树脂12,且电路衬底16的背面自密封树脂12露出。
参照图2之后,说明混合集成电路装置10的制造方法。混合集成电路装置的制造方法包括:形成由在电路衬底16表面上形成的导电图案18及与导电图案18电连接的电路元件14构成的电路的工序;在由沿电路衬底侧边配置的导电图案18构成的焊盘18A上相对于电路衬底16的面方向大致垂直地固定引线11前端部的工序;将电路衬底16收纳于模制模具30的模腔31内,并通过由模制模具30夹持引线11使电路衬底16的背面接触模腔31底面的工序;通过向模腔31内部封入密封树脂12,使电路衬底16的背面露出到外部而进行密封的工序。以下说明该制造方法。
首先,参照图2(A)及图2(B),在电路衬底16的表面形成由导电图案18及电路元件14构成的电路。作为导电图案18的制造方法,首先,介由绝缘层17将导电箔粘结在电路衬底18的表面上。然后,通过蚀刻该导电箔,得到具有所希望的图案形状的导电图案18。另外,在导电图案18的所希望的位置配置电路元件14,并通过使用金属细线15电连接而构成所希望的电路。电路元件14可全部采用半导体元件等有源元件、或者电阻或电容等无源元件。另外,象功率系半导体元件这样伴随大的发热的元件也可以介由散热器等固定在安装衬底16上。
其次,参照图3~图5说明将引线11固定在电路衬底16上的工序。首先,参照图3说明引线架20的结构。在本发明中,引线11以引线架20的状态进行供给。即本发明的引线架20固定多个由配置了引线11及电路衬底16的区域A1构成的单元21。另外,引线架20具有长方形外形,各单元21被以一定的间隔分开而配置有多个。在各单元21之间设有狭缝25,其吸收由模制等伴随加热的工序产生的热应力。另外,在引线架20纵向的两周边部设置导孔22,该导孔用于各工序中的定位。另外,在各单元21内设置的多条引线11通过第一连接部23及第二连接部24连接,其形状及位置被固定。
在各单元21内设有支承部26及突出部25。突出部25是从各单元21的两端向内侧延伸的部位,其平面形状及位置与图1所示的固定部13相同。支承部26由以后的树脂密封工序埋入密封树脂内,从而具有直至最终工序使电路装置和引线架20一体地连接的作用。支承部26的形状形成其内部具有孔部的形状,通过向该孔部内填充密封树脂来提高支承部26和密封树脂的结合力。另外,支承部26在各单元21的对向的边上各形成两个,在以后的工序中强化电路装置和引线架20的结合。这样,由于通过在支承部26上设置孔部支承部26和引线架20的机械结合减弱,故可容易地进行以后工序中的电路装置和引线架20的分割。另外,支承部26形成在除配置电路衬底16的予定区域A1以外的区域的单元21内。这样,通过配置支承部26可防止将支承部26埋入密封树脂内而导致的电路装置的耐湿性降低。
其次,参照图4,在引线架20的各单元21固定电路衬底16。图4(A)是显示本工序的平面图,图4(B)是从剖面方向D1看到的剖面图。电路衬底16与引线架20的固定通过介由焊锡等焊料固定各单元21的引线11的先端部和电路衬底16的焊盘18A来进行。参照图4(B),在焊盘18A上固定的部分的引线11相对于电路衬底16以大致垂直的方向接触。
其次,参照图5说明引线11和电路衬底16的相关结构。图5(A)~图5(C)是各方式的引线11的连接结构的剖面图。
参照图5(A),在此,在设于一侧边上的焊盘18A上固定引线11。具体地说,相对于电路衬底16面方向而向垂直方向延伸的第二延伸部11B的前端部介由焊料被固定在焊盘18A上。
参照图5(B),在此,在对向的两个侧边上设置焊盘18A,并在这些焊盘18A上固定引线11。在此,虽然在两个侧边上固定引线11,但也可以在四个侧边上固定引线11。
参照图5(C),在此,圆弧状延伸的第二延伸部11B的前端部被固定在焊盘18A上。在此,圆弧状形成的第二延伸部11B的前端部相对于电路衬底16的面方向大致垂直地接触。即第二延伸部11B的前端部切线方向11D和电路衬底16的面方向形成垂直。另外,在本实施例中,切线方向11D和电路衬底16的面方向所构成的角度α可在80度~100度的范围内进行变化。如为该范围内的α,则可在以后的模制工序中防止电路衬底16的背面自模腔31的下面上浮。
当上述角度α小于80度或大于100度时,在以后的模制工序中向引线11的第一延伸部11A作用了下向的外力时,弯曲部11C的部分的引线11有可能变形。当引线11变形时,会产生电路衬底16向横向移动或电路衬底16倾斜等问题。
其次,参照图6~图8,使电路衬底16的背面露出,利用密封树脂12进行密封。首先,参照图6,将电路衬底16收纳入进行密封的模具30内部。图6(A)及图6(B)是本工序的剖面图。在此说明密封一个电路衬底16的方法,但实际上是在多个电路衬底16由引线架20连接的状态下进行本工序。
首先,参照图6(A)说明进行密封的模具30和电路衬底16的相关结构。模具30由上模30A及下模30B构成,通过使两者上下接触而形成进行密封的空间即模腔31。另外,在上模30A及下模30B设置有接触部32A及接触部32B,通过由这些接触部32夹持引线11进行电路衬底平面位置的固定。该图中表示在将电路衬底16载置到下模30B上后使上模30A与下模30B接触的状态。在此,设模腔31的下面和下模接触部32A上端的上下方向的距离为D1。而且,设电路衬底16的下面和引线11的下面的上下方向的距离为D2。这样,在本实施例中,D1被设定得比D2更短。当利用该结构将电路衬底16载置到下模30B下面时,在引线11和接触部32B之间形成与D1和D2之差对应的间隙。
参照图6(B),将上模30A向下方按压直至使引线11接触接触部32B。由此,在模腔31内部,电路衬底16相对于模腔31的下面被按压。具体地说,接触部32A将引线11的第一延伸部11A向下方压入,电路衬底16被间接地向下方按压。另外,由于引线11的第二延伸部11B相对于电路衬底16垂直地延伸,故上述压入几乎不产生横向的外力。因此,在本工序中,可防止压入引线11而产生的电路衬底16的上浮。另外,由于可使电路衬底16和模腔的下面密切接触,故也可以防止密封树脂回绕到电路衬底16的背面。
参照图7,通过自浇口G向模腔31内部封入密封树脂12而进行模制。浇口G被设于比电路衬底16的上面更位于上方的位置的模具30的侧边。在该图中与固定引线11的边对向而设置浇口G,但也可以在位于纸面进深方向的模具的侧边上设置浇口G。进行密封直至密封树脂12填充模腔31,完成模制工序。在密封工序阶段,由于电路衬底16的背面接触模腔的下面,故形成电路衬底16的背面自密封树脂12露出的结构。
参照图8说明完成模制工序后引线架20的平面状态。该图是图3所示引线架20的局部放大平面图。
形成密封在各单元21内固定的电路衬底16的密封树脂。在对应突出部25区域的位置不形成密封树脂12。因此,该位置形成图1所示的固定部13。另外,支承部26在模制工序被埋入密封树脂12内。该图中虚线表示被埋入密封树脂内的部分的支承部26。
其次,参照图9,自各单元21分离引线11。在此,利用冲裁等除去方法切除虚线所示的第一连接部23,将各引线11机械地、且电性地分离。进一步通过切割连接于第二连接部24的部分的引线11将引线11自引线架20分离。通过机械地分离引线架20和引线11,介由支承部26连接树脂密封后的电路衬底16和引线架20。因此,在本实施例中即使在进行引线11的分离后也可以一体地支承各单元21的混合集成电路装置和引线架20,故具有易于进行工序间的搬运等优点。
完成上述工序后,经由将引线11弯曲成所希望的形状而进行成形的工序、将混合集成电路装置自引线架20分离的工序、计测各混合集成电路装置电特性的工序,完成例如如图1所示的混合集成电路装置10。
Claims (8)
1、一种混合集成电路装置,其特征在于,包括:电路衬底;在所述电路衬底的表面上形成的导电图案;电连接在所述导电图案上的电路元件;固定在由所述导电图案构成的焊盘上的引线,其中,所述引线的前端部相对于所述电路衬底的面方向大致垂直地固定在所述焊盘上。
2、如权利要求1所述的混合集成电路装置,其特征在于,具有至少覆盖所述电路元件表面而形成的密封树脂,且所述焊盘和所述引线的连接部被所述密封树脂覆盖。
3、如权利要求1所述的混合集成电路装置,其特征在于,所述引线由第一延伸部和第二延伸部构成,所述第一延伸部相对于所述电路衬底的面方向大致水平地延伸,所述第二延伸部介由弯曲部与所述第一延伸部连接,并相对于所述电路衬底的面方向大致垂直地延伸,所述第二延伸部的前端被固定在所述焊盘上。
4、一种混合集成电路装置的制造方法,其特征在于,包括:构成电路的工序,该电路由在电路衬底表面上形成的导电图案及与所述导电图案电连接的电路元件构成;在由所述导电图案构成的焊盘上相对于所述电路衬底的面方向大致垂直地固定引线前端部的工序;将所述电路衬底收纳入模制模具的模腔内,通过由所述模制模具夹持所述引线,使所述电路衬底的背面接触所述模腔底面的工序;通过向所述模腔内部封入密封树脂,使所述电路衬底的背面露出外部进行密封的工序。
5、如权利要求4所述的混合集成电路装置的制造方法,其特征在于,所述引线由第一延伸部和第二延伸部构成,所述第一延伸部相对于所述电路衬底的面方向大致水平地延伸,所述第二延伸部介由弯曲部与所述第一延伸部连接,且相对于所述电路衬底的面方向大致垂直地延伸,所述第一延伸部由所述模具夹持。
6、如权利要求5所述的混合集成电路装置的制造方法,其特征在于,所述引线的自弯曲部附近至前端部的部分弯曲成圆弧状,且相对于所述电路衬底的面方向,所述前端部的切线方向大致为直角。
7、如权利要求4所述的混合集成电路装置的制造方法,其特征在于,所述引线的前端部与所述电路衬底接触的角度在80度~100度的范围内。
8、如权利要求4所述的混合集成电路装置的制造方法,其特征在于,通过由所述模具夹持所述引线,介由所述引线将所述电路衬底的背面压在所述模腔的底面。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP428410/03 | 2003-12-24 | ||
JP428410/2003 | 2003-12-24 | ||
JP2003428410A JP2005191147A (ja) | 2003-12-24 | 2003-12-24 | 混成集積回路装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1638104A true CN1638104A (zh) | 2005-07-13 |
CN100336209C CN100336209C (zh) | 2007-09-05 |
Family
ID=34787391
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004101021533A Expired - Fee Related CN100336209C (zh) | 2003-12-24 | 2004-12-20 | 混合集成电路装置的制造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20050161782A1 (zh) |
JP (1) | JP2005191147A (zh) |
KR (1) | KR20050065328A (zh) |
CN (1) | CN100336209C (zh) |
TW (1) | TW200526087A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102347245A (zh) * | 2010-07-22 | 2012-02-08 | 安森美半导体贸易公司 | 电路装置的制造方法 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102008003790A1 (de) | 2008-01-10 | 2009-07-16 | Robert Bosch Gmbh | Elektronisches Bauteil und Verfahren zur Herstellung des elektronischen Bauteils |
JP2012069764A (ja) * | 2010-09-24 | 2012-04-05 | On Semiconductor Trading Ltd | 回路装置およびその製造方法 |
USD637192S1 (en) | 2010-10-18 | 2011-05-03 | Apple Inc. | Electronic device |
USD709894S1 (en) | 2012-09-22 | 2014-07-29 | Apple Inc. | Electronic device |
TWD190983S (zh) * | 2017-02-17 | 2018-06-11 | 三星電子股份有限公司 | 固態硬碟儲存裝置 |
USD869469S1 (en) * | 2018-04-09 | 2019-12-10 | Samsung Electronics Co., Ltd. | SSD storage device |
USD869470S1 (en) * | 2018-04-09 | 2019-12-10 | Samsung Electronics Co., Ltd. | SSD storage device |
DE102020114442A1 (de) * | 2020-05-29 | 2021-12-02 | Danfoss Silicon Power Gmbh | Halbleiterbauelement |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5756527Y2 (zh) * | 1977-02-25 | 1982-12-04 | ||
US5233131A (en) * | 1990-12-19 | 1993-08-03 | Vlsi Technology, Inc. | Integrated circuit die-to-leadframe interconnect assembly system |
DE4418426B4 (de) * | 1993-09-08 | 2007-08-02 | Mitsubishi Denki K.K. | Halbleiterleistungsmodul und Verfahren zur Herstellung des Halbleiterleistungsmoduls |
US5497032A (en) * | 1993-03-17 | 1996-03-05 | Fujitsu Limited | Semiconductor device and lead frame therefore |
US5501755A (en) * | 1994-02-18 | 1996-03-26 | Minnesota Mining And Manufacturing Company | Large area multi-electrode radiation detector substrate |
JP3201187B2 (ja) * | 1994-12-08 | 2001-08-20 | 富士電機株式会社 | 半導体装置 |
US5675181A (en) * | 1995-01-19 | 1997-10-07 | Fuji Electric Co., Ltd. | Zirconia-added alumina substrate with direct bonding of copper |
US6259157B1 (en) * | 1998-03-11 | 2001-07-10 | Sanyo Electric Co., Ltd. | Hybrid integrated circuit device, and method of manufacturing thereof |
JP3547333B2 (ja) * | 1999-02-22 | 2004-07-28 | 株式会社日立産機システム | 電力変換装置 |
US6489879B1 (en) * | 1999-12-10 | 2002-12-03 | National Semiconductor Corporation | PTC fuse including external heat source |
JP2002043496A (ja) * | 2000-07-21 | 2002-02-08 | Hitachi Ltd | 半導体装置 |
-
2003
- 2003-12-24 JP JP2003428410A patent/JP2005191147A/ja not_active Withdrawn
-
2004
- 2004-11-22 TW TW93135809A patent/TW200526087A/zh unknown
- 2004-12-17 KR KR1020040108078A patent/KR20050065328A/ko not_active Application Discontinuation
- 2004-12-20 CN CNB2004101021533A patent/CN100336209C/zh not_active Expired - Fee Related
- 2004-12-22 US US10/905,251 patent/US20050161782A1/en not_active Abandoned
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102347245A (zh) * | 2010-07-22 | 2012-02-08 | 安森美半导体贸易公司 | 电路装置的制造方法 |
CN102347245B (zh) * | 2010-07-22 | 2015-06-17 | 半导体元件工业有限责任公司 | 电路装置的制造方法 |
Also Published As
Publication number | Publication date |
---|---|
TW200526087A (en) | 2005-08-01 |
JP2005191147A (ja) | 2005-07-14 |
CN100336209C (zh) | 2007-09-05 |
KR20050065328A (ko) | 2005-06-29 |
US20050161782A1 (en) | 2005-07-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1235288C (zh) | 导线接合性增强的半导体器件组件 | |
US11978700B2 (en) | Power semiconductor module arrangement | |
CN1104741C (zh) | 半导体封装及其制造方法 | |
CN100594602C (zh) | 半导体装置及其制造方法 | |
US20070138624A1 (en) | Semiconductor device | |
CN1127761C (zh) | 半导体装置 | |
CN1139989C (zh) | 半导体模块及使用该半导体模块的电力变换装置 | |
US8598697B2 (en) | Power semiconductor module, method for producing a power semiconductor module and a housing element for a power semiconductor module | |
CN1501485A (zh) | 电子器件 | |
CN1755919A (zh) | 电路装置及其制造方法 | |
CN1499622A (zh) | 引线框及制造方法以及树脂密封型半导体器件及制造方法 | |
CN1856219A (zh) | 电子电路装置及其制造方法 | |
CN100336209C (zh) | 混合集成电路装置的制造方法 | |
CN1645579A (zh) | 混合集成电路装置的制造方法 | |
CN1832659A (zh) | 电路装置及其制造方法 | |
CN1309071C (zh) | 引线框架以及制造该引线框架的方法 | |
CN105633023A (zh) | 半导体装置 | |
TWI248175B (en) | Semiconductor device | |
CN102437444B (zh) | 电气的连接装置 | |
CN1649140A (zh) | 混合集成电路装置及其制造方法 | |
CN100555609C (zh) | 混合集成电路装置及其制造方法 | |
CN1705085A (zh) | 电路装置的制造方法 | |
CN1179626A (zh) | 一种改进的表面封装的大功率半导体封壳及其制造方法 | |
CN114566473A (zh) | 包括具有嵌入的封装式半导体芯片的引线框的印刷电路板 | |
CN1305618A (zh) | 制造集成电路卡的方法和按照这种方法制造的卡 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070905 Termination date: 20100120 |