CN1592964A - 在铜晶种沉积后的植入方法 - Google Patents
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Abstract
一种制造集成电路的方法，该方法是可包括：沿通孔孔洞的侧壁及底部形成阻障层；形成相近且顺应(conformal)于该阻障层的晶种层；以及形成相近且顺应于该阻障层与该晶种层的植入层。该通孔孔洞是用以容纳通孔材料以电性导接第一导电层与第二导电层。
Description
技术领域
本发明一般是有关在一种集成电路与制造集成电路的方法，特别是，本发明是有关于一种在铜晶种沉积后的植入方法。
背景技术
半导体装置或集成电路可包含数百万例如晶体管的组件。超大型尺寸积体(ULSI)电路可包括有互补式金属氧化物半导体(CMOS，complementary metal oxide semiconductor)场效晶体管(FET)。尽管现有系统与工艺有能力在集成电路上制造数百万的集成电路装置，惟其仍然需要减少集成电路装置的特征尺寸，进而藉此增加在集成电路上的装置数量。然而，其仍有许多因素使得持续微小化集成电路遭逄困难。例如，当通孔(via)尺寸(或者是用以电性连接分离导电层的集成电路层间的信道)减小，然而电阻增加。
现有集成电路是利用通孔来连接结构(例如闸极、汲极区、源极区)以及导电线路。通孔一般为延伸通过绝缘层的金属栓塞(metal plug)。阻障层是用以保护该通孔避免金属扩散及电子迁移(electromigration，EM)干扰。该阻障层可有效提供关于通孔金属的阻抗。由于导体电子与扩散金属原子之间的动量交换，因而电子迁移是为主要运输方式。电子迁移产生对位于集成电路中金属导体的逐渐伤害。一般而言，其特性是在金属位于非常高的电流密度以及在100℃的温度或更高的情况下。
当该通孔尺寸透过减少该阻障材料的厚度而减小时，集成电路制造已试图减少通孔阻抗。根据一现有工艺，电浆气相沉积(PVD)，由于采用非顺应(non-conformal)沉积，集成电路业者可沈积非常薄的阻障材料在该通孔的底部。该阻障材料的厚度是藉由化学气相沉积(CVD)或原子层沉积(ALD)工艺而减小。该些先进的沉积工艺形成高顺应阻障金属薄层。然而，减低该阻障材料的厚度将导致铜(Cu)扩散变得更加可渗透该阻障，如此反而不利地影响对于电子迁移的阻抗。
第1图是显示集成电路的部分100的剖面示意图，该集成电路包括有铜层110、铜通孔120、铜层130、介电层150以及介电层160。通孔120及铜层130是为阻障层140所分隔。
该部分100也包括有藉由蚀刻挡止层144而与铜层130分隔的介电层142。介电层142可为氧化物且蚀刻挡止层144可为氮化硅(SiN)。蚀刻挡止层144预止自铜层130的铜扩散至介电层142。介电层150可藉由阻障层152而与铜层130分隔。同样地，介电层160可藉由阻障层162而与铜层110分隔。阻障层152及162可为氮化钽(TaN)。蚀刻挡止层172，174，176及178也可提供不同部分或不同层的分隔。蚀刻挡止层172，174，176及178可为氮化硅(SiN)。
根据现有工艺，阻障层140可具有横截面厚度在7nm至25nm之间。阻障层140限制由层间铜离子扩散到通孔120且形成通孔至介电层142。现有阻障层可包括氮化钽(TaN)。
第1图显示依据双镶嵌(dual damascene)工艺所形成的部分，其中铜层110及铜通孔120是由一步骤或工艺而沉积，且未为阻障材料所分隔。
如先前所讨论，现有系统具有企图来降低阻障层140的厚度，藉以减少关于通孔120的阻抗。然而，此厚度的降低可能导致电子迁移失败。第2图显示参阅第1图所描述的部分100，更进一步具有电子迁移失败(electromigration failure)或在铜层130中的空隙(void)45。第2图显示依据双镶嵌工艺(如参阅第1图所描述)所形成的部分，其中铜层110及铜通孔120是形成在一步骤或工艺。
第3图显示由于自铜层110大量扩散所造成具有电子迁移失败或在通孔120中形成有空隙155的部分100。第3图显示依据双镶嵌工艺(如参阅第1图所描述)所形成的部分，其中铜层110及铜通孔120是形成于一步骤或工艺。
电子迁移失败已由Stanley Wolf Ph.D.在「用于超大尺寸集成电路部分的硅工艺(Silicon Processing for the VLSI Era)」，Lattice Press，SunsetBeach，California，第二卷，第264-65页(1990年)所讨论。Wolf博士解释导体离子运动的正向分歧(positive divergence)导致空间的累积，而形成在金属中的空隙。该空隙可最终成长至一尺寸而导致该导线的断路(open-circuit)失败。
因此，需要可对应铜扩散提供有效阻抗的阻障。进一步需要在铜晶种沉积后植入阻障材料的方法。更进一步需要藉由提供近似晶种层的界面层(interfacial layer)而加强阻障特性的方法。进一步，需要植入组件至晶种层中。
发明内容
一典型实施例是有关于制造集成电路的方法。该方法是包括：沿通孔孔洞的侧壁及底部形成阻障层；形成相近且顺应(conformal)于该阻障层的晶种层；以及形成相近且顺应于该阻障层与该晶种层的植入层。该通孔孔洞是用以容纳通孔材料以电性导接第一导电层与第二导电层。
另一典型实施例是有关于在集成电路制造过程中，在铜晶种沉积后的植入方法。该方法可包括在集成电路基材上提供第一导电层；提供顺应层(conformal layer)部分于位于该第一导电层上的通孔孔洞的底部及侧边，以形成分隔该通孔孔洞与该第一导电层的阻障；植入组件至该顺应层部分，以在该顺应层部分中形成植入层；以通孔材料填充该通孔孔洞；以及在该通孔材料上提供第二导电层，藉以使该通孔材料电性连接该第一导电层与第二导电层。
另一典型实施例是有关于在集成电路中形成通孔的方法。该方法可包括沉积第一导电层；在该第一导电层上沉积蚀刻挡止层；在该蚀刻挡止层上沉积绝缘层；在该绝缘层及该蚀刻挡止层中形成孔洞；在该孔洞底部及侧边提供阻障材料以形成阻障层；在该阻障层上提供晶种层；提供植入物至该阻障层及晶种层以形成植入层；以通孔材料填充该孔洞；以及在该通孔上提供第二导电层，如此使该通孔电性连接该第一导电层与第二导电层。
依据检阅以下图式、详细说明以及所附申请专利范围，对于熟习此项技术者而言，本发明其它主要的特征及优点将变得明显。
附图说明
典型实施例将参阅以下附图而加以描述，其中相同数目标示同样组件。
第1图是为依据现有技术所制造的集成电路的双镶嵌部分的剖面示意图；
第2图是为如第1图所述的集成电路的双镶嵌部分显示电子迁移失败的剖面示意图；
第3图是为如第1图所述的集成电路的双镶嵌部分显示电子迁移失败的剖面示意图；
第4图是为依据典型实施例的集成电路部分显示晶种/阻障界面层的剖面示意图；
第5图是为依据另一典型实施例的集成电路部分显示阻障/介电界面层的剖面透视图；
第6图是为依据另一典型实施例的集成电路部分显示晶种植入层的剖面透视图；以及
第7图是为依据另一典型实施例的集成电路部分显示植入步骤的剖面透视图。
具体实施方式
参阅第4图所示，集成电路的部分400包括有基材层410、阻障层420、晶种/阻障界面层(seed/barrier interfacial layer)430、以及晶种层440。基材410可为介电层或不同层的任意变化而不发生扩散(diffusion)或迁移(migration)现象。
阻障层420是用以提供预防材料扩散至基材层410。阻障层420可为钽(Ta)、氮化钽(TaN)、氮硅化钽(TaSiN)或任何其它阻障材料的变化。在一例子中，阻障层420可具有一横截面厚度为30-70埃(Angstrom)。晶种层440可包括铜(Cu)或铜合金且可具有横截面厚度为100-300埃。
在第一典型实施例中，晶种/阻障界面层430可包括不同组件，该组件是经植入而形成具有均匀分布组件的混合区。例如该晶种/阻障界面层430可包括第六周期金属组件(钽、鎢、铼、锇、铱、铂)、第五周期金属组件(铌、钼、钌、铑、钯)、及/或第四周期金属组件(钒、铬、铁、钴、镍)。该些元素具有形成具最高熔点及最高密度的金属材料特性。在一例子中，晶种/阻障界面层430可具有横截面厚度为10-30埃。在一较佳实例中，该晶种/阻障界面层430包括铼(Re)或铬(Cr)。
形成晶种/阻障界面层430的植入可使用超低能离子植入(ultra lowenergy ion implantation，ULEII)。使用超低能离子植入(ULEII)允许许多组件植入至晶种层440而无需制造铜合金目标(copper alloy target)，如同使用于电浆气相沉积(plasma vapor deposition)工具中。超低能离子植入也允许控制植入浓度及深度。有利地是，组件的均匀分布于晶种/阻障界面层430可改善电子迁移(EM)信赖性以及晶种层440与阻障层420之间的附着。
参阅第5图所示，集成电路的部分500包括有介电层510、阻障/介电界面层(barrier/dielectric interfacial layer)520、阻障层530以及晶种层540。
介电层510可为任意包括内阶介电(interlevel dielectric，ILD)的介电材料的变化。介电层510可为一层供形成通孔孔洞所通过，以形成如第7图所述的通孔。
在第二典型实施例中，阻障/介电界面层520可包括不同组件用以植入而形成具有均匀组件分布的混合区。阻障/介电界面层520可包括碳(C)、硼(B)、磷(P)、硅(Si)、氮(N)、铝(Al)、砷(As)、镓(Ga)或锗(Ge)元素。在一例子中，阻障/介电界面层520可具有横截面厚度在10-30埃。在一较佳实例中，该阻障/介电界面层520包括磷(P)或铝(Al)。
有利地是，组件的均匀分布于阻障/介电界面层520可改善阻障层530与介电层510之间的附着。如同晶种/阻障界面层430，阻障/介电界面层520可在超低能离子植入(ULEII)工艺中形成，藉此将允许植入许多组件而无需阻障合金目标(barrer alloy target)，例如在电浆气相沉积(PVD)工具中所使用的目标。
参阅第6图所示，集成电路的部分600包括有介电层610、阻障层620以及晶种植入层630。介电层610可包括任意介电材料的变化。介电层610可为一层如第7图所述的供通孔电性连接层间而通过。
阻障层620可为钽(Ta)、氮化钽(TaN)、氮硅化钽(TaSiN)或任意其它阻障材料。阻障层620可具有一横截面厚度为30-70埃。阻障层620可藉由原子层沉积(ALD)及/或化学气相沉积(CVD)所沉积。
在第三典型实施例中，植入组件至晶种植入层630可更改在晶种植入层630中的铜合金，而形成变更合金层以及改善电子迁移信赖性。在晶种植入层630所植入的组件可包括锌(Zn)、锡(Sn)、铬(Cr)、钙(Ca)、银(Ag)或铟(In)。植入可包含使用超低能离子植入(ULEII)工艺。另外，也可选择藉由电浆气相沉积(PVD)、化学气相沉积(CVD)或原子层沉积(ALD)沉积晶种植入层630。在一例子中，晶种植入层630的厚度在10-30埃。在一典型实施例中，热处理是用以促进植入物内部混合于晶种植入层630中的铜合金。在一较佳实例中，该晶种植入层包括锌或钙。选择组件可形成铜锌(CuZn)及铜钙(CuCa)层，以提供具有降低电阻的晶种植入层。该铜锌(CuZn)及铜钙(CuCa)晶种层也形成具有增加电子迁移阻抗的内联机(interconnect)。
有益地是，参阅第4-6图所描述的典型实施例是可形成电子迁移(EM)阻抗层或区域，藉以改善信赖性。该电子迁移(EM)阻抗层或区域包括作为层间部分的植入层。例如，参阅第4图所描述的晶种/阻障界面层430是为位于阻障层420及晶种层440之间的植入层。在另一例子中，参阅第4图所描述的阻障/介电界面层520是为位于介电层510及阻障层530之间的植入层。在又另一例子中，参阅第6图所描述的晶种植入层630是为相近阻障层620的植入层。
包括晶种/阻障界面层430、阻障/介电界面层520以及晶种植入层630与参阅第4-6图所描述的该多数的层可包括在作为通孔(via)所用的沟槽中的顺应层(conformal layer)区域中。该通孔可用以电性连接两层结构，例如藉由介电层分隔及通孔连接的二导电层结构。
参阅第7图所示，是为集成电路的部分700所呈现的剖面示意图，该部分700包括有孔洞705、介电层715、蚀刻挡止层725、铜层735、阻障层745以及晶种层755。阻障层745及晶种层755形成顺应层(conformal layer)区域，其可包括例如于第4-6图中所描述的晶种/阻障界面层430、阻障/介电界面层520或晶种植入层630的植入层。
部分700较佳是为具有百万或更多晶体管的超大尺寸积体(ULSI)电路的部分。部分700的制造是作为例如硅晶圆的半导体晶圆上的集成电路部分。
孔洞705的形成是预备为藉由蚀刻介电层715及蚀刻挡止层725的部分而形成通孔(via)。孔洞705可具有横截面宽度在50-200nm。孔洞705也可具有二区段，其中之一较另一者具有较小的宽度。例如，孔洞705的上区段可具有横截面宽度在100-150nm，以及孔洞705的下区段可具有横截面宽度在70-100nm。
在一典型实施例中，介电层715为氧化物材料且蚀刻挡止层725为氮化硅(SiN)或其它适合材料。蚀刻挡止层725预防铜自铜层735扩散至介电层715。
铜层735可为设置在相近通孔区域720的铜层。铜层735可为包括铜的合金。在另一实施例中，铜层730为多层的叠层。
阻障层745可为钽(Ta)、氮化钛(TiN)、氮硅化钛(TiSiN)、氮化钨(WNx)或其它合适材料。在一典型实施例中，阻障层745具有横截面厚度在30-70埃。阻障层745可藉由原子层沉积(ALD)及/或化学气相沉积(CVD)沉积。该阻障层745的阻障性质可藉由添加例如硼(B)、磷(P)、硅(Si)或锗(Ge)的植入物而加强。
晶种层755可为铜合金，例如包括有碳(C)、硫(S)、氯(Cl)及或掺杂任何其它适合材料的合金。晶种层755的沉积可藉由先进的电浆气相沉积(PVD)、化学气相沉积(CVD)或原子层沉积(ALD)形成。在一典型实施例中，晶种层755具有横截面厚度在100-300埃。
晶种层755可包括如第6图所述的晶种植入物。或者，晶种层755可藉由如第4图所述的晶种/阻障界面层而与阻障层745分隔。再者，在又另一实施例中，阻障层745可藉由如第5图所述的阻障/介电界面层而与铜层735或介电层715分隔。
在一制作部分700的典型方法中，在铜层735沉积后，蚀刻挡止层725是沉积在铜层735上，且介电层715是沉积在蚀刻挡止层725上。接着阻层沉积于介电层715。该阻层是用以图案化及蚀刻介电层715及蚀刻挡止层725以形成孔洞705。在沈积通孔材料于孔洞705以及沉积导电层以透过通孔电性连接至铜层735前移除该阻层。
在孔洞705内沈积通孔材料前，是沿孔洞705壁面形成阻障层745及晶种层755。阻障层745的形成可藉由原子层沉积(ALD)及/或化学气相沉积(CVD)。晶种层755的形成可藉由先进的电浆气相沉积(PVD)、化学气相沉积(CVD)或原子层沉积(ALD)。
在一典型实施例中，在形成阻障层745及晶种层755后，可藉由角度植入(angle implaant)或与无角度植入一起的角度植入而进行植入795。植入795的角度可为35及/或65度。该角度植入可为35至90度。在一典型实施例中，植入795是为一剂量例如在E16cm2-E15cm2范围内形成掺杂单层(doped monolayer)，且在0.25KeV-5.0KeV能量中植入。植入795可形成界面或植入层例如在第4-6图中所描述的该植入层。
达到在特定角度下植入795的植入技术是藉由旋转包括部分700的集成电路晶圆。如此，植入装置可导入于一方向，且由于该集成电路晶圆的旋转，植入795可沿通孔区域720的孔洞周缘侧壁来提供。在另一实施例中，该晶圆是可用于控制植入795的分布。
有益地是，该植入795的添加提供包括如第6图所述的晶种植入物的晶种层的产生。在另一实施例中，植入795提供如第4图所述的晶种/阻障界面层的产生，藉以分隔晶种层755及阻障层745。在又另一实施例中，植入795提供如第5图所述的阻障/介电界面层的产生，藉以分隔阻障层745及铜层735或介电层715。
在铜晶种沉积后，例如硼(B)、磷(P)或锗(Ge)的植入组件提供具有均匀组件分布的混合层的产生。例如，组件可利用1-2KeV能量以及5-7 E15cm2剂量植入。该包括有植入组件的混合层可改善层间附着效果，以及进一步的电子迁移信赖性。其也可形成阻障层的非晶(amorphous)部分而无需大量的晶粒边界(grain boundary)。
在图式中及先前所描述的典型实施例是为较佳态样，其应可了解到该些实施例仅是用以例示说明。其它实施例是可包括，例如不同植入种类方法。本发明并非用以局限在特定的实施例，但可延伸至不同变更、组合及交换而仍在所附的权利要求书的范畴及精神内。
Claims (10)
1.一种制造集成电路的方法，该方法是包含：
沿通孔孔洞(705)的侧壁及底部形成阻障层(530)，该通孔孔洞(705)是用以容纳通孔材料，所述通孔材料电性连接第一导电层与第二导电层；
形成相近且顺应在该阻障层的晶种层(540)；以及
形成相近且顺应于该阻障层的植入层(530)。
2.如权利要求1所述的方法，其中，该植入层(530)是为设置在该晶种层(755)与该阻障层(530)之间的晶种/阻障界面层。
3.如权利要求1所述的方法，其中，该植入层(520)是为设置在该阻障层(530)与位于该阻障层(530)下方的介电层之间的阻障/介电界面层。
4.如权利要求3所述的方法，其中，该植入层(520)是位在该晶种层(540)上方、该晶种层中间、或该晶种层(540)下方。
5.如权利要求1所述的方法，其中，该植入层(520)具有横截面厚度在10-30埃。
6.如权利要求1所述的方法，其中，该植入层(520)是藉由角度植入方式形成，藉以达到组件的均匀分布。
7.一种在集成电路工艺中在铜晶种沉积后的植入方法，该方法是包含：
在集成电路基材上提供第一导电层(735)；
在位于该第一导电层(735)上的通孔孔洞(705)的底部及侧边提供顺应层部分(745)，以形成分隔该通孔孔洞(705)与该第一导电层(735)的阻障(745)；
植入组件至该顺应层部分(745)，以在该顺应层部分(745)中形成植入层(520)；
以通孔材料填充该通孔孔洞(705)；以及
在该通孔材料上提供第二导电层，藉以使该通孔材料电性连接该第一导电层(735)与该第二导电层。
8.如权利要求7所述的方法，其中，将组件植入至该顺应层部分(745)以在该顺应层部分(745)中形成植入层(520)包括在该顺应层部分(745)中的晶种(440)层与阻障层(420)之间形成晶种/阻障界面层(430)。
9.如权利要求7所述的方法，其中，将组件植入至该顺应层部分(745)以在该顺应层部分中形成植入层包括在该顺应层部分(745)中的阻障层(520)与位于该顺应层部分(745)下方的介电层(510)之间形成阻障/介电界面层(520)。
10.如权利要求7所述的方法，其中，将组件植入至该顺应层部分(745)以在该顺应层部分(745)中形成植入层(520)是包括在该顺应层部分(745)中的晶种层(540)中形成植入层(520)。
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| CNB028234413A Expired - Fee Related CN100447978C (zh) | 2001-11-26 | 2002-10-11 | 在铜晶种沉积后的植入方法 |
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| EP (1) | EP1449248A2 (zh) |
| JP (1) | JP4685352B2 (zh) |
| KR (1) | KR20040064288A (zh) |
| CN (1) | CN100447978C (zh) |
| AU (1) | AU2002340177A1 (zh) |
| WO (1) | WO2003046978A2 (zh) |
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| CN101661922B (zh) * | 2009-07-30 | 2014-04-09 | 广州市香港科大霍英东研究院 | 一种高深宽比硅通孔铜互连线及其制备方法 |
| CN109216261A (zh) * | 2017-07-03 | 2019-01-15 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
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-
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-
2002
- 2002-10-11 JP JP2003548300A patent/JP4685352B2/ja not_active Expired - Fee Related
- 2002-10-11 CN CNB028234413A patent/CN100447978C/zh not_active Expired - Fee Related
- 2002-10-11 WO PCT/US2002/032554 patent/WO2003046978A2/en active Application Filing
- 2002-10-11 EP EP02778522A patent/EP1449248A2/en not_active Withdrawn
- 2002-10-11 KR KR10-2004-7007988A patent/KR20040064288A/ko not_active Application Discontinuation
- 2002-10-11 AU AU2002340177A patent/AU2002340177A1/en not_active Abandoned
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101661922B (zh) * | 2009-07-30 | 2014-04-09 | 广州市香港科大霍英东研究院 | 一种高深宽比硅通孔铜互连线及其制备方法 |
| CN109216261A (zh) * | 2017-07-03 | 2019-01-15 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
| CN109216261B (zh) * | 2017-07-03 | 2021-07-09 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
Also Published As
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| AU2002340177A1 (en) | 2003-06-10 |
| JP4685352B2 (ja) | 2011-05-18 |
| EP1449248A2 (en) | 2004-08-25 |
| WO2003046978A3 (en) | 2003-10-30 |
| CN100447978C (zh) | 2008-12-31 |
| US20040023486A1 (en) | 2004-02-05 |
| KR20040064288A (ko) | 2004-07-16 |
| JP2005510874A (ja) | 2005-04-21 |
| WO2003046978A2 (en) | 2003-06-05 |
| US6703307B2 (en) | 2004-03-09 |
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