CN1585114A - Semiconductor sealing baseplate structure of electric padding metal protective layer and producing method thereof - Google Patents
Semiconductor sealing baseplate structure of electric padding metal protective layer and producing method thereof Download PDFInfo
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- CN1585114A CN1585114A CNA031558194A CN03155819A CN1585114A CN 1585114 A CN1585114 A CN 1585114A CN A031558194 A CNA031558194 A CN A031558194A CN 03155819 A CN03155819 A CN 03155819A CN 1585114 A CN1585114 A CN 1585114A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/0361—Physical or chemical etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
- H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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Abstract
The structure and producing method of the base plate supplies an insulated layer which contains multiple hatches, and the inner circuit covered under the insulated layer. The conducting film is formed on the insulated layer and the hatch. The first resistance layer is formed on the conducting film on which the part of the conducting film is exposed. In the electroplate procedure, the circuit layer and conducting hatch are formed. Then the second resistance layer formed, cover the circuit layer outside the connecting pad with electrical property to expose the second resistance layer. After the electroplate procedure, the obstructed metallic layer is formed, remove the second, first resistance layers and the conducting film, the obstructed metallic layer exposed.
Description
Technical field
The invention relates to a kind of conductor package substrate construction and method for making thereof that the electric connection pad coat of metal is arranged; particularly about a kind of when making base plate line with conductive blind hole, the structure and the manufacturing method thereof thereof of formation coat of metal on the electric connection pad of substrate simultaneously.
Background technology
Compact, multi-functional at electronic product, at a high speed and under the development trend of high frequencyization, printed circuit board (PCB) (PCB) or IC base plate for packaging technology are also to fine rule road and small-bore development.At present printed circuit board (PCB) or IC base plate for packaging processing procedure are from the wire sizes more than traditional 100 μ m: comprise lead wide (Line width), wire pitch (Space) and depth-to-width ratio (Aspect ratio), reduce to about 30 μ m, and the littler circuit precision of research and development.
In the prior art, when the substrate conductor size when 40 μ m are above, with low cost and the traditional fast etching method of etching of general employing, shown in Figure 1A and Figure 1B, on the surface of insulating barrier 10, form metal level 11, then on metal level 11, be coated with a resistance layer 12, utilize wet etch method again, adopt the diffusion effect (Diffusion) of strong acid or highly basic etching solution 13 (Etchant) and treat that the surface molecular of etched metal level 11 carries out chemical reaction, remove to finish etching, thisly subtract (Subtractive) etching method to have high etch rates and low use cost, and (Uniformity) is higher for the etched conductive layer uniformity, because this etching method is to finish by the etching solution 13 and the chemical reaction of certain material, therefore its etching selectivity (Selectivity) is better than other method, can not remove and not want etched other material, but because this wet etching is for waiting tropism (Isotropic) etching, therefore when etching downwards, will cause undercutting (Undercut) phenomenon 14 shown in Figure 1B, influence the precision of processing procedure, the restriction of the quality transmission of this wet etch method (Mass transport) precision makes the precision of its etched conductor size be difficult to down develop again.
The dry ecthing method (Dry etching) that generally is used for manufacture of semiconductor, etching no matter splash (Sputtering etching) or electric paste etching (Plasma etching), its anisotropy (Anisotropic) though etching characteristic can reach thinner etching precision and the live width of having dwindled lead, but the low etch-rate that its per minute only can the several nanometers of etching (nm), only be applicable to the semiconductor chip that chip thickness is thin, base plate for packaging for thickness thicker (5 to 30 μ m), dry ecthing method consumed time cost is too big, simultaneously, dry ecthing method is a physical etch method for the treatment of etched surfaces with ion bombardment, its etching selectivity is unsatisfactory, therefore if adopt the omnidistance base plate for packaging of making of dry ecthing method, also may have conductive layer and suffer pollution problems.
Become (Substractive) etching method relatively with traditional subtracting, industrial circle adopts and can make the more addition on fine rule road (Additive) method at present, to satisfy the demand of more highdensity circuit board, typical method is to form a crystal seed layer (Seedlayer) with electroless coating copper on insulating circuit board, on insulating barrier, directly form circuit layer again, this method can be further divided into complete addition (Fully-additive) method and false add and become two kinds of processing procedures of (Semi-additive) method, the problem that runs into when avoiding etching.
The typical processes of semi-additive process that can make thin circuit at present is shown in Fig. 2 A to Fig. 2 F.
See also Fig. 2 A, at first, core circuit plate 20 comprises the circuit layer 21 of a plurality of patternings, is positioned at the insulating barrier 22 of 21 of two circuit layers, and as 21 of this circuit layers electrically in the plating via 23 that connects.
Shown in Fig. 2 B, provide two organic insulators 24 again, by the surface of vacuum pressing-combining to core circuit plate 20.
See also Fig. 2 C, then, patterning in organic insulator 24 forms a plurality of perforates 240, manifests the circuit layer 21 of part, and forms electroless coating copper lamina 25 on organic insulator 24 surfaces.
See also Fig. 2 D, on electroless coating copper lamina 25, lay the resistance layer (Resistlayer) 26 of a patterning, make resistance layer 26 form a plurality of openings (Opening) 260, to expose outside this electroless coating copper lamina 25.
See also Fig. 2 E, utilize plating mode to form line layer 27 again in resistance layer opening 260, this electroplated metal layer generally can be the conducting wire that metallic copper constitutes.
See also Fig. 2 F, afterwards, remove resistance layer 26 again and the electroless coating copper lamina 25 that covers after, can form four laminar substrates 200 of an additional layers.
Wherein, the surface that is used for conductor package substrate is formed with a plurality of conducting wires of being made up of copper product, and form electric connection pad by its part surface, with transmission of electric signals or power supply, simultaneously, generally can be formed with metal level at the exposed surface of electric connection pad,, also can avoid causing electrically connecting the oxidation of pad body because of the external environment influence so that the electrical couplings of electric connection pad and conductive component such as gold thread, projection or soldered ball and chip or circuit board effectively to be provided as nickel/gold (Ni/Au).
This electric connection pad can be the convex pads (Bump pad) or the prewelding soldering pad (Presolder pad) of semiconductor flip chip package substrate and chip electrical couplings, this electric connection pad also can be the weld pad (Finger) of routing type conductor package substrate and chip electrical couplings, and the solder ball pad (Ball pad) of base plate for packaging and circuit board electrical couplings for example.By electrically connecting pad body exposed surface formation nickel/gold metal layer, the electric connection pad (being generally metallic copper) that is coated in nickel/gold metal layer is difficult for because of external environment influence oxidation, plants electric connection quality in electric connection pad to improve projection, pre-scolding tin or soldered ball etc.
At present because the electroless coating copper lamina that comprehensive conducting of semi-additive process (SAP) processing procedure is used; just in addition etching (Etching) is removed after circuit graphic plating (Pattem plating) processing procedure is finished; then electroplate line layer and avoid external environmental for protection; promptly form and refuse solder flux (green lacquer) processing procedure at substrate surface; and the surface that makes electric connection pad be formed with nickel/gold (Ni/Au) metal level manifests the perforate of refusing layer; because before having electroplated the electroless coating copper layer that conducting uses removes; so must adopt electroless coating (Electro-less) mode usually; promptly do not have the driving force (Drivingforce) of external voltage, carried out.
See also Fig. 2 G and Fig. 2 H, what show among the figure is that the electric connection pad surface at base plate for packaging utilizes the electroless coating mode in the prior art, i.e. chemical nickel/golden processing procedure forms the method schematic diagram of nickel/gold metal layer.
See also Fig. 2 G, as previously mentioned, for making wherein nickel/gold metal layer correctly be deposited on the surface of electric connection pad, on base plate for packaging 200 surfaces of the line layer 27 that forms figure, printing (Printing) or coating (Coating) are refused layer (Soldermask) 28 as green lacquer, and the line layer 27 on these base plate for packaging 200 surfaces comprises a plurality of electric connection pads 270, and makes and refuse layer 28 and form perforate 280 at electric connection pad 270 places, to expose electric connection pad 270.
See also Fig. 2 H, when carrying out chemical nickel/golden processing procedure, substrate 200 is changed nickel soak golden processing procedure (Electroless Nickel/Immersion Gold (EN/IG)), by the perforate 280 of refusing layer, nickel/gold metal layer 29 is deposited on exposes electric connection pad 270 surfaces of refusing layer perforate 280.
Therefore, as mentioned above, because semi-additive process (SAP) processing procedure is to electroplate the general electroless coating copper lamina of figure line powering conductance, after finishing, the circuit patterning promptly removes, the electroless coating copper layer that the nickel gold metal layer that will form is then used because of the plating conducting is removed, so must adopt the electroless coating formula to form, processing procedure liquid in the general chemical nickel/golden processing procedure that adopts will be to being formed on refusing layer and carrying out corrosivity and attack of base plate for packaging surface, causing the problem that the peeling off of layer (Peeling) and nickel/reliabilities such as gold metal layer pollution on the electric connection pad reduce of refusing.
In addition, for according with the demands of the market, it is compact that semiconductor package is made every effort to, chip is also towards small size, highly integrated (Integration) development, therefore, preferably be laid with highdensity electric connection pad as the conductor package substrate of chip bearing member (Chipcarrier), so that the chip that is carried on the substrate can form good and complete electric connection with substrate, make highly integrated chip operate freely, thereby bring into play its function and characteristic fully.But because the IC base plate for packaging that is furnished with lead has the restriction on the processing procedure, it transmits chip signal and improves frequency range, functions such as control group limited, become the development obstacle of high I/O (I/O) class packaging part, and because basal plate making process occupies 20% to 50% of packaging cost, therefore the integrated circuit manufacture process at semiconductor chip has narrowed down to 0.13 μ m, and package dimension also constantly dwindles, during almost with chip same big (pact only is 1.2 times of chip), how to develop fine rule road (Fine circuit) with its collocation, the base plate for packaging of high density and small-bore is the important research and development problem that IC industry and even other associated electrical industry enter next-generation technology.
But if will be with the down development again of lead precision, dimensioned area and adjacent spacing (Pitch) with respect to electric connection pad on the substrate also need reduction thereupon, cause being formed on the electric connection pad place to refuse the layer perforate too little, cause in chemical nickel/golden processing procedure, because of liquid convection not good, it is not good that making nickel particles quality transmits (Mass transfer), the phenomenon of full plating appears being difficult for, make follow-up change gold immersion plating smoothly (Immersed) on nickel metal layer, therefore occur jumping the plating phenomenon, or make the surperficial excessively roughening of electric connection pad can't form nickel/gold metal layer of densification (Dense).
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of conductor package substrate construction and method for making thereof that the electric connection pad coat of metal is arranged, and can utilize plating mode to form the resistance barrier metal on electric connection pad surface.
Another object of the present invention is to provide a kind of conductor package substrate construction and method for making thereof that the electric connection pad coat of metal is arranged, can integrate the resistance barrier metal level that semi-additive process (SAP) forms line construction and plating mode formation electric connection pad surface simultaneously.
A further object of the present invention is to provide a kind of conductor package substrate construction and method for making thereof that the electric connection pad coat of metal is arranged; avoid in the existing chemical nickel and gold processing procedure; processing procedure liquid carries out corrosivity and attacks the layer of refusing on base plate for packaging surface, cause refuse layer peel off with electric connection pad on nickel/not good problems of reliability such as gold metal layer pollution.
Another purpose again of the present invention is to provide a kind of conductor package substrate construction and method for making thereof that the electric connection pad coat of metal is arranged; avoided not good in chemical nickel/golden processing procedure because of liquid convection; it is not good that making nickel particles quality transmits (Mass transfer); the phenomenon of full plating appears being difficult for; this can make follow-up change gold immersion plating smoothly (Immersed) on nickel metal layer; therefore occur jumping the plating phenomenon, or make the surperficial excessively roughening of electric connection pad can't form the problems such as nickel/gold metal layer of densification (Dense).
For reaching above-mentioned purpose, the invention provides a kind of method for making that the conductor package substrate construction of electric connection pad coat of metal is arranged, its main processing procedure comprises: an insulating barrier is provided, and is formed with a plurality of blind holes in this insulating barrier to appear the internal layer circuit that covers under the insulating barrier; Form a conducting film at insulating barrier and blind hole surface; On conducting film, form first resistance layer, and make first resistance layer form a plurality of openings exposed portions serve conducting film in addition; Carry out electroplating process and form conductive blind hole to form in figure line layer and the blind hole at insulating barrier in the first resistance layer opening, this figure line layer comprises a plurality of electric connection pads, and has at least an electric connection pad to be electrically connected to conductive blind hole; Form second resistance layer and cover electric connection pad figure line layer in addition, make electric connection pad expose outside second resistance layer; Carry out electroplating process on electric connection pad, to form resistance barrier metal level; And remove second resistance layer, first resistance layer and cover conducting film under first resistance layer.
Of the present invention have another method for making of the conductor package substrate construction of electric connection pad coat of metal mainly to comprise: an insulating barrier is provided, and is formed with a plurality of blind holes in the insulating barrier to appear the internal layer circuit that covers under the insulating barrier; Form a conducting film at insulating barrier and blind hole surface; On conducting film, form resistance layer, and this resistance layer is formed with a plurality of openings exposed portions serve conducting film in addition; Carry out electroplating process in the resistance layer opening, forming a plurality of electric connection pads and in the blind hole of insulating barrier, to form conductive blind hole, and this electric connection pad is electrically connected to conductive blind hole; Carry out electroplating process on electric connection pad, to form resistance barrier metal level; And remove resistance layer and cover conducting film under the resistance layer.Wherein, the corresponding insulating barrier blind hole of this resistance layer opening position.
Logical the present invention also provides a kind of conductor package substrate construction that the electric connection pad coat of metal is arranged, and this substrate mainly comprises: at least one insulating barrier is formed with a plurality of conductive blind holes, to be electrically connected to the internal layer circuit that covers under the insulating barrier in this insulating barrier; At least one figure line layer is formed on the insulating barrier with plating mode by a conducting film, and this figure line layer comprises a plurality of electric connection pads, wherein has at least an electric connection pad to be electrically connected to conductive blind hole; And at least one resistance barrier metal level, the complete electric connection pad upper surface that covers.
Because the present invention is with semi-additive process (SAP), when making figure circuit and conductive blind hole, utilize and electroplate required conducting film, collocation is resistance layer for the second time, carry out image transfer to define the zone of desiring plate surface metal level (for example nickel/gold (Ni/Au) metal level), also or only form and electrically connect pad area at substrate surface, on the upper surface of electric connection pad, form as electric connection pad as big or small nickel/gold metal layer, reach structure and the method for utilizing electronickelling/gold to replace existing chemical nickel/gold, and then avoid the existing all bad problem that chemical nickel/golden processing procedure causes.
In sum, the present invention can be when forming patterned circuit and conductive blind hole processing procedure, utilize the conducting film that comprehensively electrically conducts, also set up the second resistance layer image transfer to cover outer remaining the conductive trace zone of electric connection pad, also or only form electric connection pad at substrate surface, carry out electroplating process again on electric connection pad, to form resistance barrier metal level, hinder metal level so as to the resistance that in substrate, forms conducting wire, conductive blind hole, electric connection pad simultaneously and cover on it.Replace electroless coating (Electro-less) processing procedure, avoid the processing procedure liquid in the electroless coating processing procedure that the layer of refusing on base plate for packaging surface is carried out corrosivity and attacks, cause refuse layer peel off with electric connection pad on nickel/not good problems of reliability such as gold metal layer pollution, and avoid the processing procedure liquid convection that causes because of fine rule road design not good, form the phenomenon that is difficult for full plating, make follow-up change gold immersion plating smoothly (Immersed) on nickel metal layer, the plating phenomenon occurs jumping, or make this excessive roughening in electric connection pad surface can't form nickel/gold metal layer of densification (Dense).
Description of drawings
Figure 1A and Figure 1B are the basal plate making process schematic diagrames of existing wet etch method;
Fig. 2 A to Fig. 2 F is the basal plate making process schematic diagram of existing semi-additive process;
Fig. 2 G and Fig. 2 H are the existing processing procedure schematic diagrames that utilizes the electroless coating mode to form resistance barrier metal level on the electric connection pad surface of substrate;
Fig. 3 A to Fig. 3 I is the generalized section of the embodiment 1 of conductor package substrate construction that the electric connection pad coat of metal arranged of the present invention and method for making thereof;
Fig. 4 is the generalized section of the embodiment 2 of conductor package substrate construction that the electric connection pad coat of metal arranged of the present invention and method for making thereof;
Crystal formation ball grid array (CDBGA) semiconductor package part generalized section is put in Fig. 5 has the conductor package substrate construction of electric connection pad coat of metal to form for application is of the present invention basion;
Fig. 6 is for using the routing type semiconductor package part generalized section that the conductor package substrate construction formation of electric connection pad coat of metal is arranged of the present invention; And
Fig. 7 is for using the flip-chip type semiconductor packaging part generalized section that the conductor package substrate construction formation of electric connection pad coat of metal is arranged of the present invention.
Embodiment
Embodiment 1
Fig. 3 A to Fig. 3 J is the have conductor package substrate construction of electric connection pad coat of metal and the embodiment generalized section of method for making thereof of the present invention.
Of the present invention have the conductor package substrate construction of electric connection pad coat of metal to comprise: at least one insulating barrier 30 forms a plurality of conductive blind holes 301 to be electrically connected to the internal layer circuit 30a that covers under the insulating barrier 30 in this insulating barrier 30; At least one figure line layer 33 is formed on this insulating barrier 30 with plating mode by a conducting film 31, and this figure line layer 33 comprises a plurality of electric connection pads 330, wherein has at least an electric connection pad 330 to be electrically connected to conductive blind hole 301; And at least one resistance barrier metal level 35, the complete upper surface that covers electric connection pad 330.
As shown in Figure 3A; of the present invention have the method for making of the conductor package substrate construction of electric connection pad coat of metal to be; at first; one dielectric insulation layer 30 is provided; and be formed with a plurality of blind holes 301 in this insulating barrier 30; appearing the internal layer circuit 30a that covers under the insulating barrier, and form conducting films 31 at insulating barrier 30 and blind hole 301 surfaces.Insulating barrier 30 can be epoxy resin (Epoxyresin), polyimides (Polyimide), cyanate (Cyanate Ester), glass fibre (Glassfiber), ABF (Aiinomoto Build-up Film, Japanese trader's aginomoto company produces), bismaleimides/triazine (BT, Bismaleimide Triazine) or blending epoxy and glass fibre materials such as (FR5) constitute; Conducting film 31 carries out the required current conduction path of electroplated metal layer (comprising the resistance barrier metal level on figure line layer and the electric connection pad) mainly as aftermentioned, it can be made of metal, alloy or a storehouse number layer metal level, can be selected from the metal of the cohort that copper, tin, nickel, chromium, titanium, copper-evanohm constitute.Conducting film 31 can form by modes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless coating or chemical depositions, for example methods such as the chemical vapour deposition (CVD) that promotes of sputter (Sputtering), evaporation (Evaporation), electric arc steam deposition (Arc vapor deposition), ion beam sputter (Ionbeam sputtering), the molten deposition (Laser ablation deposition) of loosing of laser, electricity slurry or electroless coating.But according to the experience of practical operation, conducting film 31 preferably is made of the electroless coating copper particle.Wherein insulating barrier 30 is formed at the surface of multilayer circuit laminar substrate, and this substrate can be to have finished required FEOL, for example is formed with a plurality of vias (PTH) or blind hole etc. on it, for circuit between lamination electrically conduct (figure mark).
Shown in Fig. 3 B, on conducting film 31, utilize modes such as printing, spin coating or applying to cover first resistance layer 32 again, first resistance layer 32 can be the photoresist layer (Photoresist) of dry film or liquid photoresistance etc., and can make first resistance layer 32 form a plurality of openings 320 by the exposure (Exposure) and the patterning process such as (Development) that develops, so as to manifesting the partially conductive film 31 that will form the figure line layer.
Shown in Fig. 3 C, then carry out electroplating process, in the first resistance layer opening 320, to form figure line layer 33 and in insulating barrier blind hole 301, to form conductive blind hole 302, this figure line layer 33 comprises a plurality of electric connection pads 330, and electric connection pad 330 can be electrically connected to internal layer circuit 30a by the conductive blind hole 302 that is formed at insulating barrier 30.Wherein conductive blind hole 302 can be formed directly in below electric connection pad 330, or by the lead of figure line layer 33 electric connection pad 330 is electrically conducted to internal layer circuit 30a.
Shown in Fig. 3 D, form one second resistance layer 34, cover electric connection pad 330 figure line layer 33 in addition; Wherein second resistance layer 34 can be the photoresist layer (Photoresist) of dry film or liquid photoresistance etc., and can make second resistance layer 34 form a plurality of openings 320 by the exposure (Exposure) and the patterning process such as (Development) that develops, can be identical so as to the material that manifests electric connection pad 330, the second resistance layers 34 with the material of first resistance layer 32.
Shown in Fig. 3 E, then electroplate (Electroplating) processing procedure, by current conduction path such as conducting film 31, conductive blind hole 302 and electric connection pads 330, form a complete resistance barrier metal level 35 that covers electric connection pad 330 upper surfaces.This resistance barrier metal 25 can be gold, nickel, palladium, silver, tin, nickel/palladium, chromium/titanium, nickel/gold, palladium/gold or nickel/palladium/gold etc., preferable selection is electronickelling/gold metal layer, after it electroplates one deck nickel 351 earlier, electroplate one deck gold 352 (shown in Fig. 3 F) more thereon, make nickel/metal by the on the whole surface of conducting film 31 plating at each electric connection pad 330, the complete covering one resistance barrier metal level 35 of upper surface with electric connection pad 330, the selection of certain resistance barrier metal material of the present invention, can only be above-mentioned nickel also, one of gold or other metal, for example directly electroplate in appearing of electric connection pad surperficial with gold, other simple substitution all belongs to category of the invention process.
Shown in Fig. 3 G, remove second resistance layer 34 and first resistance layer 32, promptly form the surface on the whole that plating resist barrier metal level 35 covers electric connection pad 330.
Shown in Fig. 3 H, also remove the conducting film 31 that had before been covered by first resistance layer 32 by technology such as etchings.
Shown in Fig. 3 I; on the base plate for packaging surface coverage, one refuse layer (Solder mask) 36 afterwards; for example green lacquer; avoid external environment so as to the protection packaging substrate and pollute destruction; this is refused layer 36 and is formed with a plurality of perforates 360, the electric connection pad 330 of finishing plating resist barrier metal level 35 can be revealed in refuse layer perforate 360.
Embodiment 2
See also Fig. 4, in embodiment 2, can directly on substrate surface, form a plurality of electric connection pads 330, and in this insulating barrier 30, form conductive blind hole 302, and do not have all the other conductor part, these electric connection pads 330 can directly be electrically conducted to internal layer circuit 30a by the conductive blind hole 302 that is formed in the insulating barrier 30.On follow-up electric connection pad 330, electroplate in the processing procedure that forms resistance barrier metal level, owing to only be formed with electric connection pad at substrate surface, then need not to cover again second resistance layer and partly can directly carry out electroplating process, so as to complete covering one resistance layer metal level on the exposed surface of these electric connection pads.
As mentioned above, the present invention utilizes semi-additive process (SAP) to form circuit and the conductive blind hole that increases layer segment, utilize first resistance layer and the conducting film that forms this pattern structure then, and form second resistance layer (thin dry film) in addition again and cover the conductive trace part that does not form resistance barrier metal level, define the electric connection pad part that will form resistance barrier metal level, also or only form and electrically connect pad area at substrate surface, with conducting film by previous formation graph line line structure, conductive blind hole and electric connection pad, on electric connection pad, add for example nickel/gold (Ni/Au) metal level of plating one resistance barrier metal level, on electric connection pad, to form the resistance barrier metal-layer structure approximate with electric connection pad upper surface size, remove these resistance layers and conducting film afterwards again, with the follow-up processing procedure of refusing welding flux layer, finish table and on figure circuit and the electric connection pad resistance hinder the multilager base plate of metal level.
Fig. 5 has the formed basion of conductor package substrate construction of electric connection pad coat of metal to put crystal formation ball grid array (Cavity down ball grid arrays for application is of the present invention; CDBGA) semiconductor package part; its characteristics are; substrate wherein forms a perforate, and the semiconductor chip is electrically connected to substrate with upside down by this perforate.
This CDBGA semiconductor package part mainly forms the perforate 41 of at least always wearing its upper and lower surface in a ball grid array (BGA) conductor package substrate 40, and connect with fin 42 and to put on the upper surface of substrate 40 to close a side of perforate 41, semiconductor chip 43 is accommodated in the perforate 41, pass through a thermal conductivity adhesive with non-acting surface with chip 43, tight adhesion is on fin 42, and pass perforate 41 by many bonding wires 44, to electrically connect the electric connection pad 401 on semiconductor chip 43 and substrate 40 lower surfaces, and the surface of this electric connection pad 401 promptly covers a resistance barrier metal level 45 (as nickel/gold metal layer), effectively weld knot and be electrically conducted to electric connection pad 401 for bonding wire 44 (as gold thread), then, after coating semiconductor chip 43 and bonding wire 44 with packing colloid 46 again, on the electric connection pad 402 of substrate 40, plant and put a plurality of soldered balls 47, and the surface of this electric connection pad 402 also is coated with a resistance barrier metal level 45, effectively weld knot and be electrically conducted to electric connection pad 402 for soldered ball 47, integrate gelled semiconductor package part to finish.
Fig. 6 and Fig. 7 are for using a routing type and the flip-chip type semiconductor packaging part generalized section that the conductor package substrate construction formation of electric connection pad coat of metal is arranged of the present invention.
As shown in Figure 6, except that above-mentioned CDBGA semiconductor package part, the present invention also can be applicable to routing type (Wire bonding) semiconductor package part 50, it provides a routing type substrate 51, and will be at least semiconductor chip 52 connect and put behind substrate 51, utilize many bonding wires 53 chip 52 to be electrically connected on the electric connection pad 54 of substrate 51, and with electric connection pad 54 upper surfaces that bonding wire 53 is electrically conducted be the complete resistance barrier metal level 55 that is coated with as nickel/gold metal layer, effectively weld for bonding wire 53 (being generally gold thread) and to tie to electric connection pad 54.
As shown in Figure 7; the present invention also can be applicable to flip-chip type semiconductor packaging part 60; it provides a chip upside-down mounting type substrate 61; and will be at least semiconductor chip 62 connect and put behind substrate 61; utilize a plurality of metal couplings 63 on semiconductor chip 62 circuit face to be electrically conducted to the electric connection pad 64 on substrate 61 surfaces with flip chip; and hinder barrier metal level 65 as nickel/gold metal layer with complete being coated with of electric connection pad 64 upper surfaces that this metal coupling 63 is electrically conducted; not only can protect electric connection pad 64 not to be affected by the external environment and corrosion, and the weldering knot of metal coupling 63 with electric connection pad 64 can effectively be provided.
Therefore, the conductor package substrate construction that the electric connection pad coat of metal is arranged of the present invention except that can be applicable to routing type (Wire bonding) base plate for packaging, also can be applicable to the chip upside-down mounting type base plate for packaging; Have again, electric connection pad of the present invention, can sufficient wire pad, convex pads, prewelding soldering pad or solder ball pad etc., represent with the part electric connection pad among the previous figure, the number of actual this graph line line structure and electric connection pad, be according to the needs of actual processing procedure and designed and be distributed in substrate surface, and this processing procedure may be implemented in the single side or the two sided of substrate.
By conductor package substrate construction and the method for making thereof that the electric connection pad coat of metal is arranged of the present invention, not only can form the fine rule line structure of multilayer on the substrate and in insulating barrier, form conductive blind hole, simultaneously, also can on the electric connection pad of graph line line structure, electroplate and form the approximately uniform resistance barrier of size metal level, to increase electric connection pad and the contact area that hinders the barrier metal level, and effectively provide this electric connection pad and other conductive component (as metal coupling, soldered ball and bonding wire etc.) electrical couplings, also can avoid simultaneously causing the oxidation of this electric connection pad body because of the external environment influence; And the problem that produces when avoiding existing chemical nickel/golden processing procedure, effectively improve the reliability of encapsulating structure.Also have, though the at present also favourable resistance barrier metal level that forms the electric connection pad surface with plating mode, but the existing plating mode is to lay electroplated lead in addition by the surface at base plate for packaging, by this electroplated lead conducting to electric connection pad, but in this processing procedure because of the setting of these electroplated leads, to significantly reduce the base plate for packaging area that effectively connects up, and may derive problems such as noise jamming because of laying this electroplated lead.
Claims (26)
1. the conductor package substrate construction that the electric connection pad coat of metal is arranged is characterized in that, this conductor package substrate construction comprises:
At least one insulating barrier forms a plurality of conductive blind holes, to be electrically connected to the internal layer circuit that covers under the insulating barrier in this insulating barrier;
At least one figure line layer is formed on this insulating barrier with plating mode by a conducting film, and this figure line layer comprises a plurality of electric connection pads, wherein has at least an electric connection pad to be electrically connected to conductive blind hole; And
At least one resistance barrier metal level, the complete upper surface that covers electric connection pad.
2. the conductor package substrate construction that the electric connection pad coat of metal is arranged as claimed in claim 1; it is characterized in that; this conductor package substrate construction also comprises refuses layer; be formed at substrate surface; cover the figure line layer, and this is refused layer and a plurality of perforates is arranged to expose outside resistance barrier metal level.
3. the conductor package substrate construction that the electric connection pad coat of metal is arranged as claimed in claim 1 is characterized in that this insulating barrier is formed at the Mulitilayer circuit board surface.
4. the conductor package substrate construction that the electric connection pad coat of metal is arranged as claimed in claim 1 is characterized in that, this base plate for packaging is in chip upside-down mounting type base plate for packaging and the routing type base plate for packaging.
5. the conductor package substrate construction that the electric connection pad coat of metal is arranged as claimed in claim 1 is characterized in that this electric connection pad is a convex pads.
6. the conductor package substrate construction that the electric connection pad coat of metal is arranged as claimed in claim 1 is characterized in that this electric connection pad is a solder ball pad.
7. the conductor package substrate construction that the electric connection pad coat of metal is arranged as claimed in claim 1 is characterized in that this electric connection pad is a wire pad.
8. the conductor package substrate construction that the electric connection pad coat of metal is arranged as claimed in claim 1; it is characterized in that, the material of this resistance barrier metal level can be gold, nickel, palladium, silver, tin, nickel/palladium, chromium/titanium, nickel/gold, palladium/gold and group that nickel/palladium/gold constituted in a kind of.
9. the method for making that the conductor package substrate construction of electric connection pad coat of metal is arranged is characterized in that, the method for making of this conductor package substrate construction comprises:
One insulating barrier is provided, and is formed with a plurality of blind holes in this insulating barrier to appear the internal layer circuit that covers under the insulating barrier;
Form a conducting film at insulating barrier and blind hole surface;
On conducting film, form first resistance layer, and make first resistance layer be formed with a plurality of openings exposed portions serve conducting film in addition;
Carry out electroplating process and form conductive blind hole with the blind hole that formation figure line layer in the first resistance layer opening reaches at insulating barrier, this figure line layer comprises a plurality of electric connection pads, and has at least an electric connection pad to be electrically connected to conductive blind hole;
Form second resistance layer and cover electric connection pad figure line layer in addition, make electric connection pad expose outside second resistance layer;
Carry out electroplating process on electric connection pad, to form resistance barrier metal level; And
Remove second resistance layer, first resistance layer and cover conducting film under first resistance layer.
10. the method for making that the conductor package substrate construction of electric connection pad coat of metal is arranged as claimed in claim 9; it is characterized in that; the method for making of this conductor package substrate construction also is included in this substrate surface and forms and refuse layer, and makes and refuse layer and form a plurality of perforates to expose outside resistance barrier metal level.
11. the method for making that the conductor package substrate construction of electric connection pad coat of metal is arranged as claimed in claim 9 is characterized in that this insulating barrier is formed at the surface of multilayer circuit laminar substrate.
12. the method for making that the conductor package substrate construction of electric connection pad coat of metal is arranged as claimed in claim 9 is characterized in that, this base plate for packaging is in chip upside-down mounting type base plate for packaging and the routing type base plate for packaging.
13. the method for making that the conductor package substrate construction of electric connection pad coat of metal is arranged as claimed in claim 9 is characterized in that this electric connection pad is a convex pads.
14. the method for making that the conductor package substrate construction of electric connection pad coat of metal is arranged as claimed in claim 9 is characterized in that this electric connection pad is a solder ball pad.
15. the method for making that the conductor package substrate construction of electric connection pad coat of metal is arranged as claimed in claim 9 is characterized in that this electric connection pad is a wire pad.
16. the method for making that the conductor package substrate construction of electric connection pad coat of metal is arranged as claimed in claim 9; it is characterized in that the material of this resistance barrier metal level can be that gold, nickel, palladium, silver, tin, nickel/palladium, chromium/titanium, nickel/gold, palladium/gold and nickel/palladium/gold constitute a kind of in the group.
17. the method for making that the conductor package substrate construction of electric connection pad coat of metal is arranged as claimed in claim 9 is characterized in that, this first and second resistance layer can be a kind of in dry film and the liquid photoresistance.
18. the method for making that the conductor package substrate construction of electric connection pad coat of metal is arranged is characterized in that, the method for making of conductor package substrate construction comprises:
One insulating barrier is provided, and forms a plurality of blind holes in this insulating barrier to appear the internal layer circuit that covers under the insulating barrier;
Form a conducting film at insulating barrier and blind hole surface;
On conducting film, form a resistance layer, and this resistance layer there is a plurality of openings exposed portions serve conducting film in addition;
Carry out electroplating process and form conductive blind hole, and this electric connection pad is electrically connected to conductive blind hole with the blind hole that a plurality of electric connection pads of formation in this resistance layer opening reach at insulating barrier;
Carry out electroplating process on this electric connection pad, to form resistance barrier metal level; And
Remove this resistance layer and the conducting film that covers under the resistance layer.
19. the method for making that the conductor package substrate construction of electric connection pad coat of metal is arranged as claimed in claim 18; it is characterized in that; the method for making of conductor package substrate construction also is included in substrate surface and forms and to refuse layer, and makes and refuse layer and form a plurality of perforates and hinder metal level to expose outside this resistance.
20. the method for making that the conductor package substrate construction of electric connection pad coat of metal is arranged as claimed in claim 18 is characterized in that, this resistance layer opening corresponds to insulating barrier blind hole position.
21. the method for making that the conductor package substrate construction of electric connection pad coat of metal is arranged as claimed in claim 18 is characterized in that this insulating barrier is formed at the surface of multilayer circuit laminar substrate.
22. the method for making that the conductor package substrate construction of electric connection pad coat of metal is arranged as claimed in claim 18 is characterized in that, this base plate for packaging is in chip upside-down mounting type base plate for packaging and the routing type base plate for packaging.
23. the method for making that the conductor package substrate construction of electric connection pad coat of metal is arranged as claimed in claim 18 is characterized in that this electric connection pad is a convex pads.
24. the method for making that the conductor package substrate construction of electric connection pad coat of metal is arranged as claimed in claim 18 is characterized in that this electric connection pad is a solder ball pad.
25. the method for making that the conductor package substrate construction of electric connection pad coat of metal is arranged as claimed in claim 18 is characterized in that this electric connection pad is a wire pad.
26. the conductor package substrate construction method for making that the electric connection pad coat of metal is arranged as claimed in claim 18; it is characterized in that the material of this resistance barrier metal level can be gold, nickel, palladium, silver, tin, nickel/palladium, chromium/titanium, nickel/gold, palladium/gold and nickel/palladium/gold and constitutes a kind of in the group.
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| CNB031558194A CN100342526C (en) | 2003-08-22 | 2003-08-22 | Semiconductor sealing baseplate structure of electric padding metal protective layer and producing method thereof |
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