TWI764317B - Circuit board and method of fabricating the same - Google Patents

Abstract

A method of fabricating a circuit board includes forming a conductive layer on a surface of a substrate, and patterning the conductive layer to define a plurality of plating regions and a plurality of plating lines. The plating regions have at least two different sizes, and a first group of the plating regions are interconnected by a first plating line of the plating lines, and a second group of the plating regions are interconnected by a second plating line of the plating lines, in which a ratio of a total area of the first group of the plating regions to a total area of the second group of the plating regions is from about 1 to about 5. A solder mask is formed on the surface of the substrate, in which the solder mask covers the plating lines and partially exposes the plating regions. At least one metal layer is electroplated on the exposed plating regions, in which a topmost surface of the metal layer is below a top surface of the solder mask.

Description

Circuit board and method of making the same

The present disclosure relates to a circuit board and a manufacturing method thereof.

Electroplating technology has been widely used in various industrial applications. Taking circuit board technology (including printed circuit boards, IC substrates, etc.) as an example, circuit boards include substrates (such as core layers or multi-layer circuit boards, etc., but not limited to this) ) and a contact pad disposed on the surface of the substrate, wherein taking the core layer as an example, the core layer may include an insulating material layer, such as FR4 resin material and the like. A plurality of patterned conductive blocks can be disposed on the substrate, and contact pads can be formed on these conductive blocks by means of electroplating. Since the contact pads serve as the interface for signal or current connection between the circuit board and other components, if the contact pads have uneven plating thickness, undesired defects such as abnormal assembly or uneven loading will be caused. Therefore, the thickness uniformity of the electroplated metal layer has a critical influence on the quality of the product.

In some embodiments of the present disclosure, a method of manufacturing a circuit board includes forming a conductor layer on a surface of a substrate, patterning the conductor layer to define a plurality of electroplating blocks and a plurality of electroplating lines, wherein the electroplating blocks include at least two Different sizes, a first group of electroplating blocks is connected by a first electroplating line of electroplating lines, a second group of electroplating blocks is connected by a second electroplating line of electroplating lines, wherein the first group of electroplating blocks is The ratio of the total area to the total area of the second group of electroplating blocks is about 1 to 5. A solder resist layer is formed on the surface of the substrate, wherein the solder resist layer covers the plated lines and partially exposes the plated blocks. At least one metal layer is electroplated on the exposed electroplated blocks, wherein the topmost surface of the metal layer is lower than the top surface of the solder mask.

In some embodiments, the method further includes, after electroplating the metal layer on the exposed electroplating blocks, cutting off a first electroplating line at a location between adjacent ones of the first set of electroplating blocks, and in the electroplating area The second plating line is cut off at a position between two adjacent ones of the second group of blocks.

In some embodiments, the method further includes recessing at least one of the plated areas before electroplating the metal layer on the exposed plated areas.

In some embodiments, the first set of electroplating blocks are connected in series and the second set of electroplating blocks are connected in series

Some embodiments of the present disclosure provide a method of manufacturing a circuit board, including forming a conductor layer on a surface of a substrate; patterning the conductor layer to define a plurality of electroplating blocks and a electroplating line, wherein all the electroplating blocks are formed by the electroplating line connecting; forming a solder resist layer on the surface of the substrate, wherein the solder resist layer covers the plated lines and partially exposed plated blocks; and electroplating at least one metal layer on the exposed plated blocks, wherein the topmost surface of the metal layer is lower than the resist the top surface of the solder layer.

Some embodiments of the present disclosure provide a circuit board including a substrate, a plurality of contact pads disposed on a surface of the substrate, and a solder mask. The contact pad includes a plurality of electroplating blocks and metal layers disposed on the electroplating blocks, and the electroplating blocks include at least two different sizes. The solder mask covers the surface of the substrate and the edge of the electroplating block, wherein the topmost surface of the contact pad is lower than the top surface of the solder mask, and the distance between the topmost surface of the contact pad and the top surface of the solder mask is greater than 0 microns and less than 5 microns.

In some embodiments, the circuit board further includes electroplating line tails extending from the first electroplating block of the electroplating blocks and pointing to an adjacent second electroplating block.

In some embodiments, the plated line tails are connected to the first plated block but not to the second plated block.

In some embodiments, the circuit board further includes two electroplating line tails, respectively extending from two adjacent electroplating blocks and pointing toward each other.

In some embodiments, the metal layer is embedded in at least one of the electroplating blocks.

By properly arranging the layout of the electroplating blocks, the current density during electroplating can be made more uniform, thereby making the electroplating thickness more uniform. Therefore, the contact pads on the circuit board produced by this method can also have a uniform thickness.

The following will clearly illustrate the spirit of the present invention with drawings and detailed descriptions. After understanding the preferred embodiments of the present invention, anyone with ordinary knowledge in the technical field can make changes and modifications by the techniques taught in the present invention. without departing from the spirit and scope of the present invention.

The present disclosure provides a method for manufacturing a circuit board, wherein by appropriately configuring the layout of the electroplating blocks, the current density during the electroplating process can be more uniform, thereby making the thickness of the electroplating more uniform. Therefore, the circuit boards fabricated by this method also have uniform thicknesses on the contact pads.

FIGS. 1A to 7B illustrate different manufacturing stages of various embodiments of the circuit board manufacturing method according to the present disclosure, wherein FIGS. 1A, 2A, 3A, 4A, 5A, 6A, and 7A are top views, and FIG. 1B , 2B, 3B, 4B, 5B, 6B, and 7B are cross-sectional views along line A-A in Figures 1A to 7A. Referring to FIGS. 1A and 1B , a substrate 100 is provided, the substrate 100 includes a core layer 102 , and the core layer 102 may include a plurality of conductive vias therein for connecting lines on opposite surfaces of the core layer 102 . The core layer 102 may include a resin material, such as epoxy resin, polyimide resin, BT (bismaleimide triazine) resin, FR4 resin, or FR5 resin. In some embodiments, a metal foil layer 104 , such as a thin layer of copper or copper alloy, covers the surface of the core layer 102 .

Referring to FIGS. 2A and 2B , a pre-cleaning process is performed to clean the substrate 100 . For example, a pre-cleaning process may be performed to remove residues on the surface of the substrate 100, especially the metal foil layer 104, which may lead to increased resistance of the contact pads. In some embodiments, the pre-clean process is used to remove native oxides on the metal foil layer 104 . In some embodiments, the pre-clean process includes dry etching or wet etching. After the pre-cleaning process, the conductor layer 110 is blanket formed on the surface of the substrate 100 . For example, the conductor layer 110 is formed on the metal foil layer 104 of the substrate 100 , and the metal foil layer 104 can be regarded as a seed layer, so that the conductor layer 110 can be formed on the surface of the substrate 100 flatly. That is, the conductor layer 110 may have a uniform thickness to be conformally formed on the metal foil layer 104 of the substrate 100 . In some embodiments, the metal foil layer 104 fully covers the core layer 102 , and the conductor layer 110 fully covers the metal foil layer 104 .

Referring to FIGS. 3A and 3B , a patterning process is performed on the conductor layer 110 and the metal foil layer 104 thereunder to define a plurality of electroplating blocks 120 and a plurality of electroplating lines 130 . In some embodiments, the conductor layer 110 and the metal foil layer 104 below it further define at least one electroplating frame 190 and at least one fixture electrode 140 , and the plurality of electroplating lines 130 are connected to the electroplating frame 190 and then through the connecting lines 192 . Connect to the clamp electrode 140 . In some embodiments, the plating block 120 , the plating line 130 , the jig electrode 140 , the plating frame 190 and the connecting line 192 are the same material layer and are defined by the same etching process. During the electroplating process, the current provided by the fixture electrodes 140 is sent to the electroplating frame 190 through the connecting wires 192 , and then distributed to the electroplating blocks 120 through the electroplating wires 130 connected to the electroplating frame 190 .

Since the circuit board may include a plurality of contact pads with different functions, and these contact pads may have correspondingly different shapes and/or areas to meet the usage requirements. Therefore, the plated blocks 120 corresponding to the contact pads also have different shapes and/or areas.

For example, the plating block 120 includes a first plating block 120A having a larger area and a second plating block 120B having a smaller area. In some embodiments, the number of the first electroplating blocks 120A is plural, and the first electroplating blocks 120A are disposed in the central area of the substrate 100 . In some embodiments, the number of the second electroplating blocks 120B is plural, and the second electroplating blocks 120B are disposed in the peripheral area of the substrate 100 and surround the first electroplating blocks 120A. In some embodiments, the first electroplating block 120A having a larger area can be used as a terminal (gold finger) butt joint with a terminal (gold finger) of the socket, or as a solder pad at a soldering place. The second plating block 120B having a smaller area can be used as a test pad, a terminal or a solder pad.

The proportional relationship between the area of each of the first electroplating blocks 120A and the area of each of the second electroplating blocks 120B is determined according to usage requirements, and can be varied within a very wide range. For example, the ratio of the area of each first electroplating block 120A to the area of each second electroplating block 120B may be greater than 5. In some embodiments, the ratio of the area of each first electroplating block 120A to the area of each second electroplating block 120B may be greater than 20.

Since the ratio of the area of each first electroplating block 120A to the area of each second electroplating block 120B can be very large, if each first electroplating block 120A and each second electroplating block 120B are independently plated with When the frame 190 is connected, the current flowing through each first electroplating block 120A and the current flowing through each second electroplating block 120B are also different, resulting in uneven plating thickness in the subsequent electroplating process.

In order to solve the above problem, the electroplating line 130 of the present disclosure can be used to connect all the second electroplating blocks 120B, so that the total area of the connected second electroplating blocks 120B is similar to that of the first electroplating block 120A.

For example, the first electroplating block 120A has the largest area among all the electroplating blocks 120 , and each first electroplating block 120A is respectively connected to the electroplating frame 190 through the first electroplating line 130A. The second electroplating blocks 120B can be grouped (a group in the figure) and connected by second electroplating lines 130B, and these groups of second electroplating blocks 120B are connected to the electroplating frame in series through the second electroplating lines 130B 190. In some embodiments, the ratio of the area of each first electroplating block 120A to the total area of the group of second electroplating blocks 120B is about 1-5. In other embodiments, the ratio of the area of each first electroplating block 120A to the total area of the group of second electroplating blocks 120B is about 5-1.

By grouping the second plating blocks 120B with smaller areas and connecting them in series, the total area of these connected second plating blocks 120B will approximate the area of the first plating block 120A. Therefore, the plating area that each plating line 130 passes through will be more uniform, thereby making the voltage drop and current of the plating line 130 more uniform.

Refer to Figures 4A and 4B. The solder mask layer 150 is formed on the substrate 100 to control where the electroplating metal is deposited. The solder mask layer 150 can be fabricated by one or more yellow photolithography processes. The solder mask 150 includes an insulating material and has a sufficient thickness to define a plurality of openings 152 on the first electroplating block 120A and the second electroplating block 120B, wherein the thickness of the solder resist 150 is greater than the thickness of the electroplating block 120 .

In some embodiments, the solder mask layer 150 only covers the outer edges of the first electroplating block 120A and the second electroplating block 120B, and most areas of the first electroplating block 120A and the second electroplating block 120B are exposed to the Solder mask 150 . The exposed area of the first electroplating block 120A and the second electroplating block 120B is where the subsequent electroplating metal is deposited. Likewise, the solder resist layer 150 only covers the outer edge of the fixture electrode 140 , so that most of the area of the fixture electrode 140 is exposed to the solder resist layer 150 .

In some embodiments, the solder mask layer 150 covers areas of the core layer 102 that are not covered by the first plating block 120A, the second plating block 120B, and the fixture electrodes 140 . The plating line 130 , the plating frame 190 and the connecting line 192 are all covered by the solder resist layer 150 .

Referring to FIGS. 5A and 5B, one or more electroplating processes are performed to form one or more metal layers 160 on the exposed surfaces of the first electroplating block 120A and the second electroplating block 120B. For example, the clamp electrode 140 is connected to a power supply through the clamp such that a voltage is applied to the clamp electrode 140 . In this way, the clamp electrode 140 can be regarded as a voltage source when the substrate 100 is electroplated.

The first electroplating block 120A and the group of second electroplating blocks 120B are connected to the electroplating frame 190 through the corresponding electroplating lines 130, wherein the first electroplating blocks 120A are respectively connected to the electroplating frame 190 through the corresponding first electroplating lines 130A, The grouped second plating blocks 120B are connected to the plating frame 190 through the second plating lines 130B. The electroplating frame 190 is connected to the clamp electrode 140 through the connecting wire 192 , so that the electroplating frame 190 has substantially the same voltage level as the clamp electrode 140 .

As mentioned above, the second electroplating blocks 120B with smaller areas are connected by the second electroplating lines 130B, so that the total area of the connected second electroplating blocks 120B is similar to the area of the first electroplating block 120A , so the voltage drop and current flowing through each plating line 130 can be more uniform. Therefore, the one or more metal layers 160 formed on the first electroplating block 120A and the second electroplating block 120B can also have a relatively uniform thickness.

In some embodiments, the metal layer 160 includes a bottom metal layer 162 and a top metal layer 164, wherein the bottom metal layer 162 is located between the top metal layer 164 and the first electroplating block 120A and the second electroplating block 120B. The bottom metal layer 162 may include a metal with good adhesion, such as nickel (Ni), wherein the bottom metal layer 162 has barrier properties to prevent the material of the top metal layer 164 from penetrating into the core layer 102 . The top metal layer 164 may include a metal with higher hardness and is used to prevent oxidation of the bottom metal layer 162, and the top metal layer 164 may include, for example, an alloy of gold.

Referring to FIGS. 6A and 6B, a cutting process is performed to cut at least one plating line 130 after the metal layer 160 is plated on the first plating block 120A and the second plating block 120B. For example, the second plating line 130B for connecting the second plating block 120B is cut off after the metal layer 160 is plated on the first plating block 120A and the second plating block 120B. More specifically, the second electroplating lines 130B are cut off at positions between two adjacent second electroplating blocks 120B, so that the second electroplating blocks 120B are not directly connected to each other. In some embodiments, the first plating lines 130A used to respectively connect the first plating blocks 120A to the plating frame 190 are not cut off.

In some embodiments, the cutting process for cutting off the second electroplating line 130B may be a laser drilling process, and the laser light penetrates the solder mask 150 to cut off the second electroplating line 130B. Therefore, a plurality of through holes 154 are formed in the solder mask layer 150 , and a part of the core layer 102 of the substrate 100 is exposed to the through holes 154 .

Referring to FIGS. 7A and 7B, a severing process is performed to cut the substrate 100 and remove the portion of the substrate 100 including the jig electrodes 140 and the plating frame 190 (see FIG. 6A ) to obtain a circuit board 200, wherein the circuit board 200 It can be used as an IC carrier board or connected to a circuit board.

As shown in FIG. 7A , the first plating line 130A extends from the corresponding first plating block 120A and terminates at the edge of the circuit board 200 . One end of the second plating line 130B also terminates at the edge of the circuit board 200 . However, the second electroplating line 130B will be cut off after the metal layer 160 is electroplated. Therefore, a plurality of electroplating line tails 132 will exist on the circuit board 200 . Each electroplating line tail 132 extends from one of the second electroplating blocks 120B and points to the adjacent other second electroplating block 120B. Electroplating line tails 132 extending from adjacent pairs of second electroplating blocks 120B are aligned with each other. Each electroplating line tail section 132 is not directly connected to the adjacent electroplating line tail section 132, nor is it directly connected to another adjacent second electroplating block 120B.

As shown in FIG. 7B , the circuit board 200 includes a core layer 102 , an electroplating block 120 disposed on the surface of the core layer 102 , a metal layer 160 disposed on the electroplating block 120 , and an electroplating block 120 between the electroplating blocks 120 . Solder mask 150 . The stack composed of the metal foil layer 104 , the conductor layer 110 , and the metal layer 160 may be referred to as a contact pad 180 on the core layer 102 . Each contact pad 180 includes a lower portion 182 and an upper portion 184 , wherein the lower portion 182 includes the metal foil layer 104 and the conductor layer 110 , and the lower portion 182 is covered by the upper portion 184 and the solder mask layer 150 . The upper portion 184 contains the metal layer 160 and the upper portion 184 is exposed to the solder mask 150 . The width W1 of the lower portion 182 of the contact pad 180 is greater than the width W2 of the upper portion 184 of the contact pad 180 .

The solder mask layer 150 has a thickness T1 from the top surface of the core layer 102 to the top surface S2 of the solder mask layer 150 . The plated block 120 has a thickness T2 from the top surface of the core layer 102 to the top surface S3 of the lower portion 182 of the contact pad 180 . The contact pad 180 has a thickness T3 from the top surface of the core layer 102 to the topmost surface S1 of the contact pad 180 . The metal layer 160 has a thickness T4 from the top surface S3 of the lower portion 182 to the topmost surface S1 of the contact pad 180 .

In some embodiments, the topmost surface S1 of the contact pad 180 is lower than the top surface S2 of the solder mask 150 . The thickness T1 of the solder mask layer 150 is greater than the thickness T3 of the contact pad 180 , and the thickness T1 of the solder mask layer 150 is greater than the sum of the thickness T2 of the electroplating block 120 and the thickness T4 of the metal layer 160 . A gap G exists between the topmost surface S1 of the contact pad 180 and the top surface S2 of the solder mask 150 . In some embodiments, the distance G between the topmost surface S1 of the contact pad 180 and the top surface S2 of the solder mask 150 is greater than 0 micrometers and less than 5 micrometers, preferably greater than 0 micrometers and less than 2 micrometers.

In some embodiments, the metal layer 160 of the contact pad 180 includes an underlying metal layer 162 that contacts the corresponding electroplating block 120 . The underlying metal layer 162 is, for example, a nickel layer. The metal layer 160 of the contact pad 180 includes a top metal layer 164 disposed on the corresponding bottom metal layer 162. The top metal layer 164 is, for example, a layer containing gold alloy. The top metal layer 164 is used to provide sufficient hardness to protect the contact pads 180 from damage.

Although the embodiments in FIGS. 1A to 7B are described by taking the substrate 100 including the core layer 102 and the metal foil layer 104 and the conductor layer 110 disposed on the surface of the core layer 102 as an example, in other embodiments, the substrate It can include a multi-layer circuit board. At this time, the metal foil layer and the conductor layer, or the electroplating block obtained by patterning thereafter, are arranged on the surface of the multi-layer circuit board, and the present invention is not limited to this.

Referring to FIG. 8 and FIG. 9, which are respectively top views of different embodiments of the method for manufacturing a circuit board of the present disclosure, wherein the stages of FIG. 8 and FIG. 9 are the same as the aforementioned FIG. 3A and FIG. 3B, and This is followed by the steps of Figures 1A-2B followed by the execution of Figures 4A-7B.

As shown in FIG. 8, a substrate 300, such as a core layer or a multi-layer circuit board, is provided with a plurality of electroplating blocks 320, a plurality of electroplating lines 330, at least one electroplating frame 390, at least one clamp electrode 340, and at least one connection Line 392. The electroplating lines 330 are respectively connected to the electroplating frames 390 , and the electroplating frames 390 and the clamp electrodes 340 are connected through the connecting wires 392 . In this embodiment, the electroplating blocks 320 have various sizes and shapes, such as circles and various rectangles with different lengths. In this embodiment, the electroplating blocks 320 can be grouped in the manner described above, so that the areas of the grouped electroplating blocks 320 tend to be similar. For example, a part of the electroplating blocks 320, such as the electroplating blocks 320A, are connected in series by the electroplating lines 330A, and each electroplating block 320 in the group of the electroplating blocks 320A is different in shape and size. By analogy, a part of the electroplating blocks 320, such as the electroplating block 320B, are connected in series by the electroplating line 330B, a part of the electroplating blocks 320, such as the electroplating block 320C, are connected in series by the electroplating line 330C, and a part of the electroplating area Blocks 320, such as electroplating block 320D, are connected in series by electroplating lines 330D, while the remaining electroplating blocks 320, such as electroplating block 320E, are connected in series by electroplating lines 330E.

In the grouped electroplating block 320A, electroplating block 320B, electroplating block 320C, electroplating block 320D, and electroplating block 320E, their respective total areas are approximately similar. For example, among the groups of electroplating blocks 320 , the area ratio of the group with the largest total area and the group with the smallest total area can be designed to be no greater than five, so as to improve the uniformity of electroplating.

As shown in FIG. 9, a substrate 400, such as a core layer or a multi-layer circuit board, is provided with a plurality of electroplating blocks 420, a plurality of electroplating lines 430, at least one electroplating frame 490, at least one fixture electrode 440, and at least one connection Line 492. The configuration of the plating block 420 in this embodiment is substantially the same as that shown in FIG. 8 , but the paths of the plating lines 430 are different. For example, in this embodiment, the number of the plating lines 430 is changed to four, and the plating lines 430A, 430B, 430C, and 430D are respectively connected in series and in parallel to the plurality of plating blocks 420A, 420B, 420C, and 420D, so that each group of plating The total area ratio between the blocks 420 is not greater than 5.

Comparing Figure 8 and Figure 9, it can be seen that in practice, the path and quantity of the electroplating lines can be adjusted according to different wiring requirements, and the connection mode of the electroplating blocks can be connected in series or in series and in parallel. Improve process design flexibility.

Referring to FIGS. 10 and 11, which are top views of different embodiments of the method for manufacturing a circuit board of the present disclosure, respectively, wherein the stages of FIGS. 10 and 11 are the same as those of the aforementioned FIGS. 3A and 3B, and This is followed by the steps of Figures 1A-2B followed by the execution of Figures 4A-7B.

As shown in FIG. 10, a substrate 500, such as a core layer or a multi-layer circuit board, is provided with a plurality of electroplating blocks 520, a plurality of electroplating lines 530, at least one electroplating frame 590, at least one clamp electrode 540, and at least one connection Line 592. The plating blocks 520 are grouped and connected by corresponding plating lines 530 . For example, the plating line 530A is connected to the plating block 520A, and the plating block 520A may include at least two sizes and shapes. The plating line 530B is connected to the plating block 520B, and the plating block 520B may include at least two sizes and shapes. The plating line 530C is connected to the plating block 520C, and the plating block 520C may include at least two sizes and shapes. The electroplating lines 530A, 530B and 530C are connected to the electroplating frame 590 , and the electroplating frame 590 is connected to the clamp electrode 540 through the connecting wire 592 . The total areas of the grouped electroplating blocks 520A, 520B, and 520C are approximately similar.

For example, among the three sets of electroplating blocks 520A, 520B, 520C, the set of electroplating blocks 520B has the largest total area, and the set of electroplating blocks 520A/520C has a smaller total area. The ratio of the total area of the grouped electroplating blocks 520B to the total area of the grouped electroplating blocks 520A/520C is not greater than 5.

As shown in FIG. 11, a substrate 600, such as a core layer or a multi-layer circuit board, is provided with a plurality of electroplating blocks 620, electroplating lines 630, at least one electroplating frame 690, at least one clamp electrode 640, and at least one connecting line 692 . In some embodiments, all the electroplating blocks 620 are connected through a single electroplating line 630, wherein the electroplating blocks 620 include at least two sizes and shapes. The shapes of the electroplating blocks 620 are not limited to rectangles and circles, but Combinations such as triangles or other polygons can appear.

Referring to FIGS. 12 and 13, which are respectively cross-sectional views of another embodiment of the method for manufacturing a circuit board of the present disclosure, wherein the steps of FIGS. 1A-4B are followed, and the steps of FIGS. 6A-7B are subsequently performed. .

As shown in FIG. 12, in some embodiments, the area of the plating block 720B on the substrate 700, such as the core layer 702, is smaller than the area of the plating block 720A. The method further includes forming a patterned mask 770 on the substrate 700 to expose the electroplating block 720B with a smaller area and allow the electroplating block 720A with a larger area to be covered by the patterned mask 770 . In some embodiments, electroplating blocks 720A, 720B may be further connected to electroplating frame 790 by electroplating lines 730 .

Next, an etching process is performed to recess the plated block 720B. The recessed plated block 720B still covers the core layer 702 below it. That is, each recessed plated block 720B has a central portion 722 and a peripheral portion 724, wherein the central portion 722 is exposed to the solder mask 750 and the patterned mask 770, and the peripheral portion 724 is exposed to the solder mask 750 and the patterned mask 770. Mask 770 covers. The thickness of the peripheral portion 724 is greater than the thickness of the central portion 722 . Each electroplating block 720 includes a metal foil layer 702 and a conductor layer 704 , wherein the conductor layer 704 is recessed and the metal foil layer 702 is still covered by the conductor layer 704 .

As shown in FIG. 13 , the patterned mask 770 is removed, and an electroplating process is performed to deposit a metal layer 760 on the exposed surface of the electroplated block 720 . The thickness H2 of the metal layer 760 deposited on the plated block 720B with the smaller area is greater than the thickness H1 of the metal layer 760 deposited on the plated block 720A with the larger area. In some embodiments, the metal layer 760 is embedded in the plated block 720B, and the interface between the metal layer 760 and the plated block 720B is lower than the interface between the solder mask 750 and the plated block 720B.

The present disclosure provides a method for manufacturing a circuit board. By properly arranging the layout of the electroplating blocks, the current density during electroplating can be made more uniform, thereby making the electroplating thickness more uniform. Therefore, the contact pads on the circuit board produced by this method can also have a uniform thickness.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Anyone skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention The scope shall be determined by the scope of the appended patent application.

100,300,400,500,600,700: Substrate 102,702: Core Layer 104,704: Metal foil layer 110,710: Conductor layer 120, 320, 320A, 320B, 320C, 320D, 320E, 420, 420A, 420B, 420C, 420D, 520, 520A, 520B, 520C, 620, 720A, 720B: Electroplating Blocks 120A: The first electroplating block 120B: Second electroplating block 130, 330, 330A, 330B, 330C, 330D, 330E, 430, 430A, 430B, 430C, 430D, 530, 520A, 520B, 520C, 630, 730: Electroplating wire 132: Electroplating line tail 130A: The first plating line 130B: Second Electroplating Line 140, 340, 440, 540, 640: Clamp electrodes 150,750: Solder mask 152: Opening 154: Perforation 160,760: Metal Layer 162: Bottom metal layer 164: top metal layer 180: Contact pad 182: Lower part 184: Upper part 190,390,490,590,690,790: Electroplating frame 192,392,492,592,692: Connecting wires 200: circuit board 722: Center Section 724: Peripheral part 770: Patterned Mask A-A: line segment W1,W2: width T1,T2,T3,T4: Thickness S1: Topmost surface S2, S3: Top surface G: Spacing H1,H2: Thickness

In order to make the above and other objects, features, advantages and embodiments of the present invention more clearly understood, the detailed description of the accompanying drawings is as follows: FIGS. 1A-7B illustrate different manufacturing stages of various embodiments of the circuit board manufacturing method according to the present disclosure. FIGS. 8 to 11 are top views of different embodiments of the method for manufacturing a circuit board of the present disclosure, respectively. FIG. 12 and FIG. 13 are respectively cross-sectional views of another embodiment of the method for manufacturing a circuit board of the present disclosure.

Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none

100: Substrate 102: Core Layer 120: Electroplating block 120A: The first electroplating block 120B: Second electroplating block 130: Electroplating line 130A: The first plating line 130B: Second Electroplating Line 140: Fixture electrode 190: Electroplating frame 192: connecting line A-A: line segment

Claims (10)

A method of manufacturing a circuit board, comprising: forming a conductor layer on a surface of a substrate; The conductor layer is patterned to define a plurality of electroplating blocks and a plurality of electroplating lines, wherein the electroplating blocks include at least two different sizes, and a first group of the electroplating blocks is composed of a plurality of electroplating lines. A first plating line is connected, a second group of the plating blocks is connected by a second plating line of the plating lines, wherein the total area of the first group of the plating blocks and the plating areas The proportion of the total area of this second group of blocks is about 1 to 5; forming a solder mask on the surface of the substrate, wherein the solder mask covers the electroplating lines and partially exposes the electroplating blocks; and Electroplating at least one metal layer on the exposed plated blocks, wherein the topmost surface of the metal layer is lower than the top surface of the solder mask. The method of claim 1, further comprising, after electroplating the metal layer on the exposed electroplating blocks, cutting the metal layer at a position between two adjacent ones of the first group of the electroplating blocks a first electroplating line, and cutting the second electroplating line at a position between two adjacent ones of the second group of the electroplating blocks. The method of claim 1, further comprising recessing at least one of the plated areas before electroplating the metal layer on the exposed plated areas. The method of claim 1, wherein the first group of the electroplating blocks are connected in series and the second group of the electroplating blocks are connected in series. A method of manufacturing a circuit board, comprising: forming a conductor layer on a surface of a substrate; patterning the conductor layer to define a plurality of electroplating blocks and a electroplating line, wherein all the electroplating blocks are connected by the electroplating line; forming a solder mask on the surface of the substrate, wherein the solder mask covers the plated lines and partially exposes the plated blocks; and Electroplating at least one metal layer on the exposed plated blocks, wherein the topmost surface of the metal layer is lower than the top surface of the solder mask. A circuit board containing: a substrate; A plurality of contact pads are disposed on a surface of the substrate, wherein the contact pads include a plurality of electroplating blocks and a metal layer disposed on the electroplating blocks, and the electroplating blocks include at least two different size; and a solder mask covering the surface of the substrate and the edges of the electroplating blocks, wherein the topmost surfaces of the contact pads are lower than the top surface of the solder mask, and the topmost surfaces of the contact pads are the same as the The spacing between the top surfaces of the solder mask is greater than 0 microns and less than 5 microns. The circuit board of claim 6, further comprising an electroplating line tail extending from a first electroplating block among the electroplating blocks and pointing to an adjacent second electroplating block. The circuit board of claim 7, wherein the plating line tail is connected to the first plating block but not to the second plating block. The circuit board of claim 6, further comprising two electroplating line tails extending from adjacent two of the electroplating blocks and pointing toward each other. The circuit board of claim 6, wherein the metal layer is embedded in at least one of the electroplating blocks.

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