TW201625094A - Circuit board and method of manufacturing the same - Google Patents

Abstract

A circuit board and a manufacturing method thereof are provided. The circuit board includes a dielectric core, a passive device, a first circuit pattern, a second circuit pattern, a first conductive via and a second conductive via. The passive device has a main body, a first electrode and a second electrode. The first and second electrodes are disposed on two opposed sides of the main body, respectively. The first and the second electrodes have a first end and a second end opposite to each other, respectively. The second end of the first electrode and the second end of the second electrode are disposed in the dielectric core layer. The first end of the first electrode and the first end of the second electrode are protruded from the dielectric core. The first and second circuit patterns are disposed on the opposed surfaces of the dielectric core layer, respectively. The first conductive via is disposed in the dielectric core layer and is connected with the first circuit pattern and the second end of the first electrode and the second end of the second electrode. The second via is disposed in the dielectric core layer and is connected with the first circuit pattern and the second circuit pattern.

Description

Circuit board and manufacturing method thereof

The present invention relates to a circuit board and a method of fabricating the same, and more particularly to a circuit board having a buried component and a method of fabricating the same.

In recent years, with the rapid development of electronic technology, more humanized technology products have been introduced, and these technology products are designed to be light, thin, short and small. In order to reduce the area of the electronic components disposed on the circuit board or to meet other needs, a circuit board having embedded components may be disposed in the electronic products.

In the conventional circuit board process with embedded electronic components, through holes are usually formed in the core board. Next, one end of the through hole is closed with a tape to form a recess for accommodating the electronic component. The electronic component is then placed in the recess and the electronic component is secured in the recess by tape. Thereafter, the dielectric material and the conductive layer are laminated. During the lamination process, the dielectric material fills into the recess in which the electronic component is housed.

However, since the above-mentioned groove needs to accommodate the entire electronic component, the thickness of the core plate is necessarily limited and cannot be continuously thinned. In addition, since the groove needs to have a certain depth in accordance with the size of the electronic component, it is easy to cause a dielectric material. The problem of not being able to fill the grooves during the press-fitting process creates voids.

The invention provides a method for manufacturing a circuit board, which can produce a circuit board having a thin thickness.

The present invention provides a wiring board having a relatively thin thickness.

The invention provides a method for manufacturing a circuit board, comprising the following steps: First, a carrier board is provided, the carrier board comprising a dielectric substrate and a first conductive layer on the dielectric substrate. Next, a pattern layer is formed on the first conductive layer, the pattern layer having a recess exposing a portion of the first conductive layer. Then, the passive component is fixed in the recess by the adhesive material, wherein the passive component has a main body and first and second electrodes respectively disposed on opposite sides of the main body, the first electrode and the second electrode respectively having each other The first end and the second end of the first electrode, the first end of the first electrode and the first end of the second electrode are located in the groove, and the second end of the first electrode and the second end of the second electrode protrude In the groove. Thereafter, a dielectric layer is formed on the pattern layer. Next, the carrier plate and the first conductive layer are separated. Then, the first conductive layer is removed. Then, at least a portion of the adhesive material is removed to expose at least the first end of the first electrode and the first end of the second electrode. In addition, a blind via and a via are formed in the dielectric layer, and the blind via exposes the second end of the first electrode and the second end of the second electrode. Finally, a first line pattern and a second line pattern are formed on opposite surfaces of the dielectric layer, and a first via hole and a second via hole are respectively formed in the blind via and the via hole, wherein the first line pattern is formed by The first via hole is electrically connected to the second end of the first electrode and the second end of the second electrode And the second line pattern is electrically connected to the first line pattern by the second via hole.

According to the manufacturing method of the circuit board according to the embodiment of the invention, the method for removing at least part of the adhesive material is, for example, performing a wet etching process to remove the entire adhesive material.

According to the manufacturing method of the circuit board according to the embodiment of the invention, the method of removing at least part of the adhesive material is, for example, performing a laser etching process to remove all or part of the adhesive material.

According to the method of fabricating a circuit board according to the embodiment of the invention, the method for forming the pattern layer comprises: first, forming a mask layer on the first conductive layer. Next, a mask layer is used as a mask to form a material layer on the first conductive layer. Then remove the mask layer.

According to the manufacturing method of the circuit board according to the embodiment of the invention, the material layer is, for example, a metal layer, and the method of forming a material layer on the first conductive layer is, for example, performing an electroplating process.

According to the method of fabricating a circuit board according to an embodiment of the invention, the metal layer is, for example, the same material as the first conductive layer.

According to the manufacturing method of the circuit board of the embodiment of the invention, the carrier board further includes a second conductive layer and a separation layer, wherein the second conductive layer is located between the dielectric substrate and the first conductive layer, and the separation layer is located at the first The first conductive layer and the separation layer are separated between the conductive layer and the second conductive layer, and during the process of separating the carrier and the first conductive layer.

According to the manufacturing method of the circuit board according to the embodiment of the invention, the passive component is, for example, a multilayer ceramic capacitor (MLCC).

The invention provides a circuit board comprising a dielectric core layer, a passive component, a first line pattern, a second line pattern, a first via, and a second via. The passive component has a body and first and second electrodes respectively disposed on opposite sides of the body, wherein the first electrode and the second electrode each have a first end and a second end opposite to each other, the first electrode The second ends of the second ends and the second electrodes are disposed in the dielectric core layer, and the first ends of the first electrodes and the first ends of the second electrodes protrude from the dielectric core layer. The first line pattern and the second line pattern are respectively disposed on opposite surfaces of the dielectric core layer. The first via is disposed in the dielectric core layer and connects the first line pattern with the second end of the first electrode and the second end of the second electrode. The second via hole is disposed in the dielectric core layer and connects the first line pattern and the second line pattern.

According to the circuit board of the embodiment of the invention, the circuit board further includes an adhesive layer disposed on the dielectric substrate and exposing at least the first end of the first electrode and the first end of the second electrode.

According to the wiring board of the embodiment of the invention, the passive component is, for example, a multilayer ceramic capacitor.

Based on the above, the invention firstly fixes a part of the passive original in the groove with the adhesive material, and then presses the dielectric layer of the dielectric core layer to cover the remaining part of the passive original, so that the dielectric layer can be tightly coated. The passive component does not have a gap between the passive component and the dielectric layer. In addition, since the passive component is partially buried in the dielectric core layer and the entire passive component is buried in the dielectric core layer, the thickness of the wiring board can be effectively reduced. In addition, the exposed electrode of the partially buried passive component structure can be directly connected to other electronic components as a pad.

In order to make the above features and advantages of the present invention more apparent, the following is a special The embodiments are described in detail below in conjunction with the drawings.

10, 20‧‧‧ circuit board

15b, 15c‧‧‧ first end

25b, 25c‧‧‧ second end

100‧‧‧ carrying board

101a, 101b‧‧ ‧ cover layer

102‧‧‧ dielectric substrate

102a, 102b, 122, 132‧‧‧ surface

112a, 112b‧‧‧ dielectric layer

103a, 103b‧‧‧ material layer

104a, 104b, 108a, 108b‧‧‧ conductive layer

105a, 105b‧‧‧ pattern layer

106a, 106b‧‧‧ separation layer

107a, 107b‧‧‧ Groove

109‧‧‧Adhesive materials

200a, 200b‧‧‧ structure

110‧‧‧ Passive components

110a‧‧‧ Subject

110b, 110c‧‧‧ electrodes

113a, 113b‧‧‧ openings

114a, 114b‧‧‧ solder mask

115‧‧‧through hole

116‧‧‧ solder balls

117‧‧‧Blind hole

124, 134‧‧‧ line pattern

125, 127‧‧ ‧ guide hole

1A to 1K are schematic cross-sectional views showing a manufacturing process of a circuit board according to a first embodiment of the present invention.

2A-2C are schematic cross-sectional views showing a manufacturing process of a circuit board according to a second embodiment of the present invention.

1A to 1K are schematic cross-sectional views showing a manufacturing process of a circuit board according to a first embodiment of the present invention. First, the carrier board 100 is provided. In the present embodiment, the carrier board 100 includes a dielectric substrate 102, conductive layers 104a and 104b, separation layers 106a and 106b, and conductive layers 108a and 108b. However, the present invention is not limited thereto. In other embodiments, the carrier board may include only the dielectric substrate and the conductive layers disposed on the upper and lower sides thereof, or may be other carrier boards commonly used in the art. The manner in which the carrier board 100 of the present embodiment is fabricated will be described in detail below.

Referring to FIG. 1A, conductive layers 104a, 104b are formed on the opposite surfaces 102a and 102b of the dielectric substrate 102, respectively. The material of the dielectric substrate 102 is, for example, an epoxy resin, but is not limited thereto. The conductive layers 104a, 104b are, for example, copper layers. The conductive layers 104a, 104b are formed on the dielectric substrate 102, for example, by press bonding. Separate layers 106a, 106b are then formed on the conductive layers 104a, 104b, respectively. Separation The material of the layers 106a, 106b is, for example, an organic-inorganic low-adhesive composite. Next, conductive layers 108a, 108b are formed on the separation layers 106a, 106b, respectively, by plating or press bonding. The conductive layers 108a, 108b are, for example, copper layers. In particular, the separation layers 106a, 106b have low adhesion, and the conductive layer 104a and the conductive layer 108a and the adhesion conductive layer 104b and the conductive layer 108b may be adhered, respectively.

Next, referring to FIG. 1B, mask layers 101a, 101b are formed on the conductive layers 108a, 108b, respectively. The mask layers 101a, 101b are used to define the locations at which the grooves are to be subsequently formed. In the present embodiment, the mask layers 101a, 101b may be formed on the conductive layers 108a, 108b, respectively, using lithographic exposure. Then, with the mask layers 101a, 101b as masks, material layers 103a, 103b are formed on the conductive layers 108a, 108b, respectively. The material layers 103a, 103b may be metal layers, and this metal layer may be the same material as the conductive layers 108a, 108b. In the present embodiment, the method of forming the material layers 103a, 103b on the conductive layers 108a, 108b is, for example, an electroplating process.

Thereafter, referring to FIG. 1C, the mask layers 101a, 101b are removed to form the pattern layers 105a, 105b, respectively. The pattern layer 105a has a groove 107a exposing a portion of the conductive layer 108a, and the pattern layer 105b has a groove 107b exposing a portion of the conductive layer 108b. In the present embodiment, the positions, the numbers, and the sizes of the grooves 107a, 107b are the same, but the present invention is not limited thereto, and the position, the number, and the size of the grooves can be changed as needed.

Then, referring to FIG. 1D, the adhesive material 109 is filled in the grooves 107a and 107b. The adhesive material 109 is, for example, an organic-inorganic composite thermosetting material. Next, the passive component 110 is placed in the recesses 107a, 107b, and the passive component 110 is secured in the recesses 107a, 107b by the adhesive material 109. In this embodiment, the passive component 110 is, for example, a multilayer ceramic capacitor having a body 110a and electrodes 110b, 110c respectively disposed on opposite sides of the body 110a, wherein the electrode 110b has a first end 15b and a second end 25b opposite to each other, and the electrodes 110c have each other The opposite first end 15c and second end 25c. The detailed structure of the passive component 110 is well known to those skilled in the art and will not be described herein. Importantly, the passive component 110 is not entirely disposed in the recesses 107a, 107b. In this embodiment, the first end 15b of the electrode 110b, the first end 15c of the electrode 110c, and a portion of the main body 110a are disposed in the grooves 107a, 107b, and the second end 25b of the electrode 110b and the second end of the electrode 110c 25c and the remaining body 110a protrude from the grooves 107a, 107b. In other embodiments, the view element may be designed such that only the first end 15b of the electrode 110b and the first end 15c of the electrode 110c are placed in the grooves 107a, 107b. In addition, portions of the passive component 110 at the bottom of the recesses 107a, 107b do not contact the conductive layers 108a, 108b, i.e., the adhesive material 109 covers portions of the passive component 110 at the bottom of the recesses 107a, 107b to avoid subsequent removal of conductive Passive element 110 is damaged when layers 108a, 108b. In addition, in the present embodiment, the passive elements 110 fixed in the grooves 107a, 107b are the same passive elements, but the invention is not limited thereto, and the passive elements in the grooves 107a, 107b may also be different passive elements or It may be that the recess 107a may be a passive component and the recess 107b is an active component, or the recess 107a may be an active component and the recess 107b may be a passive component.

Then, referring to FIG. 1E, dielectric layers 112a, 112b are formed on the pattern layers 105a, 105b, respectively. In the present embodiment, the dielectric layers 112a, 112b cover portions of the passive component 110 that protrude from the recesses 107a, 107b (i.e., the second end of the electrode 110b) 25b, the second end 25c of the electrode 110c and a portion of the body 110a). The material of the dielectric layers 112a, 112b is, for example, an ABF film (Ajinomoto build-up film) or a semi-cured resin. In the present embodiment, the conductive layers 114a and 114b and the dielectric layers 112a and 112b are formed on the pattern layers 105a and 105b by press bonding. The dielectric layers 112a, 112b are the dielectric core layers in the circuit board to be formed by the present invention, and the passive components 110 are partially buried in the dielectric core layer.

Thereafter, referring to FIG. 1F, a separation process is performed to separate the conductive layers 108a, 108b from the dielectric substrate 102 to form two structures 200a and 200b in which the passive elements 110 are buried. In the present embodiment, the structures 200a and 200b have the same composition. Since the separation layer 106a is located between the conductive layer 108a and the conductive layer 104a, and the separation layer 106b is located between the conductive layer 108b and the conductive layer 104b, the conductive layer 108a can be easily separated from the separation layers 106a, 106b in the separation process. The conductive layer 104a is separated.

The following process will be described by taking the structure 200a as an example. Referring to FIG. 1G, the structure 200a is subjected to a wet etching process to remove the conductive layers 108a, 114a and the pattern layer 105a in the structure 200a. Since the adhesive material 109 covers the first end 15b of the electrode 110b protruding from the dielectric layer 112a, the first end 15c of the electrode 110c, and a portion of the body 110a, the passive element 110 can be prevented from being damaged during the wet etching process described above.

Next, referring to FIG. 1H, the entire adhesive material 109 is removed to expose the first end 15b of the electrode 110b and the first end 15c of the electrode 110c. In the present embodiment, the method of removing the adhesive material 109 is, for example, a wet etching process.

As can be seen from FIG. 1H, in the present example, the dielectric layer 112a is pressed. In the structure in which the passive component 110 is fixed, the dielectric layer 112a serving as the dielectric core layer in the wiring board can tightly cover the passive component 110 without voids in the passive component 110 and the dielectric layer 112a. between.

Then, referring to FIG. 1I, a blind via 117 and a via 115 are formed in the dielectric layer 112a, wherein the blind via 117 exposes the second end 25b of the electrode 110b and the second end 25c of the electrode 110c. The method of forming the blind holes 117 and the through holes 115 is, for example, laser drilling. In the present embodiment, laser drilling is performed on the surface 132 of the dielectric layer 112a to form the via 115. However, the present invention is not limited thereto, and may be performed from the surface 122 of the dielectric layer 112a in other embodiments. The laser is drilled to form a through hole 115.

Thereafter, referring to FIG. 1J, via holes 127, 125 are formed in the blind vias 117 and the vias 115, respectively. The method of forming the via holes 127, 125 is, for example, performing an electroplating process, or filling a conductive material (for example, a conductive paste) into the blind vias 117 and the via holes 115. Then, line patterns 124, 134 are formed on the surface 122 and the surface 132 of the dielectric layer 112a, respectively. The manner in which the line patterns 124, 134 are formed is well known to those skilled in the art and will not be described herein. The circuit pattern 124 is electrically connected to the second end 25b of the electrode 110b and the second end 25c of the electrode 110c via the via 127, and the line pattern 134 is electrically connected to the line pattern 124 via the via 125. In this way, the fabrication of the circuit board 10 having the partially buried passive component can be completed.

In particular, in the present embodiment, the difference between the thickness of the line pattern 134 and the thickness of the first end 15b of the electrode 110b and the first end 15c of the electrode 110c protruding from the surface 132 of the dielectric layer 112a falls within 3 μm. Within the scope. That is, the thickness of the line pattern 134 may be greater than the first end 15b of the electrode 110b and the electrode 110c The first end 15c protrudes from the thickness of the surface 132 of the dielectric layer 112a, and may also be smaller than the thickness of the first end 15b of the electrode 110b and the first end 15c of the electrode 110c protruding from the surface 132 of the dielectric layer 112a, as long as the two The difference between them is no more than 3μm. In this way, it is ensured that the line pattern of the wiring board 10 has a uniform line thickness.

In addition, since the circuit board 10 can be used as a pad by the first end 15b of the electrode 110b protruding from the surface 132 of the dielectric layer 112a and the first end 15c of the electrode 110c, the circuit board 10 does not need to form an additional connection. Pad to connect other electronic components.

In the present embodiment, after the circuit board 10 is formed, the subsequent process of the circuit board 10 can be further performed. Referring to FIG. 1K, a solder resist layer 114a is formed on the surface 122 of the dielectric layer 112a, and a solder resist layer 114b is formed on the surface 132 of the dielectric layer 112a. The material of the solder resist layers 114a, 114b is, for example, a commonly known green lacquer. The method of forming the solder resist layers 114a, 114b is, for example, an ink-jet printing method or a general conventional image transfer method. The solder resist layer 114a covers a portion of the wiring pattern 124, and the solder resist layer 114a has an opening 113a exposing a portion of the wiring pattern 124. The line pattern 124 exposed by the solder resist layer 114a can serve as a pad for connection to external components. The solder resist layer 114b covers a portion of the wiring pattern 134, and the solder resist layer 114b has an opening 113b exposing a portion of the wiring pattern 134 and the partial electrodes 110b, 110c. Then, solder balls 116 are formed in the openings 113b, and the solder balls 116 are connected to the wiring patterns 134 and the electrodes 110b and 110c. The material of the solder ball is, for example, tin. In this way, the passive component 110 can be electrically connected to other electronic components through the solder ball 116.

In the present embodiment, the circuit board 10 is a circuit board structure having two layers of line patterns. Of course, in other embodiments, before the solder resist layers 114a, 114b are formed. The layering process can be performed according to actual needs to produce a line pattern having a desired number of layers. The above-described build-up process is well known to those skilled in the art and will not be described herein. Further, in the present embodiment, since the passive element 110 is partially buried in the dielectric layer 112a, and not the entire passive element 110 is buried in the dielectric layer 112a, the thickness of the wiring board 10 can be effectively reduced.

2A-2C are schematic cross-sectional views showing a manufacturing process of a circuit board according to a second embodiment of the present invention. It should be noted here that the following embodiment follows the partial fabrication process of the foregoing embodiment and performs subsequent processes for the structure 200a of FIG. 1F. Therefore, the following embodiments will be used to refer to the same or similar elements in the above-mentioned embodiments, and the same reference numerals are used to denote the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

The manufacturing process of the circuit board 20 of this embodiment can be performed in substantially the same manner as the manufacturing process of the circuit board 10 of the foregoing embodiment. After FIG. 1F, the structure 200a is subjected to a wet etching process to place the structure 200a. The conductive layers 108a, 114a are removed from the pattern layer 105a. Next, as shown in FIG. 2A, a portion of the adhesive material 109 is removed to the first end 15b of the electrode 110b and the first end 15c of the electrode 110c. A method of removing a portion of the adhesive material 109 is, for example, a laser etching process. In this embodiment, during the laser etching process, laser drilling may be simultaneously performed to form the blind vias 117 and the vias 115 in the dielectric layer 112a. In this embodiment, after the laser etching process, a portion of the adhesive material 109 that is not removed is also attached to the passive component 110. In other embodiments, the laser etch process can also completely remove the passive component 110. All of the adhesive material 109 is formed to form a structure as shown in FIG.

Then, as shown in FIG. 2B, via holes 127, 125 are formed in the blind vias 117 and the vias 115, respectively, and line patterns 124, 134 are formed on the opposite surfaces 122 and 132 of the dielectric layer 112a, respectively. The circuit pattern 124 is electrically connected to the electrodes 110b and 110c of the passive component 110 via the via 127, and the wiring pattern 134 is electrically connected to the wiring pattern 124 via the via 125. In this way, the fabrication of the circuit board 20 of the partially buried passive component can be completed. Thereafter, the circuit board 20 can be subsequently processed. Referring to FIG. 2C, a solder resist layer 114a is formed on the surface 122 of the dielectric layer 112a, and the solder resist layer 114a has an opening 113a exposing a portion of the wiring pattern 124, and a solder resist layer is formed on the surface 132 of the dielectric layer 112a. 114b, and the solder resist layer 114b has an opening 113b exposing a portion of the wiring pattern 134 and the partial electrodes 110b, 110c. Then, solder balls 116 are formed in the openings 113b, and the solder balls 116 are connected to the wiring patterns 134 and the electrodes 110b and 110c. In this way, the passive component 110 can be electrically connected to other electronic components through the solder ball 116.

In the first embodiment and the second embodiment described above, the surface 102a and the surface 102b of the dielectric substrate 102 are subjected to the above-described process steps, but the invention is not limited thereto. In other embodiments, the process steps described above may also be performed only on surface 102a or only on surface 102b.

In summary, the present invention first fixes a part of the passive component in the recess by the adhesive material, and then presses the dielectric layer into the dielectric core layer, so that the dielectric layer can tightly cover the passive component without A gap is created between the passive component and the dielectric layer.

In addition, since the passive component is partially buried in the dielectric core layer and the entire passive component is buried in the dielectric core layer, the wiring board can be effectively thinned.

Further, in the wiring board of the present invention, the electrode of the partially buried passive component can be used as a pad to be connected to other electronic components.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧ circuit board

15b, 15c‧‧‧ first end

25b, 25c‧‧‧ second end

112a‧‧‧ dielectric layer

110‧‧‧ Passive components

110a‧‧‧ Subject

110b, 110c‧‧‧ electrodes

122, 132‧‧‧ surface

124, 134‧‧‧ line pattern

125, 127‧‧ ‧ guide hole

Claims (10)

A method for fabricating a circuit board, comprising: providing a carrier board, the carrier board comprising a dielectric substrate and a first conductive layer on the dielectric substrate; forming a pattern layer on the first conductive layer, the pattern The layer has a recess exposing a portion of the first conductive layer; the passive component is fixed in the recess by an adhesive material, wherein the passive component has a body and a first surface disposed on opposite sides of the body An electrode and a second electrode, each of the first electrode and the second electrode having a first end and a second end opposite to each other, a first end of the first electrode and a first end of the second electrode An end is located in the recess, and a second end of the first electrode and a second end of the second electrode protrude from the recess; a dielectric layer is formed on the pattern layer; a plate and the first conductive layer; removing the first conductive layer; removing at least a portion of the adhesive material to expose a first end of the first electrode and a first end of the second electrode; Forming a blind hole and a through hole in the dielectric layer, the blind Exposing a second end of the first electrode and a second end of the second electrode; and forming a first line pattern and a second line pattern on opposite surfaces of the dielectric layer, respectively Forming a first via hole and a second via hole in the via hole and the through hole, wherein the first line pattern is formed by the first via hole and the first electrode The second end and the second end of the second electrode are electrically connected, and the second line pattern is electrically connected to the first line pattern by the second guiding hole. The method of fabricating a circuit board according to claim 1, wherein the method of removing at least a portion of the adhesive material comprises performing a wet etching process to remove the entire adhesive material. The method of fabricating a circuit board according to claim 1, wherein the method of removing at least a portion of the adhesive material comprises performing a laser etching process to remove all or part of the adhesive material. The method for fabricating a circuit board according to claim 1, wherein the method for forming the pattern layer comprises: forming a mask layer on the first conductive layer; and using the mask layer as a mask, Forming a material layer on the first conductive layer; and removing the mask layer. The method of fabricating a circuit board according to claim 4, wherein the material layer is a metal layer, and the method of forming the material layer on the first conductive layer comprises performing an electroplating process. The method of fabricating a circuit board according to claim 5, wherein the metal layer is the same material as the first conductive layer. The manufacturing method of the circuit board of claim 1, wherein the carrier board further comprises a second conductive layer and a separation layer, wherein the second conductive layer is located on the dielectric substrate and the first conductive layer Between the layers, the separation layer is located at the first conductive The first conductive layer is separated from the separation layer between the layer and the second conductive layer, and during the separation of the carrier plate from the first conductive layer. A circuit board comprising: a dielectric core layer; a passive component having a body and first and second electrodes respectively disposed on opposite sides of the body, wherein the first electrode and the second electrode Each of the first end and the second end opposite to each other, the second end of the first electrode and the second end of the second electrode are disposed in the dielectric core layer, and the first electrode a first end of the second electrode protrudes from the dielectric core layer; a first line pattern and a second line pattern are respectively disposed on opposite surfaces of the dielectric core layer; the first via hole Disposed in the dielectric core layer and connecting the first line pattern with the second end of the first electrode and the second end of the second electrode; and a second via hole disposed in the dielectric layer And connecting the first line pattern and the second line pattern in the electric core layer. The circuit board of claim 8, further comprising an adhesive layer disposed on the dielectric core layer and exposing at least the first end of the first electrode and the first end of the second electrode . The circuit board of claim 8, wherein the passive component comprises a multilayer ceramic capacitor.