CN1555004A - 提高影像播放顺畅度的显示卡 - Google Patents

提高影像播放顺畅度的显示卡 Download PDF

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Publication number
CN1555004A
CN1555004A CNA2004100699879A CN200410069987A CN1555004A CN 1555004 A CN1555004 A CN 1555004A CN A2004100699879 A CNA2004100699879 A CN A2004100699879A CN 200410069987 A CN200410069987 A CN 200410069987A CN 1555004 A CN1555004 A CN 1555004A
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engine
image
clock
display
output interface
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CN1285020C (zh
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ε
廖德仁
许源泉
庄庆忠
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Via Technologies Inc
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Via Technologies Inc
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Abstract

一种提高影像播放顺畅度的显示卡，其包含一影像撷取引擎用以接收一数字影像信号，一存储器连接于该影像撷取引擎，用来储存该影像撷取引擎撷取的数字影像信号，一影像显示引擎连接于该存储器，用来接收储存于该存储器的数字影像信号，以及一时钟产生器，连接于该影像撷取引擎与该影像显示引擎，用来对该影像撷取引擎与该影像显示引擎提供同一时钟，以使该影像撷取引擎与该影像显示引擎同步接收数字影像信号。

Description

提高影像播放顺畅度的显示卡
技术领域
本发明涉及一种显示卡，特别是涉及一种提高影像播放顺畅度的显示卡。
背景技术
请参阅图1，图1为已知显示卡100的示意图，显示卡100包含一译码器120，其包含一第一时钟产生器122。显示卡100还包含一影像撷取引擎130、一影像处理引擎150、一存储器140、一影像显示引擎160、一影像处理时钟产生器152、一第二时钟产生器162、一电视编码器110、一液晶显示器(Liquid Crystal Display，LCD)输出接口112、一阴极射线管(Cathode RayTube，CRT)显示器输出接口114，以及一等离子体显示器(Plasma DisplayPanel，PDP)输出接口116。在已知显示卡100中，影像撷取引擎130、影像处理引擎150以及影像显示引擎160分别接收不同的时钟来源，影像撷取引擎130所需的时钟CAPCLK是由译码器120的第一时钟产生器122所提供；影像处理引擎150所需的时钟ECK是由影像处理时钟产生器152所提供；影像显示引擎160所需的时钟DCK是由第二时钟产生器162所提供。其中影像撷取引擎130与影像显示引擎160所需的时钟频率须相同，即实时钟CAPCLK与时钟DCK须同步，以避免输出影像至显示器时，造成影像丢帧(drop-frame)现象，即播放不顺畅。但由于第一时钟产生器122与第二时钟产生器162为各自独立的锁相回路，所以必定存在频率差的问题，而无法使影像撷取引擎130与影像显示引擎160同步(意即同频率)，所以会发生播放不顺畅的现象。
举例来说，在ITU-R BT601规范中，二个时钟产生器122、162设定为欲产生频率27MHz的时钟，然而由于第二时钟产生器162是由一参考时钟起振再产生出输出时钟，而非依据第一时钟产生器122产生的时钟来产生输出时钟，因此两时钟产生器122、162所产生的时钟必定会有误差，假设第一时钟产生器122产生的时钟为27MHz，第二时钟产生器162产生的时钟为26.9MHz，以这个例子来看，因为这两个时钟的频率些许不同，久而久之就会造成丢帧现象，即播放不顺畅。反之，若第一时钟产生器122产生的时钟为27MHz，第二时钟产生器162产生的时钟为27.1MHz，此时影像播放的速度快于影像自撷取装置输入的速度，如此影像播放装置便有可能在一段时间后(当两者的频率差距累积到播放一帧(frame)的时间时)，需要重复播放同一张撷取的影像。不论是丢帧或重复的影像，都会造成观看影片的不流畅感。
发明内容
本发明提供一种提高影像播放顺畅度的显示卡，以解决上述已知的问题。
本发明披露了一种提高影像播放顺畅度的显示卡，其包含一影像撷取引擎，用以接收数字影像信号，一存储器，连接于该影像撷取引擎，用来储存该影像撷取引擎撷取的数字影像信号，一影像显示引擎，连接于该存储器，用来接收储存于该存储器的数字影像信号，以及一第一时钟产生器，连接于该影像撷取引擎与该影像显示引擎，用来对该影像撷取引擎与该影像显示引擎提供同一时钟，以使该影像撷取引擎与该影像显示引擎同步接收数字影像信号。
附图说明
图1为已知显示卡的示意图。
图2为本发明显示卡第一实施例的示意图。
图3为本发明显示卡第二实施例的示意图。
附图符号说明
110、210  电视编码器              112、212   LCD输出接口
114、214  CRT输出接               116、216   PDP输出接口
120、220  译码器                  122、222   第一时钟产生器
130、230  影像撷取引擎            140、240   存储器
150、250  影像处理引擎
152、252  影像处理时钟产生器
160、260  影像显示引擎            162        第二时钟产生器
270       第二时钟产生器          280        多任务器
286            输出埠
282、284       输入埠
100、200、300  显示卡
具体实施方式
请参阅图2，图2为本发明显示卡200的示意图，显示卡200包含一译码器220，其包含一第一时钟产生器222。显示卡200还包含一影像撷取引擎230、一影像处理引擎250、一存储器240、一影像显示引擎260、一影像处理时钟产生器252、一电视编码器210、一液晶显示器(LCD)输出接口212、一阴极射线管(CRT)显示器输出接口214，以及一等离子体显示器(PDP)输出接口216。译码器220将接收的模拟影像信号AVS转换为数字影像信号DVS。影像撷取引擎230用以接收译码器220的数字影像信号DVS存入存储器240中，存储器240连接于影像撷取引擎230。影像处理引擎250自存储器240中读取数字影像信号DVS，对数字影像信号DVS作影像放大、影像缩小或其它特殊的影像效果的处理，而形成数字影像数据DVD储存至存储器240中。影像显示引擎260自存储器240读取数字影像数据DVD再输出至一输出接口例如电视编码器210、LCD输出接口212、CRT输出接口214或PDP输出接口216，影像显示引擎260所读取储存于存储器240中的影像数据可为影像撷取引擎230传送至存储器240的数字影像信号(未经特殊处理)或为经过影像处理引擎250所处理过后的数字影像数据。
在显示卡200中，译码器220的第一时钟产生器222为一锁相回路，连接于影像撷取引擎230与影像显示引擎260，用以提供同一时钟DCK于影像撷取引擎230与影像显示引擎260，以使影像撷取引擎230与影像显示引擎260的时钟同步，进而避免影像不顺畅的现象。此外，第一时钟产生器222还可连接于译码器220与电视编码器210、输出接口212、214以及216，以提供与影像撷取引擎230、影像显示引擎260同一频率的时钟DCK于电视编码器210、输出接口212、214以及216。
由于显示卡200内部的构件并非全设置于同一芯片中，译码器220是设置于第一芯片202中，影像撷取引擎230、影像处理引擎250、影像处理时钟产生器252、存储器240以及影像显示引擎260是设置于第二芯片204中，而电视编码器210、液晶显示器输出接口212、阴极射线管显示器输出接口214以及等离子体显示器输出接口216是设置于第三芯片206中，当第一芯片202上的第一时钟产生器222输出时钟CAPCLK于第二芯片204上的影像撷取引擎230与影像显示引擎260，以及输出时钟CAPCLK于第三芯片206的编码器210、输出接口212、214与216时，由于时钟CAPCLK自一芯片传至另一芯片可能会有时钟跳动(jitter)的现象，易造成影像显示引擎260、编码器210、输出接口212、214以及216所接收的时钟CAPCLK有跳动的现象，进而使影像显示于屏幕时会有画面跳动或其它问题产生，因此为避免因时钟跳动造成显示影像的品质降低，图3所示的本发明另一实施例可解决此问题。
请参阅图3，图3为本发明另一实施例显示卡300的示意图。显示卡300与显示卡200的架构相似，在此相同组件以相同符号表示，在此不再重复说明，不同之处是在显示卡300中增加了第二时钟产生器270与多任务器280，第二时钟产生器270连接于第一时钟产生器222及多任务器280的第二输入端284，第二时钟产生器270为一锁相回路，用来依据第一时钟产生器222产生的时钟(CAPCLK)产生与第一时钟产生器222产生的时钟(CAPCLK)相同周期的时钟(DCK)。多任务器的输出端286连接于影像显示引擎260、编码器210、输出接口212、214以及216，用来提供同一时钟CAPCLK或DCK。另外，多任务器280的第一输入端282直接接收第一时钟产生器222所产生的时钟CAPCLK，以可经由多任务器280的输出端286将同一时钟CAPCLK提供于影像显示引擎260、编码器210、输出接口212、214以及216，此与显示卡200直接提供同一时钟于影像撷取引擎230、影像显示引擎260、编码器210、输出接口212、214以及216是相同的方式。在本实施例中，使用者可藉由操控多任务器280的控制端288来选择输出第一时钟产生器222产生的时钟CAPCLK或第二时钟产生器270产生的时钟DCK。
如前所述，由于CAPCLK自一芯片传至另一芯片可能会有时钟跳动(jitter)的现象，因此，藉由第二时钟产生器270依据第一时钟产生器222产生的时钟(CAPCLK)产生与第一时钟产生器222产生的时钟(CAPCLK)相同周期的时钟(DCK)，此锁出的DCK较稳定，便可避免时钟跳动的问题。相同地，影像撷取引擎230自另一芯片接收CAPCLK时亦有时钟跳动的可能，然而图3的实施例中并未重新锁出CAPCLK，如第二时钟产生器270重新锁出DCK，其原因为，只要影像撷取引擎230所需的时钟的频率与译码器220接收影像时钟的频率相同，即可正确地撷取影像数据并将影像数据存至存储器240中。
另外，如前所述，显示卡200、300内部的构件并非全设置于同一芯片中，然而本发明亦可将显示卡200、300内部的构件设计于同一芯片中，再应用本发明的第一实施例(如图2)的方式，即可避免已知的影像晃动现象，而不必使用第二时钟产生器270重新锁出DCK。
以上所述仅为本发明的较佳实施例，凡依本发明的权利要求所做的均等变化与修饰，皆应属本发明专利的涵盖范围。

Claims (16)

1.一种提高影像播放顺畅度的显示卡，其包含：
一影像撷取引擎，用以接收一数字影像信号；
一存储器，连接于该影像撷取引擎，用来储存该影像撷取引擎撷取的数字影像信号；
一影像显示引擎，连接于该存储器，用来接收储存于该存储器的数字影像信号；以及
一第一时钟产生器，连接于该影像撷取引擎与该影像显示引擎，用来对该影像撷取引擎与该影像显示引擎提供同一时钟，以使该影像撷取引擎与该影像显示引擎同步接收数字影像信号。
2.如权利要求1所述的显示卡，其还包含一电视编码器，连接于该影像显示引擎。
3.如权利要求2所述的显示卡，其中该第一时钟产生器还连接于该编码器，用来对该影像撷取引擎、该影像显示引擎以及该编码器提供同一时钟。
4.如权利要求1所述的显示卡，其还包含一输出接口，连接于该影像显示引擎，用来输出自该影像显示引擎的数字影像信号。
5.如权利要求4所述的显示卡，其中该第一时钟产生器还连接于该输出接口，用来对该影像撷取引擎、该影像显示引擎以及该输出接口提供同一时钟。
6.如权利要求4所述的显示卡，其中该输出接口为LCD输出接口、CRT输出接口或PDP输出接口。
7.如权利要求1所述的显示卡，其还包含一影像处理引擎，连接于该存储器，用来将该存储器的数字影像信号处理成一数字影像数据后，再传回存储器内。
8.如权利要求7所述的显示卡，其还包含一影像处理时钟产生器，连接于该影像处理引擎，以该影像处理时钟产生器产生的时钟提供给该影像处理引擎。
9.一种提高影像播放顺畅度的显示卡，其包含：
一影像撷取引擎，用以接收一数字影像信号；
一存储器，连接于该影像撷取引擎，用来储存该影像撷取引擎撷取的数字影像信号；
一影像显示引擎，连接于该存储器，用来接收储存于该存储器的数字影像信号；
一多任务器，其输出端连接于该影像显示引擎；
一第一时钟产生器，连接于该影像撷取引擎与该多任务器的第一输入端，用来对该影像撷取引擎与该多任务器的第一输入端提供相同的一第一时钟；以及
一第二时钟产生器，连接于该第一时钟产生器及该多任务器的第二输入端，用来接收该第一时钟来产生一第二时钟，该第一时钟与该第二时钟为具有同周期的时钟但固定相位差的两时钟。
10.如权利要求9所述的显示卡，其还包含一电视编码器，连接于该影像显示引擎。
11.如权利要求10所述的显示卡，其中该多任务器的输出端还连接于该编码器，用来对该影像显示引擎以及该编码器提供同一时钟。
12.如权利要求9所述的显示卡，其还包含一输出接口，连接于该影像显示引擎，用来输出自该影像显示引擎的数字影像信号。
13.如权利要求12所述的显示卡，其中该多任务器的输出端还连接于该输出接口，用来对该影像显示引擎以及该输出接口提供同一时钟。
14.如权利要求12所述的显示卡，其中该输出接口为LCD输出接口、CRT输出接口或PDP输出接口。
15.如权利要求9所述的显示卡，其还包含一影像处理引擎，连接于该存储器，用来将该存储器的数字影像信号处理成一数字影像数据后，再传回存储器内。
16.如权利要求15所述的显示卡，其还包含一影像处理时钟产生器，连接于该影像处理引擎，以该影像处理时钟产生器产生的时钟提供给该影像处理引擎。
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