CN1312841C - 可将像素时钟脉冲转换为字时钟脉冲的转接装置 - Google Patents

可将像素时钟脉冲转换为字时钟脉冲的转接装置 Download PDF

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CN1312841C
CN1312841C CNB2004100825405A CN200410082540A CN1312841C CN 1312841 C CN1312841 C CN 1312841C CN B2004100825405 A CNB2004100825405 A CN B2004100825405A CN 200410082540 A CN200410082540 A CN 200410082540A CN 1312841 C CN1312841 C CN 1312841C
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clock pulse
pixel clock
pixel
word
cycle
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CN1592106A (zh
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廖德仁
许源泉
庄庆忠
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Via Technologies Inc
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Via Technologies Inc
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Abstract

一种可将像素时钟脉冲转换为字时钟脉冲的转接装置，其包含一像素时钟脉冲发生器，一分频器以及一逻辑单元。该像素时钟脉冲用来产生像素时钟脉冲，其周期的数目在一预定时段并非为一预定数字的整数倍。该分频器连接于该像素时钟脉冲发生器，用来对该像素时钟脉冲分频以产生字时钟脉冲。该逻辑单元用来依据该像素时钟脉冲于该预定时段中的周期的数目控制该分频器将该像素时钟脉冲中的部分时钟脉冲的周期的数目除以该预定数字以及将该像素时钟脉冲中的其余部分时钟脉冲的周期的数目除以非该预定数字的数字。

Description

可将像素时钟脉冲转换为字时钟脉冲的转接装置
技术领域
本发明提供一种转接(connection)装置，特别指一种可将像素时钟脉冲转换为字时钟脉冲的转接装置。
背景技术
请参考图1，图1为常规转接装置100的示意图，像素时钟脉冲中发生器130用以产生像素时钟脉冲(pixel clock，PCK)，其周期的数目在一预定时段为一预定数字的整数倍，并将其所产生的像素时钟脉冲输入至分频器140，分频器140根据像素时钟脉冲发生器130所输出的像素时钟脉冲产生字时钟脉冲(character clock，CCK)并将所产生的字时钟脉冲输出至时间控制模块120，逻辑单元110用来控制时间控制模块120的第二计数器122，以使第二计数器122根据分频器140所输出的字时钟脉冲，控制何时使控制信号(如Hsync、VSync…等等)进行转变(L(低)至H(高)或H至L)。
由于控制图像显示于显示器的时间以一字(character)的周期为单位，一字的周期等于八个像素(pixel)或九个像素的周期(1 CCK cycle＝8 or 9 PCKcycles)，因此，分频器140所产生的字时钟脉冲周期为八倍的像素时钟脉冲周期或为九倍的像素时钟脉冲周期。
于此以一字的周期长度等于八个像素的周期长度为例进行说明，请参考图2，图2为在预定时段中周期数目为八的整数倍的像素时钟脉冲与字时钟脉冲的关系图，设定分频器140的第一计数器不断自0数至7(CNT PCK值自0数至7)，且令CNT PCK值为0、1、2、3时CCK为H，其余为L，因此，一个CCK的周期长度等于八个PCK的周期长度，如图2所示，意即分频器140根据像素时钟脉冲以及第一计数器142的CNT PCK值为产生图2的CCK。
请参考图3，图3为图2的字时钟脉冲与控制信号的关系图，图3中控制信号以HSync为例，在T3结束而T1开始时，显示信号会由L转为H，此时开始将图像显示于屏幕上。在T1接近尾声时，显示信号会由H转为L，之后在T1结束时，控制信号Hsync会由L转为H，并在T2结束时，控制信号Hsync会由H转为L。注意的是，T1、T2以及T3皆为CCK的周期的整数倍，CCK由图1的分频器140所产生，每一CCK的周期长度等于八个PCK的周期长度。图1中，时间控制模块120的第二计数器根据分频器140所输出的字时钟脉冲CCK，用以控制时间控制模块120产生如图3中的HSync，再利用HSync来控制屏幕的水平扫描。注意的是，HSync控制屏幕的水平扫描会因不同屏幕制造商或不同分辨率而有不同的控制方式，如HSync从L至H或从H至L来控制水平扫描等等。
当图像显示于显示器或电视屏幕时，以控制信号控制显示器或电视屏幕的扫描，而控制信号的时钟脉冲以一字的周期为单位，一字的周期长度等于八个像素(pixel)或九个像素的周期长度，意即仅可控制水平分辨率为八或九的整数倍的屏幕，但有些高分辨率的电视屏幕(如高画质电视，high definitiontelevision，HDTV)，根据VESA标准(Video Electronics Standards Association)其分辨率为2200×1100、2640×1320、2750×1375，其中如2750×1375的水平分辨率(2750)并非为八的整数倍，常规转接装置100便无法控制这些水平分辨率并非为八的整数倍的屏幕。
发明内容
本发明提供一种可将像素时钟脉冲转换为字时钟脉冲的转接装置，以解决上述常规的问题。
本发明公开一种可将像素时钟脉冲转换为字时钟脉冲的转接装置，其包含一像素时钟脉冲发生器，一分频器以及一逻辑单元。该像素时钟脉冲发生器用来产生像素时钟脉冲，其周期的数目在一预定时段并非为一预定数字的整数倍。该分频器连接于该像素时钟脉冲发生器，用来对该像素时钟脉冲分频以产生字时钟脉冲。该逻辑单元用来依据该像素时钟脉冲于该预定时段中的周期的数目控制该分频器将该像素时钟脉冲中的部分时钟脉冲的周期的数目除以该预定数字以及将该像素时钟脉冲中的其余部分时钟脉冲的周期的数目除以非该预定数字的数字，以使该分频器产生该字时钟脉冲。
附图说明
图1为常规转接装置的功能方块图。
图2为在预定时段中周期数目为八的整数倍的像素时钟脉冲与字时钟脉冲的关系图。
图3为图2的字时钟脉冲、控制信号与显示信号的关系图。
图4为本发明转接装置的功能方块图。
图5为在预定时段中周期数目为非八的整数倍的像素时钟脉冲与字时钟脉冲的关系图。
图6与图7为在不同处加入图5中的延长时钟脉冲的示意图。
附图符号说明
100、200转接装置          110、210逻辑单元
120时间控制模块           122第二计数器
130 像素时钟脉冲发生器    140、240分频器
142、242第一计数器
具体实施方式
在此以一字等于八个像素为例且屏幕分辨率为非八整数倍的状况进行说明，请参考图4，图4为本发明转接装置200的示意图，转接装置200与转接装置100不同处在于逻辑单元210可控制屏幕分辨率为非八整数倍的屏幕。逻辑单元210依据屏幕分辨率控制时间控制模块220的第二计数器222以及分频器240的第一计数器242，逻辑单元210控制时间控制模块220的第二计数器222的方法与常规技术相同，于此不再赘述。而逻辑单元210控制分频器240的第一计数器242用以产生分辨率为非八整数倍所需的字时钟脉冲。由于分辨率为非八整数倍，意即于一预定时段中的像素时钟脉冲的周期数目无法被八整除，因此，逻辑单元210根据此预定时段中所产生的像素时钟脉冲的周期数目，将此预定时段中像素时钟脉冲分为两部分，其一部分为可被八整除，其余部分为不可被八整除，逻辑单元210便根据所划分的两部分用以控制分频器240的第一计数器242以产生字时钟脉冲。
请参考图5，图5为在预定时段中周期数目为非八的整数倍的像素时钟脉冲PCK与字时钟脉冲CCK的关系图，设定分频器240的第一计数器242的CNT PCK值为0、1、2、3时CCK为H，其余为L，当预定时段中处理周期数目为非八的整数倍的像素时钟脉冲时，第一计数器242的CNT PCK值重复自0数至7，以产生多个如图2的CCK，并另设定在某个周期处加入一延长时钟脉冲，此延长时钟脉冲的长度根据在预定时段中的像素周期数目除以八后所得的余数，增加与余数相同数目的PCK周期长度，此加入该延长时钟脉冲的周期处即为逻辑单元210所划分的不可被八整除的部分，而其余部分为可被八整除的部分。
举例来说，假设一屏幕分辨率为2750×1375，将2750除以8，得商为343，余数为6，逻辑单元210则将此预定时段中的像素时钟脉冲分为242×8的部分以及(8+6)的其余部分，分频器240将342×8的部分以8(预定数字)分频以产生如图2中的CCK，而将(8+6)的部分以14(非预定数字)分频以产生如图5中一个CCK被延长6个PCK的长度的时钟脉冲。注意的是，当决定在某个周期处加入此延长时钟脉冲时，此时第一计数器242的CNT_PCK值会从0数到13，而非数到7，如此才可增加6个PCK长度于此周期中，产生完此延长时钟脉冲后，CNT_PCK值又会从0数到7，以继续产生多个如图2的CCK，换句话说，在产生每一水平扫描线的控制信号时，分频器240的第一计数器242仅需数一次0至13(CNT PCK自0数至13)，并数342次0至7，直到产生另一水平扫描线的控制信号时，再重新数一次0至13，并数342次0至7，如此重复下去。
将图5的实施例应用于控制分辨率为非八的整数倍的屏幕，如图6与图7所示，图6与图7为在不同处加入图5的延长时钟脉冲，图6为在图3的T2中最后一个CCK的周期内加入图5的延长时钟脉冲，而图7为在图3的T1中最后一个CCK的周期内加入图5的延长时钟脉冲，以使图6的各个区段(T1、T2′、T3)与图7各区段(T1′、T2、T3)仍为CCK的周期的整数倍。注意的是，图3中，T1的起始点为开始将图像显示于屏幕上的时间，因此，为确保图像正确地显示于屏幕上，在图6与图7中，不可将图5的延长时钟脉冲加入于图3的T3中最后一个CCK的周期内。当然，亦可将图5中6个多余的PCK周期可分配至超过一个CCK的周期内，举例来说，分频器240的第一计数器242可数1次0至9，1次0至11，并数341次0至7。或者，分频器240的第一计数器242可数6次0至8，并数337次0至7，以产生343个CCK的周期。
相较于先前技术，本发明将一预定时段中的像素时钟脉冲分为可被一整数整除的部分以及不可被该整数整除的部分。分频器会将不可被该整数整除的部分分频以产生一个CCK的周期，以使该预定时段中的像素时钟脉冲可转换为多个完整的CCK的周期。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求，所进行等效变化与修改，皆应属本发明的涵盖范围。

Claims (8)

1.一种可将像素时钟脉冲转换为字时钟脉冲的转接装置，其包含：
一像素时钟脉冲发生器，用来产生像素时钟脉冲，其周期的数目在一预定时段并非为一预定数字的整数倍；
一分频器，连接于该像素时钟脉冲发生器，用来对该像素时钟脉冲分频以产生字时钟脉冲；以及
一逻辑单元，连接于该像素时钟脉冲发生器与该分频器，用来依据该像素时钟脉冲于该预定时段中的周期的数目，控制该分频器将该像素时钟脉冲分为两部分，一部分为可被该预定数字所整除，其余部分为不可被该预定数字所整除，以该不可该预定数字所整除的像素周期数目产生一延长时钟脉冲；其中，该分频器会在有一水平扫描线的控制信号产生时，将该延长时钟脉冲加入每一水平扫描线的该字时钟脉冲周期中。
2.如权利要求1所述的转接装置，其中该逻辑单元用来使该分频器对该预定时段中的像素时钟脉冲分频后产生的字时钟脉冲的周期的数目成为一整数。
3.如权利要求1所述的转接装置，其中该预定数字为八或九。
4.如权利要求1所述的转接装置，其中将该延长时钟脉冲加入每一水平扫描线的某一个字时钟脉冲周期中或分配于每一水平扫描线的多个字时钟脉冲周期中。
非该预定数字的数字为该像素时钟脉冲中的其余部分时钟脉冲的周期的数目。
5.一种将像素时钟脉冲转换为字时钟脉冲的方法，其包含：
提供像素时钟脉冲，其周期的数目在一预定时段并非为一预定数字的整数倍；以及
依据该像素时钟脉冲于该预定时段中的周期的数目，将该像素时钟脉分为两部分，一部分为可被该预定数字所整除，其余部分为不可被该预定数字所整除，以该不可该预定数字所整除的像素周期数目产生一延长时钟脉冲；其中，该分频器会在有一水平扫描线的控制信号产生时，将该延长时钟脉冲加入每一水平扫描线的该字时钟脉冲周期中。
6.如权利要求5所述的方法，其中对该预定时段中的像素时钟脉冲分频后产生的字时钟脉冲的周期的数目为一整数。
7.如权利要求5所述的方法，其中该预定数字为八或九。
8.如权利要求5所述的方法，其中将该延长时钟脉冲加入每一水平扫描线的某一个字时钟脉冲周期中或分配于每一水平扫描线的多个字时钟脉冲周期中。
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