CN1530665A - 测试动态存储电路之方法及测试电路 - Google Patents
测试动态存储电路之方法及测试电路 Download PDFInfo
- Publication number
- CN1530665A CN1530665A CNA200410028418XA CN200410028418A CN1530665A CN 1530665 A CN1530665 A CN 1530665A CN A200410028418X A CNA200410028418X A CN A200410028418XA CN 200410028418 A CN200410028418 A CN 200410028418A CN 1530665 A CN1530665 A CN 1530665A
- Authority
- CN
- China
- Prior art keywords
- bit line
- storage unit
- switching device
- device shifter
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 75
- 238000000034 method Methods 0.000 title claims abstract description 19
- 238000003860 storage Methods 0.000 claims description 151
- 230000006698 induction Effects 0.000 claims description 69
- 238000011002 quantification Methods 0.000 claims description 25
- 230000002950 deficient Effects 0.000 description 26
- 239000003990 capacitor Substances 0.000 description 11
- 230000006870 function Effects 0.000 description 7
- 238000012423 maintenance Methods 0.000 description 5
- 238000010998 test method Methods 0.000 description 5
- 230000003213 activating effect Effects 0.000 description 4
- 238000006073 displacement reaction Methods 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- 241001269238 Data Species 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/026—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
Landscapes
- Dram (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
Description
Claims (7)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10310570.0 | 2003-03-11 | ||
DE10310570A DE10310570B3 (de) | 2003-03-11 | 2003-03-11 | Verfahren und Testschaltung zum Testen einer dynamischen Speicherschaltung |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1530665A true CN1530665A (zh) | 2004-09-22 |
CN100342240C CN100342240C (zh) | 2007-10-10 |
Family
ID=32920723
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB200410028418XA Expired - Fee Related CN100342240C (zh) | 2003-03-11 | 2004-03-11 | 测试动态存储电路的方法及测试电路 |
Country Status (3)
Country | Link |
---|---|
US (1) | US6862234B2 (zh) |
CN (1) | CN100342240C (zh) |
DE (1) | DE10310570B3 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101821810B (zh) * | 2007-08-31 | 2013-05-01 | 国立大学法人东京工业大学 | 利用电流感应磁化反转mtj的非易失性sram/锁存电路 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7308624B2 (en) * | 2005-04-28 | 2007-12-11 | Infineon Technologies North America Corp. | Voltage monitoring test mode and test adapter |
JP4851189B2 (ja) * | 2006-01-11 | 2012-01-11 | エルピーダメモリ株式会社 | 半導体記憶装置及びそのテスト方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6105152A (en) * | 1993-04-13 | 2000-08-15 | Micron Technology, Inc. | Devices and methods for testing cell margin of memory devices |
DE19944037C1 (de) * | 1999-09-14 | 2001-01-25 | Infineon Technologies Ag | Integrierter Speicher mit Speicherzellen und Referenzzellen |
JP2002208277A (ja) * | 2001-01-05 | 2002-07-26 | Toshiba Corp | 半導体記憶装置のセンスアンプ制御回路 |
DE10119052C1 (de) * | 2001-04-18 | 2002-12-05 | Infineon Technologies Ag | Integrierter Speicher und Verfahren zum Testen eines integrierten Speichers |
-
2003
- 2003-03-11 DE DE10310570A patent/DE10310570B3/de not_active Expired - Fee Related
-
2004
- 2004-03-11 US US10/798,245 patent/US6862234B2/en not_active Expired - Fee Related
- 2004-03-11 CN CNB200410028418XA patent/CN100342240C/zh not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101821810B (zh) * | 2007-08-31 | 2013-05-01 | 国立大学法人东京工业大学 | 利用电流感应磁化反转mtj的非易失性sram/锁存电路 |
Also Published As
Publication number | Publication date |
---|---|
US20040257893A1 (en) | 2004-12-23 |
DE10310570B3 (de) | 2004-09-30 |
US6862234B2 (en) | 2005-03-01 |
CN100342240C (zh) | 2007-10-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C41 | Transfer of patent application or patent right or utility model | ||
C56 | Change in the name or address of the patentee | ||
CP01 | Change in the name or title of a patent holder |
Address after: Munich, Germany Patentee after: Infineon Technologies AG Address before: Munich, Germany Patentee before: INFINEON TECHNOLOGIES AG |
|
TR01 | Transfer of patent right |
Effective date of registration: 20120920 Address after: Munich, Germany Patentee after: QIMONDA AG Address before: Munich, Germany Patentee before: Infineon Technologies AG |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20151224 Address after: German Berg, Laura Ibiza Patentee after: Infineon Technologies AG Address before: Munich, Germany Patentee before: QIMONDA AG |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20071010 Termination date: 20160311 |
|
CF01 | Termination of patent right due to non-payment of annual fee |