CN1514494A - 高性能垂直pnp晶体管及其制法 - Google Patents
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Abstract
本发明公开了一种高性能垂直PNP晶体管及其制法。所得的高性能垂直PNP晶体管包括发射极区,发射极区包括硅和锗,并且其PNP发射极与NPN晶体管的基极共享一层硅单层。该方法向传统的用于CMOS和双极器件的制造工艺添加了两个额外的掩模步骤,因此实现了对整个工艺流程的最小附加。所得的结构明显增强了PNP器件性能。
Description
技术领域
本发明涉及一种高性能PNP晶体管,以及形成垂直PNP和NPN晶体管的方法。
背景技术
持续增长的对移动通讯的使用促进了射频(RF)通讯的进步。特别是,膨胀的市场要求降低功耗低并提高性能。已经形成多种应用的一个可能的解决方案是双极型互补金属氧化物半导体(BiCMOS)技术。例如,见Wilson等人的“Process HJ:A 30GHz NPN and 20GHz PNP Complementary BipolarProcess For High Linearity RF Circuits,”BCTM,1998,第164页;Onai等人的“Self-Aligned Complementary Bipolar Technology for Low-PowerDissipation and Ultra-High Speed LSI’s,”IEEE TED,43:3,1995,第413页;Miwa等人的“A Complementary Bipolar Technology for Low Cost and HighPerformance Mixed Analog/Digital Applications,”BCTM,1996,第185页;以及,Chyan等人的“A 50GHz 0.25μm...BiCMOS Technology for Low-PowerWireless-Communication VLSI’s”BCTM,1998,第128页。
然而,随着越来越多地使用这项技术,出现了这样的问题,即目前仅可以获得高性能的垂直NPN晶体管。对于当前低性能的横向PNP晶体管仅能获得低于1GHz的截至阈值(fT)。
基于上述原因,本技术领域中需要高性能PNP晶体管,以及制备均具有高性能的NPN和PNP晶体管的方法。
发明内容
本发明包括一种用于制造高性能垂直NPN和PNP晶体管的方法,及所得结构。所得的高性能垂直PNP晶体管包括发射极区,发射极区包括硅和锗,并且其PNP发射极与NPN晶体管的基极共享一层硅单层(a single layerof silicon)。该方法向传统的用于CMOS和双极型器件的制造工艺添加了两个额外的掩模步骤,因此实现了对整个工艺流程的最小附加。所得的结构明显增强了PNP器件性能。
本发明的第一方面提供一种垂直PNP晶体管,包括:发射极区,包括硅和锗。
本发明的第二方面提供垂直PNP和NPN晶体管,包括:硅单层,其形成PNP晶体管的发射极区、NPN晶体管的非本征基极区、和NPN晶体管的本征基极区。
本发明的第三方面提供一种在形成CMOS器件和NPN晶体管的同时形成PNP晶体管的方法,其采用了除用于形成CMOS和NPN器件的掩模步骤以外的至少两个掩模步骤,该方法包括:第一掩模步骤,限定第一开口,通过第一开口进行用于PNP晶体管的本征基极和集电极的注入;以及,第二掩模步骤,限定PNP晶体管的发射极。
本发明的前述及其它特征将通过下面对本发明实施例的更加具体的描述而变得明显易懂。
附图说明
下面,将参照附图详细介绍本发明的实施例,其中相同的附图标记表示相同的元件,并且附图中:
图1示出了制造高性能PNP器件的方法的第一步;
图2和3分别示出了该方法的第二和第三步;
图4示出了该方法可选的第四步;
图5至15分别示出了该方法的第五至第十五步;以及
图16示出了该方法的第十六步和所得的高性能NPN及PNP晶体管。
具体实施方式
本发明包括制造高性能垂直NPN和PNP晶体管的方法及所得的结构。该方法产生了作为传统的SiGe BiCMOS制造技术的一部分的高性能垂直PNP晶体管。所得的高性能垂直PNP晶体管包括含有硅和锗的发射极区,并且其发射极与NPN晶体管的基极共享一层硅单层。此结构是应用SiGe低温外延层的结果,SiGe低温外延层在PNP区上形成多晶硅并在NPN区上形成单晶硅和多晶硅,接着进行形成垂直NPN的非本征基极和垂直PNP的发射极的单次注入。该方法向用于CMOS和双极器件的传统SiGe制造工艺增加了两个额外的掩模步骤,由此实现了对整个工艺流程的最小附加。
参照附图,图1至16示出了制造工艺步骤。在所有附图中,其中将要建立垂直NPN晶体管的NPN区2示于左侧,其中将要建立垂直PNP晶体管的PNP区4示于右侧。应认识到,为了简洁和清楚起见,忽略了一些根据传统SiGe技术的制造步骤。另外应理解的是,为了清楚起见,示出了一些传统SiGe技术的制造步骤,但这些步骤不是构成本发明的必要部分。
在第一步中,如图1所示,提供第一掩模步骤,其中例如通过旋涂在二氧化硅层22(以下称作“氧化物”)上涂布光致抗蚀剂10。光致抗蚀剂10以及此处所用的任何其它光致抗蚀剂可是任何公知或新近开发出来的光致抗蚀剂材料。按已知方式(例如,曝光和显影)在光致抗蚀剂10中形成用于注入15的开口。如果期望将器件与衬底12隔离开,和/或不提供实现相同目的的现有工艺,第一注入可包括用于为p型衬底12建立n型隔离部分23的n型材料。因此,此第一注入是可选的。其次,提供用于建立垂直PNP晶体管的集电极16的p型材料。最后是用于建立垂直PNP晶体管的本征基极18的n型材料。也可以在上述注入之前建立多个其它结构。在这些结构之中,如图1所示,包括浅槽隔离(STI)21、氧化层22和NPN次集电极25。此处和本说明书始终使用的n型材料可以是公知的或新近开发的用于此类掺杂的材料,例如砷、磷、锑、或这些材料的组合。类似地,此处和本说明书始终使用的p型材料可以是公知的或新近开发的用于此类掺杂的材料,例如硼、铟、或这些材料的组合。接着,按已知方式(例如,通过蚀刻)去除光致抗蚀剂10。
图2示出了第二步,其中沉积氮化硅层24(以下称作“氮化物”),接着是氧化层26。用抗蚀剂27遮蔽双极区,并蚀刻层24和26,以暴露出非双极区。然后,去除抗蚀剂27,并且层24和26保护双极区免受CMOS处理。然而应认识到,依据CMOS工艺,这些步骤可以不是必需的。注意,接下来的附图示出了仿佛未被蚀刻的层24和26。此处,可以执行部分地产生CMOS器件的公知制造步骤(未示出)。CMOS处理可以保留或者可以不保留覆盖氮化膜(blanket nitride film)(未示出)。然而,CMOS处理去除了氧化层26,因此需要再沉积另一氧化层26来在双极处理期间保护CMOS区。
图3示出了第三步,其中通过在层24和26之上涂布光致抗蚀剂28形成第二掩模,并且例如通过经由光致抗蚀剂28曝光并蚀刻层22、24和26形成开口30,从而暴露出PNP区4中的氧化层22(衬底12)的表面31。然后,例如通过蚀刻去除光致抗蚀剂28。
参照图4,其示出了可选的第四步。此可选的第四步掩模步骤包括在将要产生PNP区4的非本征基极36的位置上涂布光致抗蚀剂32并曝光形成开口34。接着,可以执行n型材料的注入从而形成PNP区4的非本征基极36。接着,去除光致抗蚀剂32。若未执行本步骤,如图15所示,则可以使用NFET源极/漏极注入在工艺结束时完成形成PNP区4的非本征基极36的n型注入,这将在下面介绍。此后一选择节省了掩模步骤,但产生了更高的基极电阻,并由此降低了PNP晶体管的性能。为清楚起见,图5至14未示出非本征基极部分36。
图5示出了第五步,其中沉积多晶硅层38,其填充了PNP区4上的开口并接触到表面31。多晶硅层38可以不小于10nm且不大于100nm,并且通常为约45nm。
接着,如图6所示,通过沉积氧化物(未示出),并籍由涂布/显影光致抗蚀剂(未示出)来进行掩蔽,再在NPN区2上蚀刻多晶硅层38至氮化层24,从而在NPN区2上产生开口40。(注意:依据前面的处理,氧化物可以不是必需的。)此处,进行N型材料的注入,从而形成NPN集电极50(依据前面NPN集电极的处理,此注入可以不是必需的)。接着,去除抗蚀剂,并且依据后续处理,进行蚀刻,直至NPN区2上的氧化层22或衬底12。
在下面的步骤中,如图7所示,在整个晶片上生长硅-锗(SiGe)的外延层42。随着外延层42的生长,SiGe由于其与硅相接触而在NPN区2上生长为单晶层46,但在多晶硅38上,即PNP区4上的区域上,生长成多晶层46。伴随沉积的发生,将添加p型材料,使得所得的层42包括NPN区2的p型基极48。在某些情况中,外延层42也可包括一些沉积在添加至层42的p型材料附近的碳。所得层42包括锗的最大浓度不小于总的硅和锗成分(combined silicon and germanium composition)的10%且不大于总的硅和锗成分的30%的区域。
图8至16示出了最终获得最后的高性能NPN和PNP晶体管的公知的SiGe技术的连续步骤。这些步骤在美国专利第5111271号中描述,其在此作为参考引入。应该认识到,为了使集成线路适用于不同的应用,这些步骤可以稍作变化。图8示出了其中氧化层52生长在整个晶片上,接着沉积氮化层54而最后是多晶硅层56的步骤。
图9示出了接下来的步骤,其中沉积并随后蚀刻掉另一层氮化层(未示出)从而在NPN区2上形成心轴(mandrel)58。另外,靠近心轴58按传统方式(例如,沉积并蚀刻氧化物)形成氧化间隔壁60。接着,注入p型材料61(例如,硼)从而形成NPN区2的非本征基极62和PNP区4的发射极64。p型材料缓慢地扩散入单晶层44中,但是快速地扩散入多晶层,例如多晶硅层38和SiGe层46。p型外扩散65通过在多晶硅中迅速扩散而形成。结果,同时形成了PNP区4的发射极64和NPN区2的非本征基极62。所得的结构包括PNP晶体管发射极区64中的多晶硅、以及NPN晶体管的非本征基极区62的一部分中的单晶硅和本征基极区63中的单晶硅。
如图10所示,接下来的步骤包括从心轴58处蚀刻掉间隔壁60(图9),并执行重度氧化68。随着氧化的发生,多晶硅层56(图9)转化为氧化层70。然而,多晶硅层56在氮化物心轴58下的部分71保留为多晶硅,因此将心轴58的形状转印至多晶硅层56。所得的结构允许将要形成的NPN区2的发射极与NPN区2的非本征基极62自对准。
参照图11,接下来的步骤包括选择性地蚀刻掉多晶硅部分71、氮化物心轴58、以及氧化层70、氮化层54和氧化层52的在其下的部分。
接下来的步骤,如图12所示,包括沉积多晶硅层72,并且或者在沉积期间或者通过注入74以n型材料对其掺杂,从而形成NPN区2的发射极76。
如图13所示,沉积氮化层78。然后用光致抗蚀剂(未示出)遮蔽掉NPN发射极76。接着,去除(例如通过蚀刻)各个层(即氮化层78、多晶硅层72、氧化层50和70、以及氮化层54)。接着,去除抗蚀剂(未示出)。
接下来的步骤,如图14所示,包括用光致抗蚀剂(未示出)遮蔽NPN区2和PNP发射极64,并蚀刻掉SiGe多晶硅层46和多晶硅层38。此蚀刻限定了NPN晶体管100的基极和PNP晶体管102的发射极64。然后,剥落光致抗蚀剂(未示出),并蚀刻氧化层26。
参照图15,如果略去了图4所示的可选的第三掩模,则可以使用CMOSNFET源极/漏极处理(未示出)从而形成PNP区4的非本征基极36。在此条件下,将蚀刻氮化层24(若存在),形成光致抗蚀剂掩模并注入N型材料80,从而建立非本征基极36。然后,将剥落光致抗蚀剂(未示出)。
最后,如图16所示,透过掩模(未示出)进行p型材料82的注入,以用于形成PFET源极/漏极(未示出)。此注入还形成了PNP集电极接触84。
继续参见图16,所得的垂直晶体管100和102包括PNP晶体管102的多晶硅发射极64和NPN晶体管100的多晶硅发射极76。垂直PNP晶体管102包括发射极区64,发射极区64包括硅和锗。另外,垂直NPN和PNP晶体管100和102包括硅单层,其形成了PNP晶体管102的发射极区64、NPN晶体管100的非本征基极62和NPN晶体管100的本征基极63。所得的结构提供了同当前的横向PNP晶体管相比具有明显增强的性能(可具有fT>1GHz的截止频率)的PNP晶体管102。
如上所述,形成PNP晶体管102的方法,除了用于形成CMOS器件(未示出)和NPN晶体管102的掩模步骤之外,使用两个附加的掩模步骤,图1和图3。未示出的CMOS工艺步骤可包括栅极氧化物生长、FET多晶硅的沉积和蚀刻、间隔壁的生长和/或沉积以及蚀刻、延展和环形(halo)掩模及注入、源极/漏极的掩模和注入等等。图1的第一掩模步骤限定了开口14,通过开口14进行PNP本征基极18、PNP集电极16和PNP n型隔离23(若前面的掩模和注入可用于相同的功能,后者是可选)注入。图3的第二掩模步骤限定了开口30,通过开口30形成PNP发射极64。
虽然本发明已经结合上面描述的具体实施例介绍如上,但是显然,各种替换、改动和变化对本领域技术人员是十分明显的。另外,本发明如前面所阐释的实施例是为了说明,而并非限制。各种变化可在不脱离本发明如权利要求所限定的实质和范围的条件下进行。
Claims (20)
1.一种垂直PNP晶体管,包括:
发射极区,包括硅和锗。
2.如权利要求1所述的晶体管,其中最大锗浓度构成不小于硅和锗的10%,并且最大锗浓度构成不大于硅和锗的30%。
3.如权利要求1所述的晶体管,其中硅为多晶硅。
4.如权利要求1所述的晶体管,其中晶体管具有大于1GHz的截止频率。
5.如权利要求1所述的晶体管,其中发射极区还包括碳。
6.一种垂直PNP和NPN晶体管,包括:
硅单层,其形成PNP晶体管的发射极区、NPN晶体管的非本征基极区和NPN晶体管的本征基极区。
7.如权利要求6所述的垂直PNP和NPN晶体管,其中PNP晶体管的发射极区包括硅和锗。
8.如权利要求7所述的垂直PNP和NPN晶体管,其中最大锗浓度构成不小于硅和锗的10%,并且该锗浓度构成不大于硅和锗的30%。
9.如权利要求7所述的垂直PNP和NPN晶体管,其中发射极区还包括碳。
10.如权利要求7所述的垂直PNP和NPN晶体管,其中硅层为PNP晶体管的发射极区中的多晶硅、以及NPN晶体管的非本征基极区的一部分中的单晶硅和本征基极区中的单晶硅。
11.如权利要求6所述的垂直PNP和NPN晶体管,其中PNP晶体管具有大于1GHz的截止频率。
12.一种在形成互补金属氧化物半导体器件和NPN晶体管的同时形成PNP晶体管的方法,其采用了除用于形成互补金属氧化物半导体和NPN器件的掩模步骤以外的至少两个掩模步骤,该方法包括:
第一掩模步骤,其限定第一开口,通过第一开口进行用于PNP晶体管的本征基极和集电极的注入;以及
第二掩模步骤,其限定PNP晶体管的发射极。
13.如权利要求12所述的方法,还包括通过第一开口注入n型隔离从而将PNP集电极与衬底分开的步骤。
14.如权利要求12所述的方法,还包括第三掩模步骤,其限定至少一个开口,通过该开口进行用于PNP的非本征基极的注入。
15.如权利要求12所述的方法,还包括步骤:
在第二开口上沉积多晶硅层;以及
生长硅和锗的外延层,
其中,硅在多晶硅层上生长为多晶硅,而在NPN上生长为单晶硅。
16.如权利要求15所述的方法,还包括通过注入p型材料同时形成PNP的发射极和NPN的非本征基极的步骤。
17.如权利要求16所述的方法,其中PNP的发射极包括硅和锗。
18.如权利要求15所述的方法,其中外延层还包括碳。
19.如权利要求15所述的方法,还包括在生长步骤期间添加p型材料的步骤。
20.如权利要求15所述的方法,其中多晶硅层不小于10nm,并且其中多晶硅层不大于100nm。
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US10/065,837 US6909164B2 (en) | 2002-11-25 | 2002-11-25 | High performance vertical PNP transistor and method |
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US7972919B2 (en) | 2005-07-18 | 2011-07-05 | International Business Machines Corporation | Vertical PNP transistor and method of making same |
CN102412200A (zh) * | 2011-10-18 | 2012-04-11 | 上海华虹Nec电子有限公司 | 与锗硅异质结npn三极管集成的pnp三极管工艺实现方法 |
CN102637597A (zh) * | 2011-02-10 | 2012-08-15 | 上海宏力半导体制造有限公司 | 垂直pnp制备方法 |
CN103107087A (zh) * | 2011-11-09 | 2013-05-15 | 上海华虹Nec电子有限公司 | 与锗硅异质结npn三极管集成的pnp三极管的制造方法 |
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US7342293B2 (en) * | 2005-12-05 | 2008-03-11 | International Business Machines Corporation | Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same |
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US7972919B2 (en) | 2005-07-18 | 2011-07-05 | International Business Machines Corporation | Vertical PNP transistor and method of making same |
CN102637597A (zh) * | 2011-02-10 | 2012-08-15 | 上海宏力半导体制造有限公司 | 垂直pnp制备方法 |
CN102412200A (zh) * | 2011-10-18 | 2012-04-11 | 上海华虹Nec电子有限公司 | 与锗硅异质结npn三极管集成的pnp三极管工艺实现方法 |
CN103107087A (zh) * | 2011-11-09 | 2013-05-15 | 上海华虹Nec电子有限公司 | 与锗硅异质结npn三极管集成的pnp三极管的制造方法 |
CN103107087B (zh) * | 2011-11-09 | 2015-10-14 | 上海华虹宏力半导体制造有限公司 | 与锗硅异质结npn三极管集成的pnp三极管的制造方法 |
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US20040248352A1 (en) | 2004-12-09 |
CN1321462C (zh) | 2007-06-13 |
US20040099895A1 (en) | 2004-05-27 |
KR100544548B1 (ko) | 2006-01-24 |
TW200423383A (en) | 2004-11-01 |
TWI269432B (en) | 2006-12-21 |
US7265010B2 (en) | 2007-09-04 |
US6909164B2 (en) | 2005-06-21 |
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