CN1499642A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN1499642A
CN1499642A CNA2003101134607A CN200310113460A CN1499642A CN 1499642 A CN1499642 A CN 1499642A CN A2003101134607 A CNA2003101134607 A CN A2003101134607A CN 200310113460 A CN200310113460 A CN 200310113460A CN 1499642 A CN1499642 A CN 1499642A
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濑川泰生
青田雅明
山田努
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Sanyo Electric Co Ltd
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Abstract

本发明关于一种半导体装置及其制造方法，其特征在于，使隔着栅极绝缘层与TFT(10)的栅极电极(20)电容结合的第1半导体层(15)，及隔着栅极绝缘层与保持电容的保持电容线(42)电容结合的第2半导体层(16)相互分开，并且由金属配线(43)连接第1半导体层(15)与第2半导体层(16)。即，分别使TFT(10)的栅极电极(20)与第1半导体层(15)电容结合，及使保持电容的保持电容线(42)与第2半导体层(16)电容结合，由于该结合而使各半导体层的电位产生变化，因此，不会产生大的电位差，可防止绝缘破坏或绝缘泄漏的发生。

Description

半导体装置及其制造方法
技术领域
本发明关于一种半导体装置及其制造方法，该半导体装置具有：形成在基板上的薄膜晶体管；以及与所述薄膜晶体管相邻接而形成，用以保持通过该薄膜晶体管所供给的电压的保持电容。
背景技术
图4是现有例子的液晶显示装置的构成图。液晶面板100具有配置成n行m列矩阵的多个像素，各像素由像素选择用薄膜晶体管TFT 10(以下称TFT 10)、液晶LC及保持电容Csc构成。
在TFT 10的栅极上连接有朝行方向延伸的栅极线20，而在漏极则连接有朝列方向延伸的数据线22。由垂直驱动电路(V驱动电路)130顺次对各行的栅极线20供给栅极扫描信号，且依据此来选择像素选择晶体管。另外，依据来自水平驱动电路(H驱动电路)140的漏极扫描信号对数据线22供给视频信号，并通过TFT 10施加到液晶LC。在此，保持电容Csc用来保持通过TFT 10所供给的视频信号。
图5是表示上述像素的平面图。此外，图6表示沿图5中Y-Y线的截面图。另外，图5是从第1基板100的背面看的平面图。此液晶显示装置是由在采用玻璃等透明绝缘材料的第1基板100与第2基板500之间挟持并贴合液晶200而构成。
在像素中，TFT 10的半导体层14(例如，多晶硅层)呈弯曲状态，2处与朝行方向直线延伸的栅极线20交叉。在该2个交叉部分，在半导体层14上构成沟道区域14c。另外，栅极线20构成所谓双栅极。
在栅极电极与沟道区域14c之间形成有栅极绝缘层66。半导体层14的漏极区域14d隔着形成在层间绝缘膜68与栅极绝缘层66的接触孔C0而与朝列方向延伸的数据线22连接。
然后，TFT 10的源极区域14s隔着形成在层间绝缘膜68与栅极绝缘层66的接触孔C1，而与金属配线40相连接。该金属配线40与数据线22以同一层(例如，铝层)在层间绝缘膜68上形成。另外，该金属配线40隔着设置在平坦化绝缘膜72上的接触孔C2而与上层的像素电极24相连接，该平坦化绝缘膜72形成于金属配线40上。
另外，保持电容线42与栅极线20由同一层(例如钼膜、铬膜)构成，朝行方向直线延伸，并隔着栅极绝缘层66与半导体层14的一部分重叠，而该重叠部分构成保持电容Csc。
另外，有关上述的液晶显示装置例如在以下专利文献1中记载。
专利文献1
特开平1-129234号公报
但是，在上述的液晶显示装置的制造过程中，经常会有TFT 10的栅极电极下的栅极绝缘层66发生绝缘破坏或绝缘泄漏不良等情况。以下说明其原因。
图7是表示液晶显示装置的制造过程的截面图，为沿图5的Y-Y线的剖视图。在栅极线20及保持电容线42的加工上虽采用干式蚀刻，但这时静电会积存在栅极线20及保持电容线42处。另外，此后以栅极线20作为掩模，而对半导体层14离子注入如砷或磷等N型杂质而形成源极区域14s及漏极区域14d时，也会产生电荷累积(charge-up)现象，使静电积存在栅极线20及保持电容线42。由于栅极线20及保持电容线42横贯液晶面板100而延伸，因此特别容易带静电。
由此，栅极线20及保持电容线42的电位会上升，而与此电容结合的半导体层14的电位也会上升。从该状态下，例如保持电容线42放电。此种放电容易在与保持电容线42接近的V驱动电路130的图案间产生。由此，保持电容线42的电位急剧下降，而与此电容结合的半导体层14的电位也急剧下降。然后，在栅极线20与半导体层14间的栅极绝缘层66上产生极大的电位差，例如在图7中的A点，导致产生绝缘破坏或是绝缘泄漏不良。因此，在由完成后的液晶显示装置进行显示时，会产生线缺陷或点缺陷的显示不良的问题。
发明内容
因此，本发明为解决上述现有技术中的问题，如图1所示，其特征在于，使隔着栅极绝缘层66与TFT 10的栅极电极20电容结合的第1半导体层15，及保隔着栅极绝缘层66与持电容Csc的保持电容线42电容结合的第2半导体层16相互分开，并且由金属配线40将第1半导体层15与第2半导体层16连接起来。
即，现有例子中是使TFT 10的栅极电极20及保持电容线42两部分与1个半导体层14电容结合，相对于此，在本发明中则是使TFT 10的栅极电极20与第1半导体层15、保持电容Csc的保持电容线42与第2半导体层16分别电容结合，因此由该结合各半导体层的电位产生变化，结果在栅极绝缘层66不会产生大的电位差，从而可防止绝缘破坏或绝缘泄漏的发生。
该半导体装置的制造方法为，该半导体装置具有：形成在基板上的薄膜晶体管；以及与所述薄膜晶体管相邻接而形成，用以保持通过该薄膜晶体管所输入的电压的保持电容，其特征在于，
在所述基板上使相互分开的第1及第2半导体层相邻接而形成的步骤；
在所述第1及第2半导体层上形成绝缘层的步骤；
在所述第1半导体层上隔着所述绝缘层而形成栅极电极，在所述第2半导体层上隔着所述绝缘层而形成保持电容电极的步骤；
通过离子注入在所述第1半导体层内形成源极区域及漏极区域的步骤；
在整个平面上形成层间绝缘膜的步骤；
在所述第1及第2半导体层上分别形成第1及第2接触孔的步骤；以及隔着所述第1及第2接触孔形成用于连接所述第1及第2半导体层的金属配线的步骤。
附图说明
图1是表示本发明的实施方式的液晶显示装置的一个像素的平面构造的图。
图2是表示沿图1的X-X线位置的截面构造图。
图3是说明本发明的实施方式的液晶显示装置的制造方法的截面图。
图4是现有例子的液晶显示装置的构成图。
图5是表示现有例子的液晶显示的一个像素的背面平面构造图。
图6是表示沿图5的Y-Y线位置的截面构造图。
图7是说明现有例子的液晶显示装置的制造方法的截面图。
符号说明：10薄膜晶体管(TFT)；14半导体层；14c沟道区域；14d漏极区域；14s源极区域；15第1半导体层；15c沟道区域；15d漏极区域；15s源极区域；16第2半导体层；20栅极电极(栅极线)；22数据线；24像素电极；40金属配线；42保持电容电极(保持电容线)；43金属配线；66栅极绝缘层；68层间绝缘膜；72平坦化绝缘膜；100液晶面板(第1基板)；130垂直驱动电路(V驱动电路)；140水平驱动电路(H驱动电路)；200液晶；500第2基板C0、C1、C2、C3接触孔；Csc保持电容；LC液晶。
具体实施方式
其次，参照附图详细说明本发明的实施方式。此实施方式的液晶显示装置基本上与图4呈相同构成。图1是表示液晶显示装置的一个像素的平面图。此外，图2表示沿图1中X-X线的截面图。图1是从第1基板100的背面观看的平面图。图5及图6中相同的构成部分赋予同一符号，并省略其说明。
TFT 10的第1半导体层15(例如，多晶硅层)以2处与在行方向直线延伸的栅极线20相交叉的方式弯曲。在该2个交叉部分，在第1半导体层15上构成沟道区域15c。另外，栅极线20构成所谓的双栅极。在此，第1半导体层15对应图1中的折叠线P-P左右对称地折叠。
在栅极电极与沟道区域15c的间形成有栅极绝缘层66。第1半导体层15的漏极区域15d隔着在层间绝缘膜68与栅极绝缘层66形成的接触孔C0，而与朝列方向延伸的数据线22连接。
接着，TFT 10的源极区域15s隔着形成在层间绝缘膜68与栅极绝缘层66的接触孔C1，与金属配线43相连接。该金属配线43以与数据线22相同的层(例如，铝层)形成在层间绝缘膜68上。另外，该金属配线43隔着设置在平坦化绝缘膜72上的接触孔C2与上层的像素电极24相连接，该平坦化绝缘膜形成于金属配线43上。
另外，保持电容线42以与栅极线20相同的层(例如为钼膜、铬膜)构成，并朝行方向直线延伸。其次，保持电容线42隔着栅极绝缘层66而与同第1半导体层15相互分开的第2半导体层16重叠，该重叠部分构成保持电容Csc。
此外，第2半导体层16隔着形成在层间绝缘膜68与栅极绝缘层66的接触孔C3，与金属配线43相连接。换言之，第1半导体层15与第2半导体层16虽相互分开，但还是由金属配线43相连接。
图3是表示该液晶显示装置的制造过程的截面图。该图是沿图2的X-X线的截面图。参照图1～图3说明该液晶显示装置的制造方法。
首先，在第1基板100上，使相互分开的第1半导体层15及第2半导体层16相邻接而形成。在此步骤中，在第1基板100上形成例如非晶硅层，由激光退火处理将该层予以多结晶化之后，以图案化方式形成。
其次，在第1半导体层15及第2半导体层16上，通过例如CVD法而形成由SiO2层构成的栅极绝缘层66。然后，在第1半导体层15上隔着栅极绝缘层66而形成栅极电极20(栅极线)，并在第2半导体层16上隔着栅极绝缘层66而形成保持电容电极42(保持电容线)。在此步骤中，在栅极绝缘层66上形成钼膜或铬膜，并予以干式蚀刻，形成栅极电极20(栅极线)及保持电容电极42(保持电容线)。
其次，通过离子注入，在第1半导体层15内形成源极区域15s及漏极区域15d。在此，在所谓LDD构造的情况下，首先以栅极电极20为掩模进行离子注入而形成低浓度的源极区域及漏极区域，之后，在栅极电极20的侧壁形成侧壁间隔层(sidewall spacer)，而以栅极电极20及该侧壁间隔层为掩模进行离子注入，而形成高浓度的源极区域及漏极区域。
在上述干式蚀刻步骤及离子注入步骤中，静电虽会积存在栅极线20及保持电容线42，但在本发明中，由于分别使TFT 10的栅极电极20与第1半导体层15电容结合，及使保持电容Csc的保持电容线42与第2半导体层16电容结合，故会因为该结合而使各个半导体层的电位产生变化，因此，在栅极绝缘层66不会产生大的电位差，而可防止绝缘破坏或绝缘泄漏的发生。
例如，栅极线20及保持电容线42的电位会因静电而上升，而与其电容结合的第1半导体层15及第2半导体层16的电位也会上升。从这种状态下，使保持电容线42放电。由此，保持电容线42的电位会急剧下降，且与该保持电容丝42电容结合的第2半导体层16的电位也急剧下降。
但是，由于第1半导体层15与第2半导体层16相互分开，故第2半导体层16的电位不会降低。因此，在栅极绝缘层66不会产生大的电位差，从而可防止绝缘破坏或绝缘泄漏的发生。
另外，在整个平面形成层间绝缘膜68。然后，在第1半导体层15及第2半导体层16上分别形成第1接触孔C1及第3接触孔C3。其次，并隔着这些接触孔形成连接第1半导体层15及第2半导体层16的金属配线43。
再者，在整个面上形成平坦化绝缘膜72。接着，在金属配线43上形成第2接触孔C2，并隔着该第2接触孔C2而形成与金属配线43相连接的像素电极24。无论在上述层间绝缘膜68的形成步骤中或在接触孔的形成步骤中，在栅极线20及保持电容线42都会积存静电，但由与上述同样的构成，可防止栅极绝缘层66的绝缘破坏或绝缘泄漏的发生。
另外，如上所述，第1半导体层15相对于图1中的折叠线P-P折叠成左右对称。此为取得电荷蓄积的平衡，由此，可更为有效地防止栅极绝缘层66的绝缘破坏。
由此，容易产生栅极绝缘层66的静电破坏的步骤，是从栅极电极形成开始到接触孔形成结束，具体地说，在栅极电极20形成时、离子注入时、层间绝缘膜形成时、接触孔形成时，但本发明在作为消除这些步骤中的静电破坏的装置能发挥功效。
另外，在本实施方式中虽以液晶显示装置为例子予以说明，但本发明并不仅限于此，也可广泛适用在具有保持薄膜晶体管、以及保持通过该薄膜晶体管所供给的电压的保持电容的半导体装置上。例如，除了液晶显示装置之外，也可适用于具有驱动用薄膜晶体管和保持电容的有机EL显示装置上。
根据本发明，由于分别使薄膜晶体管的栅极电极与第1半导体层电容结合，且使保持电容的保持电容电极与第2半导体层电容结合，故会因为该结合而使各半导体层的电位产生变化，因此，在栅极绝缘层不会产生大的电位差，从而可防止绝缘破坏或绝缘泄漏的发生。

Claims (7)

1.一种半导体装置，其具有：形成在基板上的薄膜晶体管；以及与所述薄膜晶体管相邻接而形成，用以保持通过该薄膜晶体管所供给的电压的保持电容；其特征在于，
使隔着绝缘层与所述薄膜晶体管的栅极电极电容结合的第1半导体层、及隔着绝缘层与所述保持电容的保持电容电极电容结合的第2半导体层相互分开，并且由金属配线连接所述第1及第2半导体层。
2.根据权利要求1所述的半导体装置，其特征在于，所述金属配线为与像素电极相连接。
3.根据权利要求1所述的半导体装置，其特征在于，所述保持电容电极与所述栅极电极并行配置。
4.根据权利要求1、2、3的任一项所述的半导体装置，其特征在于，所述第1半导体层是以与所述栅极电极在处交叉的方式对称折叠。
5.根据权利要求1、2、3的任一项所述的半导体装置，其特征在于，所述薄膜晶体管具有p型沟道或n型沟道。
6.一种半导体装置的制造方法，该半导体装置具有：形成在基板上的薄膜晶体管；以及与所述薄膜晶体管相邻接而形成，用以保持通过该薄膜晶体管所输入的电压的保持电容，其特征在于，
在所述基板上使相互分开的第1及第2半导体层邻接形成的步骤；
在所述第1及第2半导体层上形成绝缘层的步骤；
在所述第1半导体层上隔着所述绝缘层而形成栅极电极，在所述第2半导体层上隔着所述绝缘层而形成保持电容电极的步骤；
通过离子注入在所述第1半导体层内形成源极区域及漏极区域的步骤；
在整个平面上形成层间绝缘膜的步骤；
在所述第1及第2半导体层上分别形成第1及第2接触孔的步骤；以及隔着所述第1及第2接触孔形成用于连接所述第1及第2半导体层的金属配线的步骤。
7.根据权利要求6所述的半导体装置的制造方法，其特征在于，还具有：在整个平面上形成平坦化绝缘膜的步骤；在所述金属配线上形成第3接触孔的步骤；以及隔着所述第3接触孔而形成与所述金属配线连接的像素电极的步骤。
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