CN1419279A - 半导体器件及其制造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 title claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 61
- 239000012535 impurity Substances 0.000 claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 229920005591 polysilicon Polymers 0.000 claims description 58
- 239000010408 film Substances 0.000 claims description 49
- 239000010409 thin film Substances 0.000 claims description 16
- 239000012528 membrane Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000013459 approach Methods 0.000 claims 2
- 238000010276 construction Methods 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 12
- 238000005530 etching Methods 0.000 description 3
- 238000010348 incorporation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910018594 Si-Cu Inorganic materials 0.000 description 1
- 229910008465 Si—Cu Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- -1 aluminium-silicon-copper Chemical compound 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
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Abstract
本发明提供了一种能够减少多晶硅薄膜电阻器的阻值变化的半导体器件。在本发明的半导体器件及其制造方法中,当形成多晶硅薄膜电阻器时,通过利用新技术确定掺入到多晶硅薄膜电阻器中的杂质的掺杂量来实现一个构造,以构成一个性能更优的半导体集成电路器件。
Description
技术领域
本发明涉及一种用于电子设备的半导体器件,特别是涉及包含电阻器的半导体器件及其制造方法。
技术背景
通常,用多晶硅薄膜制成的电阻器是这样制造的:将多晶硅薄膜沉淀在表面已经被氧化或者用类似的方法使其表面形成了绝缘薄膜的硅基片上,在多晶硅中掺入诸如二氟化硼或者磷的杂质,然后,使用光阻材料或者类似物质作为掩膜将多晶硅蚀刻成电阻器。图3是一个多晶硅薄膜电阻器的平面图。掺入多晶硅薄膜电阻器103的杂质数量是这样确定的:确定多晶硅薄膜电阻器的长度L101和宽度W102,然后利用多晶硅薄膜电阻器的长度L101,宽度W102和期望的电阻值进行计算。
然而,近些年,半导体器件需要高精度。使用常规制造方法制造的多晶硅薄膜电阻器涉及阻值的变化,这种方法阻碍了装有多晶硅薄膜电阻器的半导体器件性能的提高。特别是阻碍了如A/D转换器或者类似的装置中需要电阻器绝对值精确性的半导体器件的性能提高。
发明内容
本发明是考虑到上述问题而做出的,目的是提供一种解决上述问题半导体器件,它包括一个能够减少电阻值变化的高精度多晶硅薄膜电阻器,并且提供一种上述装置的制造方法。
为了实现上述目的,本发明提供了如下所述的装置。
本发明利用了一个使用杂质掺入量的装置,当制造多晶硅薄膜电阻器时该装置使掺入到多晶硅薄膜电阻器中的杂质掺入量近似于使薄膜电阻值变得最小的杂质掺入量。
如图1所示,作为本发明的试制结果,可以证实在某一杂质掺杂数量时多晶硅薄膜电阻器的薄膜电阻值达到最小值。存在关于杂质掺杂数量的薄膜电阻值最小值的事实意味着即使杂质掺杂数量在薄膜电阻值最小值附近变化,薄膜电阻值的变化也保持很小。
当杂质掺杂数量事先确定的情况下,为了获得一个多晶硅薄膜电阻器期望的电阻值,可以利用一个由如下公式所表述的关系式:
R=ρs×L/W
其中,
R表示多晶硅薄膜电阻器的电阻值,
ρs表示多晶硅薄膜电阻器的薄膜电阻值,
L表示多晶硅薄膜电阻器的长度,
以及
W表示多晶硅薄膜电阻器的宽度。
当杂质掺杂数量确定后,多晶硅薄膜电阻器的薄膜电阻值也可确定了。因此,为了获得多晶硅薄膜电阻器期望的电阻值,L/W,即多晶硅薄膜电阻器的长度和宽度可以被确定。
按照上述提到的结构,可以获得一个小变化的多晶硅薄膜电阻器。
附图说明在附图中,图1示出在多晶硅薄膜电阻器中薄膜电阻值与杂质掺杂数量的关系曲线图;图2A到2E是沿着图3中A-A’的方向的示意性断面图,其中,按照制造顺序示出多晶硅薄膜电阻器(本发明的实施例1);图3示出多晶硅薄膜电阻器的平面图。
具体实施方式
在下文中,将描述本发明的具体实施方式。
参考附图1将描述具体实施例1。
图1示出本发明的发明人的试制结果。它示出当二氟化硼以50KeV通过离子注入被掺入到厚度为1000A的多晶硅薄膜中时薄膜电阻值与杂质掺杂数量的关系曲线图。当二氟化硼的剂量为3.0×1015cm-2时,薄膜电阻值为最小值,0.4KΩ/方格(square)。因此,在二氟化硼以50KeV通过杂质掺杂被掺入形成多晶硅薄膜电阻器的情况下,二氟化硼的杂质掺杂数量被设为3.0×1015cm-2。
此时,如果要形成1KΩ的多晶硅薄膜电阻器,由于1K=0.4K×L/W,L/W以满足5∶2比率的条件被选择。例如,L/W被设为20/8或40/16。多晶硅薄膜电阻器按照这个实施例形成,使得电阻值小变化的多晶硅薄膜电阻器能够被制造。
当半导体器件在硅基片上被制造时,在很多情况下,大量的同样的半导体器件可以在相同的硅基片上被制造。在二氟化硼的杂质掺杂数量被设为3.0×1015cm-2的情况下,甚至二氟化硼的杂质掺杂数量按照推测在2.0×1015cm-2到4.0×1015cm-2的范围内变化,抑制多晶硅薄膜电阻器的薄膜电阻值在10%或者更少的范围内变化是可能的。
在下文中,将描述通过二氟化硼的离子注入的1KΩ的多晶硅薄膜电阻器的制造方法。
多晶硅薄膜电阻器的制造方法将使用相应于沿着图3中A-A’方向的断面图2A到2E进行描述。
如图2A所示,硅基片表面以8000A被氧化形成硅氧化薄膜2,然后,多晶硅薄膜3以大约0.1μm沉淀在其表面。
随后,在多晶硅薄膜3中,通过离子注入以能量为50KeV,掺杂数量为3.0×1015cm-2注入二氟化硼。
如图2B所示,沉淀在基片表面上的多晶硅薄膜3变成具有0.4KΩ/方格的薄膜电阻值的多晶硅薄膜(在掺入二氟化硼之后)5。
通过使用光刻蚀法,在多晶硅薄膜(在掺入二氟化硼之后)5上,将光阻材料4形成一个电阻器图案。图2C是一个示出在这个阶段的状态的断面图。此时,图案形成被完成使得多晶硅薄膜电阻器6的长度L为40μm,宽度为16μm。
图2D示出在多晶硅薄膜(在掺入二氟化硼之后)5上完成刻蚀,并且保护层被剥除后的状态。
此后,没有掺杂质的厚度为0.3μm的硅酸盐玻璃8(在下文中,用NSG薄膜表示)和厚度为0.5μm的硼磷硅酸盐玻璃7(在下文中,用BPSG薄膜表示)被沉淀,然后,以900℃进行退火,通过蚀刻形成一个引出一个电极的接触部分11。用于布线的金属,钛(Ti),锡(TiN),和铝—硅—铜(Al-Si-Cu)分别以厚度为0.05μm,0.15μm和0.9μm被沉淀。然后,形成布线图案完成布线。以1μm的厚度沉淀等离子体氮化物薄膜9形成保护薄膜,随后的步骤通过刻蚀形成一个衬垫部分引出一个电极从而完成多晶硅薄膜电阻器。图2E是一个在制造完成后沿着图3中A-A’线路的剖面图。
根据本发明,当多晶硅薄膜电阻器制造时,通过改变杂质的掺杂数量将薄膜电阻值的变化量抑制在一个最小值是可能的。多晶硅薄膜电阻的薄膜电阻值的变化被抑制在最小值,由此,能够提供出高精度的装有电阻器的半导体器件。
Claims (4)
1.一种包含多晶硅薄膜电阻器的半导体器件,多晶硅薄膜电阻器是通过掺入杂质到沉淀在半导体基片上的多晶硅薄膜中形成的,
其中,多晶硅薄膜电阻器具有一个以设定的参杂量掺入杂质的浓度,所设定的参杂量接近于使薄膜电阻值为最小的杂质掺杂量。
2.一种包含多晶硅薄膜电阻器的半导体器件的制造方法,其中多晶硅薄膜电阻器是通过掺入杂质到沉淀在半导体基片上的多晶硅薄膜中形成的,
包括一个在多晶硅薄膜电阻器中以设定的参杂量掺入杂质的步骤,所设定的参杂量接近于使得薄膜电阻值为最小的杂质掺杂量。
3.如权利要求1所述的半导体器件,包含一个通过掺入杂质到沉淀在硅基片上的多晶硅薄膜中而形成的多晶硅薄膜电阻器,其中,
多晶硅薄膜电阻器有一个能够获得理想电阻值的电阻器的长度和宽度。
4.如权利要求2所述的半导体器件的制造方法,其中包含一个通过掺入杂质到沉淀在硅基片上的多晶硅薄膜中而形成的多晶硅薄膜电阻器,
进一步包括一个形成拥有能够获得理想电阻值的电阻器的长度和宽度的多晶硅薄膜电阻器的步骤。
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Application Number | Priority Date | Filing Date | Title |
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JP2001291311A JP2003100879A (ja) | 2001-09-25 | 2001-09-25 | 半導体装置とその製造方法 |
JP291311/2001 | 2001-09-25 |
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CN1419279A true CN1419279A (zh) | 2003-05-21 |
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CN02160254A Pending CN1419279A (zh) | 2001-09-25 | 2002-09-25 | 半导体器件及其制造方法 |
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US (1) | US6750531B2 (zh) |
JP (1) | JP2003100879A (zh) |
KR (1) | KR101200617B1 (zh) |
CN (1) | CN1419279A (zh) |
SG (1) | SG106096A1 (zh) |
TW (1) | TW560004B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100409415C (zh) * | 2005-12-06 | 2008-08-06 | 上海华虹Nec电子有限公司 | 一种在集成电路中使用α多晶硅的方法 |
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US20040235258A1 (en) * | 2003-05-19 | 2004-11-25 | Wu David Donggang | Method of forming resistive structures |
KR101037813B1 (ko) * | 2009-09-15 | 2011-05-30 | 한상호 | 수유 가리개 |
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JPS6289341A (ja) * | 1985-10-15 | 1987-04-23 | Mitsubishi Electric Corp | マスタスライス方式大規模半導体集積回路装置の製造方法 |
US5494845A (en) * | 1993-08-17 | 1996-02-27 | Raytheon Company | Method of fabrication of bilayer thin film resistor |
US5495845A (en) * | 1994-12-21 | 1996-03-05 | Pyromid, Inc. | Compact outdoor cooking unit |
JPH10200066A (ja) * | 1996-12-29 | 1998-07-31 | Sony Corp | 半導体装置の製造方法 |
US5994210A (en) * | 1997-08-12 | 1999-11-30 | National Semiconductor Corporation | Method of improving silicide sheet resistance by implanting fluorine |
JP2000058755A (ja) * | 1998-06-02 | 2000-02-25 | Seiko Instruments Inc | 半導体装置とその製造方法 |
US6475400B2 (en) * | 2001-02-26 | 2002-11-05 | Trw Inc. | Method for controlling the sheet resistance of thin film resistors |
-
2001
- 2001-09-25 JP JP2001291311A patent/JP2003100879A/ja not_active Withdrawn
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2002
- 2002-09-17 US US10/245,410 patent/US6750531B2/en not_active Expired - Lifetime
- 2002-09-19 SG SG200205668A patent/SG106096A1/en unknown
- 2002-09-20 TW TW091121658A patent/TW560004B/zh not_active IP Right Cessation
- 2002-09-24 KR KR1020020057816A patent/KR101200617B1/ko active IP Right Grant
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN100409415C (zh) * | 2005-12-06 | 2008-08-06 | 上海华虹Nec电子有限公司 | 一种在集成电路中使用α多晶硅的方法 |
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US20030057519A1 (en) | 2003-03-27 |
JP2003100879A (ja) | 2003-04-04 |
KR20030027707A (ko) | 2003-04-07 |
KR101200617B1 (ko) | 2012-11-12 |
US6750531B2 (en) | 2004-06-15 |
SG106096A1 (en) | 2004-09-30 |
TW560004B (en) | 2003-11-01 |
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