CN1377077A - 半导体器件 - Google Patents
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Abstract
一种半导体器件,包括:安装板、通过附着到安装板上的连接焊球电连接到安装板上的封装、在封装上承载的半导体芯片和用于将半导体芯片上的连接端子与连接焊球电连接的连接焊丝,半导体芯片和连接焊球附着到带的一个表面上,所述带具有这样的形状,即弯折180°使带的附着有半导体芯片的表面基本上平行于带的附着有连接焊球的表面,其间插入了缓冲材料,用形成在带中的连接布线使焊丝和连接焊球彼此电连接。
Description
技术领域
本发明涉及半导体器件,更具体地说,涉及表面贴装的封装结构。
背景技术
安装半导体器件的模式包括引线插入型和表面贴装型,而且表面贴装型正成为高密度表面贴装的主流。
在各种表面贴装型的模式中,图4是显示将在下表面上具有多个网格焊球的BGA(网格焊球阵列)封装安装到安装板上的安装状态的截面图。
如图4所示,承载在BGA封装110上的半导体芯片114通过焊丝115和引线113电连接到网格焊球112。布线端子102设置在印刷电路板101的表面上。网格焊球112叠放在布线端子102上,然后通过加热使其熔融,从而将网格焊球112固定在布线端子102上。
然而,当印刷电路板101由于外力翘曲时,会出现BGA封装110的网格焊球112同布线端子102脱开的问题。
这是由于BGA封装110的刚度比印刷电路板101的刚度高的缘故,因此,BGA 110的变形不能够随着印刷电路板101而变形。
发明内容
本发明的目的是提供一种半导体器件,能够减少封装同印刷电路板脱开的现象。
本发明涉及的半导体器件包括:安装板、通过附着到安装板上的连接焊球电连接到安装板上的封装、在封装上承载的半导体芯片、和用于将半导体芯片上的连接端子与连接焊球电连接的连接焊丝,半导体芯片和连接焊球附着到带的一个表面上,所述带具有这样的形状,即弯折180°使带的附着有半导体芯片的表面基本上平行于带的附着有连接焊球的表面,其间插入了缓冲材料,用形成在带中的连接布线使焊丝和连接焊球彼此电连接。
附图的简要说明
通过下面结合附图对本发明的详细描述,本发明的上述和其它目的、特征和优点将变得更加明了。
图1A和1B是显示根据制造本发明的半导体器件的工艺步骤顺序的半导体器件的第一实施例的截面图;
图2是显示本发明的半导体器件的第二实施例的截面图;
图3是显示本发明的半导体器件的第二实施例的修改实施例的截面图;
图4是显示传统的半导体器件的截面图。
发明的详细描述
下面将参考图1A和1B描述本发明的半导体器件的第一实施例。图1A和1B是显示在穿过焊料球和布线端子的切面上的半导体封装和印刷电路板的截面图。图1A和1B还显示了第一实施例的制造工艺的工艺步骤。
提供在其上设有布线端子2的印刷电路板1、形成在挠性带11上的焊料球12和板布线13、附着在带11上的半导体芯片14、用于连接半导体芯片和板布线13的焊丝15和用于密封半导体芯片14和焊丝15的环氧树脂16。此时,焊料球12、板布线13、焊丝15和环氧树脂16都设置在带11的同一表面上。将带11分为半导体芯片14的区域和焊料球12的区域,而且提供其上没有形成部件的弯折区17,用于将带11的半导体芯片14的区域弯折到图中箭头所示的方向。
将形成在挠性带11上的焊料球12附着到设在印刷电路板1上的布线端子2上之后,用弯折区17作为弯折轴,按箭头所示的方向弯折带11。以便得到图中所示的截面。
在开始弯曲带11操作之前,将作为缓冲材料的硅树脂18粘附于带11的与其上设有焊料球12的表面相对的表面上(图1A)。
当进一步在箭头所示的方向弯折带11时,将带11的与其上设有半导体芯片14的表面相对的表面粘附于硅树脂18上(图1B)。
将带的承载半导体芯片14的区域和带的其上粘附有焊料球12的区域通过硅树脂18彼此粘附,但不直接粘附,从而可以缓解由于印刷电路板1的弯曲变形而导致的施加于半导体芯片侧的扭曲,并且可以防止故障的发生,例如焊丝的断裂和芯片的脱离。
下面将参考图2描述本发明的半导体器件的第二实施例。图2是显示本发明的半导体器件的第二实施例的截面图。
与第一实施例类似,焊料球12、板布线13、焊丝15和环氧树脂16都形成在挠性带11的同一表面上,通过弯折区17将带11分为半导体芯片14的区域和焊料球12的区域。
将形成在挠性带11上的焊料球附着于设置在印刷电路板1上的布线端子2上之后,以下列方式弯折带11,即在同一平面上带11的半导体芯片14的区域和带11的焊料球12的区域是不对准的,而保持弯折区域17的直线性。具体地说,弯折区域17的带上附着作为加强材料21的用于加强的树脂或金属(例如,铜),如图所示,这样形成了直线形的弯折区17。
此时,为了以可靠的方式将焊料球12附着到布线端子2上,用螺钉19将带11的附着有焊料球12的区域的周边固定到印刷电路板1上,螺钉19穿过带11到达印刷电路板1。
这样将带11分为半导体芯片区域和焊料球区域,其间插有直线形弯曲的弯曲区域17,所有的部件构成一个半导体单元10。
形成具有与半导体单元10的构成一样的另一个半导体单元20,半导体单元20与半导体单元10相邻。在印刷电路板1上以下列方式布置图中所示的半导体单元20,即将半导体单元20的带的焊料球区域定位在半导体单元10的下面。
因此,可以将印刷电路板上被半导体单元占据的区域限制到带的附着有焊料球的区域,这样对于在印刷电路板上高密度安装半导体单元是有利的。
作为第二实施例的修改实施例,如图3所示,可以在挠性带11的与其上形成有焊料球12的表面相对的表面上形成板布线13、焊丝15和环氧树脂16。
如上所述,在这样的实施例中,即半导体芯片和焊料球附着到挠性带的不同的区域,且带的半导体芯片区和焊料球区彼此重叠在相同的平面上,通过在带的半导体区和焊料球区之间插入作为缓冲材料的硅树脂,从而缓解了印刷电路板的扭曲对带的半导体芯片区的不良影响。
在另一个实施例中,半导体区和焊料球区彼此不重叠在相同的平面上,当在印刷电路板上安装形成在一个带上的多个半导体单元时,一个半导体单元的带的焊料球区与在同一平面内的相邻的半导体单元的带的半导体区重叠,从而可以在印刷电路板上高密度地集成半导体单元。
在根据本发明的半导体器件的实施例中,如已经描述了的,其中将半导体芯片和焊料球附着到挠性带的不同区域,且带的半导体区和带的焊料球区彼此重叠在同一平面内,通过在带的半导体区和焊料球区之间插入作为缓冲材料的硅树脂,缓解了印刷电路板的变形对带的半导体芯片区的负面影响。
在另一个实施例中,带的半导体区和焊料球区彼此不重叠在同一平面上,当在印刷电路板上安装形成在一个带上的多个半导体单元时,一个半导体单元的带的焊料球区与在同一平面内的相邻的半导体单元的带的半导体区重叠,从而可以在印刷电路板上高密度地集成半导体单元。
尽管已经参考具体实施例描述了本发明,但上面的描述并不意味着限定本发明。对于本领域技术人员来说,通过参考本发明的描述,对所公开的具体实施例作出的各种修改都是显而易见的。因此,所附的权利要求将覆盖任何修改或落入本发明的实际范围内的实施例。
Claims (7)
1.一种半导体器件,包括:安装板、通过附着到安装板上的连接焊球电连接到安装板上的封装,在封装上承载的半导体芯片和用于将半导体芯片上的连接端子与连接焊球电连接的连接焊丝,
半导体芯片和连接焊球附着到带的一个表面上,所述带具有这样的形状,即弯折180°使带的附着有半导体芯片的表面基本上平行于带的附着有连接焊球的表面,其间插入了缓冲材料,用形成在带中的连接布线使焊丝和连接焊球彼此电连接。
2.如权利要求1所述的半导体器件,其中所述缓冲材料是硅树脂。
3.一种半导体器件,包括:安装板,通过附着到安装板上的连接焊球电连接到安装板上的封装,在封装上承载的半导体芯片和用于将半导体芯片上的连接端子与连接焊球电连接的连接焊丝,
所述带以这样的方式弯曲,即带的具有封装的区域和带的具有连接焊球的区域在相对于安装板的表面的距离之间彼此面对,且基本上彼此平行,用形成在带中的连接布线使焊丝和连接焊球彼此电连接。
4.如权利要求3所述的半导体器件,其中半导体芯片和连接焊球附着在带的同一表面上。
5.如权利要求3所述的半导体器件,其中半导体芯片和连接焊球附着在带的不同表面上。
6.如权利要求3所述的半导体器件,其中在安装板上安装了多个半导体单元,每个单元都包括封装,连接焊球和带,并且将一个半导体单元的封装定位在与其相邻的另一个半导体单元的连接焊球上面。
7.如权利要求3所述的半导体器件,其中所述带的具有封装的区域和带的具有连接焊球的区域之间的区域附着了用于加强的树脂或金属,使其间的区域具有直线形。
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JP085789/2001 | 2001-03-23 | ||
JP2001085789A JP2002289741A (ja) | 2001-03-23 | 2001-03-23 | 半導体装置 |
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CN1377077A true CN1377077A (zh) | 2002-10-30 |
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Application Number | Title | Priority Date | Filing Date |
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CN02107972A Pending CN1377077A (zh) | 2001-03-23 | 2002-03-22 | 半导体器件 |
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US (1) | US20020135050A1 (zh) |
JP (1) | JP2002289741A (zh) |
KR (1) | KR20020075280A (zh) |
CN (1) | CN1377077A (zh) |
TW (1) | TW529137B (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
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CN101310380B (zh) * | 2005-11-15 | 2011-02-09 | 日本电气株式会社 | 半导体封装、电子部件、以及电子设备 |
JP4561729B2 (ja) | 2006-11-06 | 2010-10-13 | エプソンイメージングデバイス株式会社 | 電気光学装置及び電子機器 |
JP5028968B2 (ja) * | 2006-11-17 | 2012-09-19 | 日立電線株式会社 | 半導体装置、積層型半導体装置およびインターポーザ基板 |
US7833456B2 (en) * | 2007-02-23 | 2010-11-16 | Micron Technology, Inc. | Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece |
JP2010212273A (ja) * | 2009-03-06 | 2010-09-24 | Elpida Memory Inc | 半導体パッケージ用基板、該基板を用いた半導体パッケージ、および半導体パッケージ用基板の製造方法 |
US10090259B2 (en) * | 2015-12-26 | 2018-10-02 | Intel Corporation | Non-rectangular electronic device components |
-
2001
- 2001-03-23 JP JP2001085789A patent/JP2002289741A/ja not_active Abandoned
-
2002
- 2002-03-14 US US10/096,839 patent/US20020135050A1/en not_active Abandoned
- 2002-03-20 TW TW091105391A patent/TW529137B/zh active
- 2002-03-21 KR KR1020020015408A patent/KR20020075280A/ko not_active Application Discontinuation
- 2002-03-22 CN CN02107972A patent/CN1377077A/zh active Pending
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US20020135050A1 (en) | 2002-09-26 |
KR20020075280A (ko) | 2002-10-04 |
JP2002289741A (ja) | 2002-10-04 |
TW529137B (en) | 2003-04-21 |
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