CN1363958A - 氮化铝和氧化铝/氮化铝栅介质叠层场效应晶体管及形成方法 - Google Patents
氮化铝和氧化铝/氮化铝栅介质叠层场效应晶体管及形成方法 Download PDFInfo
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Abstract
本发明公开了一种结构(例如,场效应晶体管)和制作该结构的方法,该结构包括具有源区,漏区和这两者之间的沟道区的衬底,该结构还包括配置在沟道区上的绝缘层,和配置在绝缘层上的栅极,该绝缘层包括一个层,该层包括配置在沟道区上的氮化铝。
Description
技术领域
本发明主要涉及半导体器件，特别是场效应晶体管。
背景技术
目前，用于诸如晶体管的硅互补金属氧化物半导体(CMOS)器件的高介电常数栅极介质通常使用二氧化硅栅极介质。在可制造的器件中使用的其他栅极介质还包含作为栅极介质堆层的一部分的硅氮氧化合物层。随着CMOS器件的微型化，比例规律需要参数e/d同样减小，其中e和d分别为电介质层的介电常数和厚度。对于诸如二氧化硅的固定的栅极介质材料，其介电常数为3.8，因此它的厚度必须随着器件变小而减小。然而，在低于近似1.5-1.7纳米的物理厚度时，该层开始传输通过该层的不能接受的高数量电泄漏电流。
发明内容
考虑到常规方法和结构的前述和其他问题，本发明的目的之一在于提供一种方法和结构，其中一种薄的栅极介质被应用在诸如场发射晶体管的半导体器件中。
另一目的在于使用栅极介质而不是二氧化硅。
根据本发明的第一方面，场效应晶体管包括衬底，配置在沟道区上的绝缘层，和配置在绝缘层上的栅电极，该衬底包括源区，漏区和这两者之间的沟道区，该绝缘层包括一个层，该层包含配置在沟道区上的氮化铝。
根据另一方面，绝缘层还优选地包括配置在沟道区上的氧化铝、配置在氧化铝上面或下面的氮化铝的层。
根据另一方面，绝缘层还优选包括配置在沟道区上的二氧化硅、配置在二氧化硅上面或下面的氮化铝的层。
根据另一方面，绝缘层还优选地包括配置在沟道区上的氮化硅、配置在氮化硅上面或下面的氮化铝的层。
由此，本发明器件的结构优选包括至少一种电介质层(例如氮化铝)并且更优选包括两种电介质层，下面的层为氧化铝(或二氧化硅或氮化硅)而上面的层为氮化铝。这些材料可为无定形，或多晶，或单晶的。
通过多种技术中的任何一种，氧化铝和氮化铝优选地直接沉积在硅表面顶部上。
因此，本发明提供用于硅互补金属氧化物半导体(CMOS)晶体管的高介电常数栅极介质，其取代当前使用的二氧化硅栅极介质。这是由于下述原因发生的。如先前提及的，相应的比例参数为比率e/d，其中e为电介质介电常数，d为薄膜厚度。注意到在电介质为二氧化硅时，e被限制到3.8的低值。另一方面，氮化铝的介电常数至少近似在9-16的范围内。结果，对于氮化铝电介质层，物理厚度可至少高于二氧化硅层厚度的2.5倍并仍然保持相同的e/d比例。换句话说，二氧化硅薄膜和比二氧化硅薄膜厚2.5倍的氮化铝薄膜可为相互电等价的。然而，由于它的较高物理厚度，氮化铝层将比二氧化硅层传导低得多的漏电流。
结果，需要超薄栅极介质层的未来微型化晶体管可使用基于氮化铝的电介质，从而导致更小更快和低漏电流的器件。
较厚的物理层也防止通过电介质层的杂质和掺杂剂的扩散并且保护了下面的硅衬底。
附图说明
参考附图，通过下面详细描述本发明优选实施方案，将更好地理解前述的和另外的目的、方面和优点，其中：
图1示出了根据本发明的流程图；
图2示出了根据本发明通过图1的方法100产生的结构；
图3示出了对于本发明使用的氮化铝(氮化铝)和氧化铝/氮化铝电介质异质结构的电容/栅压曲线；
图4示出了对于本发明使用的两个样品(例如，氮化铝和氧化铝/氮化铝电介质异质结构)的电流密度曲线，和与常规结构中使用的二氧化硅的比较。
具体实施方式
现在参考附图，特别是图1-4，它们示出了根据本发明的方法和结构的优选实施方案。
优选实施方案
参考图1，该图示出了形成半导体器件的方法100，该半导体器件诸如多端器件，场效应晶体管，开关器件，放大器等。
在步骤101中，提供衬底101，该衬底具有源区102，漏区103，和形成在源和漏区之间的沟道区104。该衬底优选由硅等形成。
在步骤102中，选择性地氧化铝(氧化铝)层105(或二氧化硅或氮化硅)被沉积在源和漏区之间的沟道区上。再次，注意到氧化铝(或二氧化硅或氮化硅)105的形成是任选的。如果提供该层，氧化铝(或二氧化硅或氮化硅)的厚度优选在大约0.1nm至2.0nm范围内。
在步骤103中，氮化铝层106被沉积在氧化铝(或二氧化硅或氮化硅)(如果先前提供了)上。
如果先前没有沉积氧化铝(或二氧化硅或氮化铝)105，那么氮化铝106直接沉积在沟道上。注意到氧化铝的形成是任选的。氮化铝的厚度优选在大约0.1至大约10nm范围内。注意到如果在下面没有氧化铝层(或二氧化硅或氮化硅)，该厚度不需要变化。
在步骤104中，由金属或多晶硅形成的栅电极107被形成在氮化铝层的顶部上。
参考图2，该图示出了通过图1方法形成的器件的结构。如上所述，该结构包括至少一种电介质层(例如，氮化铝)或两种电介质层，下面一层为氧化铝上面一层为氮化铝。这些材料可为或者无定形，或者多晶，或者单晶的。在该实施方案中描述的情形是上层为氮化铝的情形。然而，可使这种情形相反，其中第一层为氮化铝，随之以二氧化硅或氧化铝或氮化硅。
示出的结构为标准的自调整场效应晶体管的结构。然而，这种晶体管的各种变体也可使用相同的异质结电介质。
如图2所示，氧化铝(或二氧化硅或氮化硅)和氮化硅被直接沉积在Si表面顶部。这可通过各种技术完成，包括超高真空物理气相沉积(UHVPVD)。
参考图3，提供了两种样品的电学结果(电容-电压，和电流-电压)并显示出电容确实存在。
也就是说，示出了形成的铝/氮化铝/硅(样品344)和铝/氮化铝/氧化铝/硅(样品345)电容器的电学结果。
对于样品344，氮化铝厚度估计为5nm，对于样品345，氧化铝厚度估计为4nm，并且氮化铝层估计为0.8nm。
C-V结果显示了对于样品344具有1.3nm等效厚度(等效于二氧化硅)和样品345具有1.5nm等效厚度的好的性能界面(本发明者还示证了大约0.9nm等效厚度的基于氮化铝的电介质薄膜，该厚度低于二氧化硅可接受的制作厚度)，在相同等效厚度下漏电流低于二氧化硅的漏电流7个数量级大小(对于样品345)，而对于样品344低于5个数量级的漏电流。
图4说明了本发明使用的这两种样品(例如，氮化铝和氧化铝/氮化铝电介质异质结构)的电流密度曲线，和与常规结构中使用的二氧化硅的比较。
因此，图4表明利用本发明的这两种样品可得到非常低的电流密度，特别是与常规栅极介质(诸如二氧化硅)相比。
因此，如上所述，根据本发明独特和并非显而易见的方面，本发明器件优选包括至少一种电介质层(例如，氮化铝)并且更优选包括两种电介质层，其中一层为氮化铝另一层为氧化铝、二氧化硅或氮化硅。
因此，本发明提供用于硅互补金属氧化物半导体(CMOS)晶体管的高介电常数栅极介质，其取代常规的二氧化硅(或二氧化硅或氮化硅)栅极介质。这就导致一种电学上较薄的栅极介质，使保持低漏电流并提供了具有良好电特征的与Si的界面。
尽管根据几个优选实施方案描述了本发明，但是本领域中的技术人员将认识到在附加的权利要求书的精神和范围内可进行修改来实现本发明。
Claims (27)
1.一种场效应晶体管，包括：
衬底，它包括源区，漏区，和这两者之间的沟道区；
绝缘层，配置在所述沟道区上，所述绝缘层包括一个层，该层包括配置在所述沟道区上的氮化铝；以及
栅电极，配置在所述绝缘层上。
2.如权利要求1的晶体管，其特征在于所述绝缘层还包括：
配置在所述沟道区上的氧化铝层，所述氮化铝配置在所述氧化铝之上。
3.如权利要求1的晶体管，其特征在于所述绝缘层还包括：
配置在所述沟道区上的氧化铝层，所述氮化铝配置在所述氧化铝的下面。
4.如权利要求1的晶体管，其特征在于所述绝缘层还包括：
配置在所述沟道区上的二氧化硅层，所述氮化铝配置在所述二氧化硅之上。
5.如权利要求1的晶体管，其特征在于所述绝缘层还包括：
配置在所述沟道区上的二氧化硅层，所述氮化铝配置在所述二氧化硅的下面。
6.如权利要求1的晶体管，其特征在于所述绝缘层还包括：
配置在所述沟道区上的氮化硅层，所述氮化铝配置在所述氮化硅之上。
7.如权利要求1的晶体管，其特征在于所述绝缘层还包括：
配置在所述沟道区上的氮化硅层，所述氮化铝配置在所述氮化硅的下面。
8.如权利要求2的晶体管，其特征在于所述绝缘层还包括：
配置在所述氮化铝上的二氧化硅层。
9.如权利要求2的晶体管，其特征在于所述绝缘层还包括配置在所述氧化铝下面的二氧化硅层。
10.如权利要求4的晶体管，其特征在于所述绝缘层还包括：
配置在所述氮化铝之上的二氧化硅层。
11.如权利要求1的晶体管，其特征在于所述绝缘层还包括：
配置在所述氧化铝之上的氧化铝层。
12.如权利要求11的晶体管，其特征在于所述绝缘层还包括：
配置在所述氧化铝之上的二氧化硅层。
13.如权利要求12的晶体管，其特征在于所述绝缘层还包括：
配置在所述二氧化硅之上的硅层。
14.一种场效应晶体管，包括：
衬底，它包括源区，漏区，和这两者之间的沟道区；
绝缘层，配置在所述沟道区上，所述绝缘层包括第一层和第二层，第一层包括配置在所述沟道区上的氧化铝，第二层包括配置在所述第一层上的氮化铝；以及
栅电极，配置在所述绝缘层上。
15.一种半导体器件，包括：
衬底，它包括源区，漏区，和这两者之间的沟道区；
绝缘层，配置在所述沟道区上，所述绝缘层包括一个层，该层包括配置在所述沟道区上的氮化铝；以及
栅电极，配置在所述绝缘层上。
16.如权利要求15的半导体器件，其特征在于所述器件包括场效应晶体管。
17.一种多端器件，包括：
衬底，它包括源区，漏区，和这两者之间的沟道区；
绝缘层，配置在所述沟道区上，所述绝缘层包括一个层，该层包括配置在所述沟道区上的氮化铝；以及
栅电极，配置在所述绝缘层上。
18.如权利要求17的多端器件，其特征在于所述器件包括场效应晶体管。
19. 一种形成场效应晶体管的方法，包括：
形成包括源区，漏区，和这两者之间的沟道区的衬底；
将绝缘层配置在所述沟道区上，所述绝缘层包括一个层，该层包括配置在所述沟道区上的氮化铝；以及
将栅电极配置在所述绝缘层上。
20.如权利要求19的方法，其特征在于所述绝缘层还包括：
配置在所述沟道区上的氧化铝层，所述氮化铝配置在所述氧化铝之上。
21.如权利要求19的晶体管，其特征在于所述绝缘层还包括：
配置在所述沟道区上的氧化铝层，所述氮化铝配置在所述氧化铝的下面。
22.如权利要求19的方法，其特征在于所述绝缘层还包括：
配置在所述沟道区上的二氧化硅层，所述氮化铝配置在所述二氧化硅之上。
23.如权利要求19的晶体管，其特征在于所述绝缘层还包括：
配置在所述沟道区上的二氧化硅层，所述氮化铝配置在所述二氧化硅的下面。
24.如权利要求19的方法，其特征在于所述绝缘层还包括：
配置在所述沟道区上的氮化硅层，所述氮化铝配置在所述氮化硅之上。
25.如权利要求19的晶体管，其特征在于所述绝缘层还包括：
配置在所述沟道区上的氮化硅层，所述氮化铝配置在所述氮化硅的下面。
26.一种形成半导体器件的方法，包括：
形成包括源区，漏区，和这两者之间的沟道区的衬底；
将绝缘层配置在所述沟道区上，所述绝缘层包括一个层，该层包括配置在所述沟道区上的氮化铝；以及
将栅电极配置在所述绝缘层上。
27.如权利要求1的晶体管，其特征在于所述绝缘层还包括二氧化硅、氧化铝、和氮化硅中的至少一个。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/755,164 | 2001-01-08 | ||
| US09/755,164 US6831339B2 (en) | 2001-01-08 | 2001-01-08 | Aluminum nitride and aluminum oxide/aluminum nitride heterostructure gate dielectric stack based field effect transistors and method for forming same |
Publications (2)
| Publication Number | Publication Date |
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| CN1363958A true CN1363958A (zh) | 2002-08-14 |
| CN1176498C CN1176498C (zh) | 2004-11-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB01130281XA Expired - Lifetime CN1176498C (zh) | 2001-01-08 | 2001-12-29 | 氮化铝和氧化铝/氮化铝栅介质叠层场效应晶体管及形成方法 |
Country Status (4)
| Country | Link |
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| US (2) | US6831339B2 (zh) |
| JP (1) | JP2002246594A (zh) |
| CN (1) | CN1176498C (zh) |
| TW (1) | TW594992B (zh) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1319128C (zh) * | 2003-01-02 | 2007-05-30 | 上海华虹（集团）有限公司 | 一种高介电栅堆层结构 |
Families Citing this family (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040224459A1 (en) * | 1999-07-07 | 2004-11-11 | Matsushita Electric Industrial Co., Ltd. | Layered structure, method for manufacturing the same, and semiconductor element |
| US6891231B2 (en) | 2001-06-13 | 2005-05-10 | International Business Machines Corporation | Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier |
| JP4095326B2 (ja) * | 2002-03-29 | 2008-06-04 | 株式会社東芝 | 半導体装置の製造方法及び半導体装置 |
| JP4507232B2 (ja) * | 2003-03-24 | 2010-07-21 | ローム株式会社 | 半導体装置の製造方法 |
| TWI313060B (en) | 2003-07-28 | 2009-08-01 | Japan Science & Tech Agency | Feild effect transisitor and fabricating method thereof |
| JP2005064317A (ja) * | 2003-08-18 | 2005-03-10 | Semiconductor Leading Edge Technologies Inc | 半導体装置 |
| US6921691B1 (en) * | 2004-03-18 | 2005-07-26 | Infineon Technologies Ag | Transistor with dopant-bearing metal in source and drain |
| US20050258491A1 (en) * | 2004-05-14 | 2005-11-24 | International Business Machines Corporation | Threshold and flatband voltage stabilization layer for field effect transistors with high permittivity gate oxides |
| US7105889B2 (en) * | 2004-06-04 | 2006-09-12 | International Business Machines Corporation | Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics |
| US8178902B2 (en) | 2004-06-17 | 2012-05-15 | Infineon Technologies Ag | CMOS transistor with dual high-k gate dielectric and method of manufacture thereof |
| US8399934B2 (en) * | 2004-12-20 | 2013-03-19 | Infineon Technologies Ag | Transistor device |
| US7592678B2 (en) | 2004-06-17 | 2009-09-22 | Infineon Technologies Ag | CMOS transistors with dual high-k gate dielectric and methods of manufacture thereof |
| JP2006032552A (ja) * | 2004-07-14 | 2006-02-02 | Toshiba Corp | 窒化物含有半導体装置 |
| US7344934B2 (en) | 2004-12-06 | 2008-03-18 | Infineon Technologies Ag | CMOS transistor and method of manufacture thereof |
| US7160781B2 (en) * | 2005-03-21 | 2007-01-09 | Infineon Technologies Ag | Transistor device and methods of manufacture thereof |
| US7361538B2 (en) * | 2005-04-14 | 2008-04-22 | Infineon Technologies Ag | Transistors and methods of manufacture thereof |
| US8188551B2 (en) | 2005-09-30 | 2012-05-29 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
| US20070052036A1 (en) * | 2005-09-02 | 2007-03-08 | Hongfa Luan | Transistors and methods of manufacture thereof |
| US20070052037A1 (en) * | 2005-09-02 | 2007-03-08 | Hongfa Luan | Semiconductor devices and methods of manufacture thereof |
| TWI262550B (en) * | 2005-10-14 | 2006-09-21 | Ind Tech Res Inst | Element with a low temperature poly-Si film, method of direct poly-Si deposition at low temperature and inductively-coupled plasma chemical vapor deposition |
| JP2007103814A (ja) * | 2005-10-07 | 2007-04-19 | Sharp Corp | 窒化物半導体発光素子およびその製造方法 |
| US7510943B2 (en) * | 2005-12-16 | 2009-03-31 | Infineon Technologies Ag | Semiconductor devices and methods of manufacture thereof |
| US20080050898A1 (en) * | 2006-08-23 | 2008-02-28 | Hongfa Luan | Semiconductor devices and methods of manufacture thereof |
| CN101950757A (zh) * | 2010-07-13 | 2011-01-19 | 中国科学院上海微系统与信息技术研究所 | 基于soi衬底的高介电常数材料栅结构及其制备方法 |
| US8492247B2 (en) * | 2010-08-17 | 2013-07-23 | International Business Machines Corporation | Programmable FETs using Vt-shift effect and methods of manufacture |
| JP6042160B2 (ja) * | 2012-10-03 | 2016-12-14 | 東京エレクトロン株式会社 | 成膜方法及び成膜装置 |
| US20190386124A1 (en) * | 2018-06-13 | 2019-12-19 | Purdue Research Foundation | Mos devices with increased short circuit robustness |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4151537A (en) * | 1976-03-10 | 1979-04-24 | Gte Laboratories Incorporated | Gate electrode for MNOS semiconductor memory device |
| US4097314A (en) | 1976-12-30 | 1978-06-27 | Rca Corp. | Method of making a sapphire gate transistor |
| JPS54144183A (en) * | 1978-05-01 | 1979-11-10 | Handotai Kenkyu Shinkokai | Insulated gate type electrostatic induction transistor and semiconductor integrated circuit |
| JPS61140175A (ja) * | 1984-12-13 | 1986-06-27 | Semiconductor Energy Lab Co Ltd | 被膜作製方法 |
| JPS61140176A (ja) | 1984-12-13 | 1986-06-27 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
| KR100571071B1 (ko) | 1996-12-04 | 2006-06-21 | 소니 가부시끼 가이샤 | 전계효과트랜지스터및그제조방법 |
| US7115461B2 (en) * | 1997-07-24 | 2006-10-03 | Texas Instruments Incorporated | High permittivity silicate gate dielectric |
| US6020024A (en) | 1997-08-04 | 2000-02-01 | Motorola, Inc. | Method for forming high dielectric constant metal oxides |
| KR100567299B1 (ko) | 1998-03-27 | 2006-04-04 | 텍사스 인스트루먼츠 인코포레이티드 | 반도체 장치 및 반도체 장치의 게이트 구조 제조 방법 |
| JP3513018B2 (ja) | 1998-06-30 | 2004-03-31 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US6274510B1 (en) * | 1998-07-15 | 2001-08-14 | Texas Instruments Incorporated | Lower temperature method for forming high quality silicon-nitrogen dielectrics |
| JP3148982B2 (ja) | 1998-11-11 | 2001-03-26 | 工業技術院長 | 半導体装置及びその製造方法 |
| JP3443589B2 (ja) | 1999-03-01 | 2003-09-02 | 独立行政法人産業技術総合研究所 | 半導体装置の製造方法 |
| US6407435B1 (en) * | 2000-02-11 | 2002-06-18 | Sharp Laboratories Of America, Inc. | Multilayer dielectric stack and method |
| US6544906B2 (en) * | 2000-12-21 | 2003-04-08 | Texas Instruments Incorporated | Annealing of high-k dielectric materials |
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2001
- 2001-01-08 US US09/755,164 patent/US6831339B2/en not_active Expired - Lifetime
- 2001-12-21 JP JP2001388832A patent/JP2002246594A/ja active Pending
- 2001-12-28 TW TW090132766A patent/TW594992B/zh not_active IP Right Cessation
- 2001-12-29 CN CNB01130281XA patent/CN1176498C/zh not_active Expired - Lifetime
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1319128C (zh) * | 2003-01-02 | 2007-05-30 | 上海华虹（集团）有限公司 | 一种高介电栅堆层结构 |
Also Published As
| Publication number | Publication date |
|---|---|
| US6831339B2 (en) | 2004-12-14 |
| TW594992B (en) | 2004-06-21 |
| US20020090773A1 (en) | 2002-07-11 |
| JP2002246594A (ja) | 2002-08-30 |
| US20050087821A1 (en) | 2005-04-28 |
| US7488640B2 (en) | 2009-02-10 |
| CN1176498C (zh) | 2004-11-17 |
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