CN1328342A - Process for preparing diode with ceramic substrate and crystal grain structure - Google Patents
Process for preparing diode with ceramic substrate and crystal grain structure Download PDFInfo
- Publication number
- CN1328342A CN1328342A CN 00109203 CN00109203A CN1328342A CN 1328342 A CN1328342 A CN 1328342A CN 00109203 CN00109203 CN 00109203 CN 00109203 A CN00109203 A CN 00109203A CN 1328342 A CN1328342 A CN 1328342A
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- Prior art keywords
- conductor
- crystal grain
- ceramic substrate
- diode
- grainiess
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- 239000000758 substrate Substances 0.000 title claims abstract description 47
- 239000000919 ceramic Substances 0.000 title claims abstract description 28
- 239000013078 crystal Substances 0.000 title claims description 57
- 238000004519 manufacturing process Methods 0.000 title description 6
- 239000004020 conductor Substances 0.000 claims abstract description 54
- 239000000463 material Substances 0.000 claims abstract description 14
- 238000005245 sintering Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 30
- 239000003292 glue Substances 0.000 claims description 10
- 238000001704 evaporation Methods 0.000 claims description 9
- 230000008020 evaporation Effects 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 7
- 230000001681 protective effect Effects 0.000 claims description 6
- 239000006071 cream Substances 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 4
- 230000009286 beneficial effect Effects 0.000 claims description 3
- 238000001514 detection method Methods 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 claims description 2
- 210000004027 cell Anatomy 0.000 claims description 2
- 238000003486 chemical etching Methods 0.000 claims description 2
- 238000000227 grinding Methods 0.000 claims description 2
- 238000007373 indentation Methods 0.000 claims description 2
- 230000009467 reduction Effects 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 claims 1
- 238000012856 packing Methods 0.000 abstract description 5
- 239000011248 coating agent Substances 0.000 abstract 2
- 238000000576 coating method Methods 0.000 abstract 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000003723 Smelting Methods 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000009514 concussion Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
A technology for preparing diodes with ceramic substrate and grain structure includes such steps as cutting slots on substrate structure to form several hundreds units, forming lower conductor on each unit, printing resistance, adhering diode grains, coating packing material on substrate, exposing the top of grain, printing or coating upper conductor to connect to the edge of each unit, breaking the substrate to become strips, forming terminals on its sides, sintering, breaking the strip to become single units, attaching the weldable tin on terminal surface, electric test and package.
Description
The present invention relates to a kind of diode fabricating method, refer in particular to and a kind ofly can produce sheet shape diode in a large number, and the tool ceramic substrate that can reduce cost and the diode fabricating method of grainiess.
At present, low-power surface adhesion type diode package all based on tubular form, is column diode package (MELF).Yet this type of method for packing still has following shortcoming:
1, mechanization pickup, put in the manufacturing process such as part, bonding, welding, be difficult for operation, efficient is poor, hinders a large amount of productions.
2, column diode package particularly more has the problem of thermal coefficient of expansion to exist, and promptly it does not match with the circuit substrate thermal coefficient of expansion, pipe component is ruptured or opens circuit because of loose contact, causes the reliability of product poor.
Main purpose of the present invention provides the diode fabricating method of a kind of tool ceramic substrate and grainiess.
The present invention makes dissected valley to form hundreds of unit on board structure, each unit on board structure forms lower floor's conductor, the crystal grain of printing resistance body and adhesion diode is on board structure, on board structure, be coated with cover closing material, again through processing, crystal grain top salient point is revealed, print or plate layer conductor and form top conductor to be connected to the edge of each unit at the top of crystal grain salient point, the fragility jackknifing that utilizes substrate is body into strips, form terminal in its side,, utilize the fragility of substrate to become single again with automechanism jackknifing through thermal sintering, but the metal that adheres to solderability is in terminal surfaces, through electrical detection and packing.
Main effect of the present invention is: sheet shape diode reliability height, the cost made are low, and the tool productivity effect.
It below is description of drawings of the present invention.
Fig. 1 is a flow chart of the present invention.
Fig. 2 is the board structure schematic side view that dissected valley is arranged of the present invention.
Fig. 3 is the board structure schematic perspective view that dissected valley is arranged of the present invention.
Fig. 4 forms the schematic side view of lower floor's conductor at unit printing conductive cream or evaporation for the present invention.
Fig. 5 forms the schematic top plan view of lower floor's conductor at unit printing conductive cream or evaporation for the present invention.
Fig. 6 prints or plate resistance body for the present invention between the conductor on the board structure schematic side view.
Fig. 7 prints or plate resistance body for the present invention between the conductor on the board structure schematic top plan view
Fig. 8 prints protective material for the present invention on resistance body schematic side view.
Fig. 9 prints protective material for the present invention on resistance body schematic top plan view.
Figure 10 is the schematic side view of the radium-shine correction resistance of the present invention.
Figure 11 is the schematic top plan view of the radium-shine correction resistance of the present invention.
Figure 12 is the schematic side view of the present invention with the bonding crystal grain of conductive paste.
Figure 13 is the schematic top plan view of the present invention with the bonding crystal grain of conductive paste
Figure 14 is the schematic side view of lining crystal grain protection glue
Figure 15 is the schematic top plan view of lining crystal grain protection glue
The schematic side view that Figure 16 exposes electrode for the present invention
The schematic top plan view that Figure 17 exposes electrode for the present invention
Figure 18 forms the schematic side view of top conductor to the edge of each unit for the present invention in printing of the top of diode salient point or evaporation conductor.
Figure 19 forms the schematic top plan view of top conductor to the edge of each unit for the present invention in printing of the top of diode salient point or evaporation conductor.
Figure 20 is be covered the up schematic side view of insulation protection glue of the present invention.
Figure 21 is be covered the up schematic top plan view of insulation protection glue of the present invention.
Figure 22 marks the schematic side view of polarity and text printout for the present invention.
Figure 23 marks the schematic top plan view of polarity and text printout for the present invention.
Figure 24 is a full wafer substrate of the present invention jackknifing schematic perspective view into strips.
Figure 25 is a full wafer substrate of the present invention jackknifing schematic top plan view into strips.
Figure 26 adheres to the schematic side view that conductive paste or conductor form terminal for the present invention in both sides.
Figure 27 adheres to the schematic top plan view that conductor paste or conductor form terminal for the present invention in both sides.
Figure 28 becomes single schematic perspective view for jackknifing of the present invention.
Figure 29 becomes single schematic top plan view for jackknifing of the present invention.
But Figure 30 adheres to the solderability metal for the present invention in terminal surfaces schematic side view.
But Figure 31 adheres to the solderability metal for the present invention in terminal surfaces schematic top plan view.
Figure 32 adopts the schematic diagram of vibrating disc for the present invention.
Illustration is implemented in action when Figure 33 adopts vibrating disc for the present invention.
Figure 34 is positioned over embodiment schematic diagram under the crystal grain for the present invention with resistance body.
Figure 35 singly deposits the enforcement schematic diagram of crystal grain for the present invention.
Figure 36 is a die array part embodiment schematic diagram of the present invention.
Describe the present invention below in conjunction with accompanying drawing.
Flow chart of the present invention, as shown in Figure 1, its manufacture method is as follows:
First step: see also Fig. 2, Fig. 3, dissected valley (11) that go up to make del at ceramic substrate (1) is to form hundreds of unit, and this dissected valley (11) not only helps jackknifing, also can residual more conductor area when sliver.
Second step: see also Fig. 4, Fig. 5, each cell surface in substrate (1) forms lower floor's conductor (2) with printed conductor cream or evaporation.
Third step: see also Fig. 6, Fig. 7, between lower floor's conductor (2) of each unit in substrate (1), print or plate the resistance body (3) of suitable resistance.
The 4th step: see also Fig. 8, Fig. 9, be covered with protective material (4), so that protection resistance body (3) and be beneficial to the radium-shine finishing of next step on resistance body (3) surface.
The 5th step: see also Figure 10, Figure 11, if institute's resistance of the resistance body of printing (3) and expection error is arranged the time, can do correction by radium-shine reduction resistance body (3) one-tenth one breach (31).
The 6th step: see also Figure 12, Figure 13, crystal grain (as diode, light-emitting diode etc.) (5) bottom surface (52) is adhered on lower floor's conductor (2) with conductive paste (glue) (51).
The 7th step: see also Figure 14, Figure 15, for protection crystal grain (5), so be covered with cover closing material (53) up.
The 8th step: see also Figure 16, Figure 17, utilize grinding, radium-shine or chemical etching again, the top salient point (54) on the crystal grain (5) is revealed;
The 9th step: see also Figure 18, Figure 19, printing or evaporation conductor be at the top salient point (54) of crystal grain (5), and be connected to the edge of each unit, to form top conductor (6).
The tenth step: see also Figure 20, Figure 21, up with insulation protection glue (7) lining.
The 11 step: see also Figure 22, Figure 23, utilize printing ink or radium-shine indentation, polarity and literal (71) are labeled in protection glue (7) surface.
The 12 step: see also Figure 24, Figure 25, utilize the fragility and the dissected valley (11) of substrate (1) itself, through automechanism jackknifing body (12) into strips.
The 13 step: see also Figure 26, Figure 27, enclose conductor paste or conductor in strip shape body (12) side and form terminal (8), through thermal sintering.
The 14 step: see also Figure 28, Figure 29, utilize the fragility and the dissected valley (11) of substrate (1) itself, strip shape body (12) jackknifing is become the diode of single (13) through automechanism.
The 15 step: see also Figure 30, Figure 31, but the metal (81) of enclosing solderability in case the oxidation of not-go-end sub-surface, and increases solderability in terminal (8).
The 16 step: through electrical detection and packing.
See also Figure 32, shown in Figure 33, in the 6th step, can cooperate a parallel-moving type vibrating disc (9) that crystal grain (5) bottom surface (52) is correctly adhered on lower floor's conductor (2), and vibrating disc (9) has up big and down small stepped filling perforation (91), filling perforation (91) can supply the salient point (54) of crystal grain (5) to insert down, the top then can supply crystal grain (5) body to insert, to form inversion state; Promptly utilize specific vibration frequency, top salient point (54) crystal grain (5) is down moved than bottom surface (52) crystal grain (5) down is very fast, cause fall within parallel-moving type vibrating disc (9) filling perforation (91) crystal grain (5) bottom surface (52) up, be beneficial to crystal grain (5) bottom surface (52) and correctly adhere on lower floor's conductor (2).It is because have the crystal grain (5) of salient point (54), constituted by semiconductor that forms main body and the metal Base Material that forms salient point, add that its outward appearance is made up of the cuboid of body and the semicircle point of salient point (54), die based on material and apparent size under the difference on physical characteristic shows, can utilize oscillator to import suitable kinetic energy into, by its physical characteristic difference, the salient point (54) of crystal grain (5) is arranged down, crystal grain (5) moves forward simultaneously, enter in the smelting tool, crystal grain (5) orientation that can reach in the tool this moment is all identical, in order to carrying out crystal grain bonding (Die Mounted) in a large number.
See also shown in Figure 34ly, reach compact purpose, the 6th step can be replaced with the following step, be about to conductor (32) and be printed on lower floor's conductor (2) and the protective material (4), and this crystal grain (5) is arranged on the conductor (32) for making finished product.
See also shown in Figure 35ly,, then the three～five step can be omitted, make its only individualism one single die (5) if do not adopt resistance body (3).
Seeing also shown in Figure 36ly, is the schematic diagram that forms die array (Array), that is, above-mentioned the three～five step is omitted, and in the 14 step, strip shape body (12) jackknifing one-tenth is contained the die array of several unit; This substrate (1) can be made groove (14) in advance, forms terminal (8) in the side with convenient the 13 step; Simultaneously, wherein the crystal grain of unit (5) still can be resistor, capacitor or inductor except diode, promptly mixes into multiple combination with the need, and is arranged in the die array group body that contains several crystal grain.
By above-mentioned explanation, the following advantage of the true tool of the present invention as can be known:
1, be to belong to that present industry is unique can produce chip diode in a large number.
2 and to make efficient high, unit platform output hourly can reach about 200,000, and for having into most The product of this advantage.
3, this structure and manufacture method are the breakthrough invention of industry, and invention can ensure industrial competitiveness by this.
4, product has high reliability, because of the crystal grain contact of diode is bonding with conductive materials, is the contact contact of non-glass tube (MELF) and existing diode adopts.
5, can directly take out crystal grain from wafer by the automation board is adhered on the substrate or utilizes the concussion dish once to arrange whole crystal grain thereon.
6, unitary package can contain many crystal grain, forms the group body of die array, and crystal grain can be diode, resistor, electric capacity or inductance, and convenience and efficient when using to increase are made higher surcharge.
7, can be in same manufacture process, produce one fixedly crystal grain and resistance body in packing.
Claims (21)
1, the diode fabricating method of a kind of tool ceramic substrate and grainiess is characterized in that: make dissected valley to form hundreds of unit on ceramic substrate; Each cell surface on substrate forms lower floor's conductor; Be adhered on lower floor's conductor with the bottom surface of conductive paste crystal grain; Cover closing material is covered above lower floor's conductor; Crystal grain top salient point is revealed; Salient point is connected with conductor on the crystal grain top, and is connected to the edge of each unit, to form top conductor; Lining insulation protection glue above top conductor; At protection glue surface mark polarity or literal; Utilize the fragility and the dissected valley of substrate itself, whole jackknifing is body into strips; Form terminal in the strip shape body side; Utilize the fragility and the dissected valley of substrate itself, strip shape body jackknifing is become single diode.
2, the diode fabricating method of described tool ceramic substrate of claim 1 and grainiess, it is characterized in that: above-mentioned crystal grain also can be light-emitting diode.
3, the diode fabricating method of described tool ceramic substrate of claim 1 and grainiess, it is characterized in that: the dissected valley of substrate is a del.
4, the diode fabricating method of described tool ceramic substrate of claim 1 and grainiess is characterized in that: lower floor's conductor is to form with printed conductor cream.
5, the diode fabricating method of described tool ceramic substrate of claim 1 and grainiess, it is characterized in that: lower floor's conductor is to form with evaporation.
6, the diode fabricating method of described tool ceramic substrate of claim 1 and grainiess; it is characterized in that: after forming lower floor's conductor; the resistance body of suitable resistance is set between lower floor's conductor of each unit that can be in substrate; at the surface-coated protective material of resistance body, so make the diode that contains resistance body again.
7, the diode fabricating method of described tool ceramic substrate of claim 6 and grainiess is characterized in that: resistance body is to form with printing.
8, as the diode fabricating method of tool ceramic substrate as described in the claim 6 and grainiess, it is characterized in that: resistance body is to form with evaporation.
9, the diode fabricating method of described tool ceramic substrate of claim 6 and grainiess is characterized in that: can utilize the method for radium-shine reduction, form a breach of revising resistance body on resistance body.
10, the diode fabricating method of described tool ceramic substrate of claim 1 and grainiess is characterized in that: when the crystal grain bottom surface is bonded in lower floor's conductor, can cooperate a parallel-moving type vibrating disc that the crystal grain bottom surface is correctly adhered on lower floor's conductor; Promptly be to utilize specific vibration frequency, salient point crystal grain down in top comparatively fast moved than bottom surface crystal grain down, cause fall within the filling perforation of parallel-moving type vibrating disc the crystal grain bottom surface up, be beneficial to the crystal grain bottom surface and correctly adhere on lower floor's conductor.
11, the diode fabricating method of described tool ceramic substrate of claim 10 and grainiess, it is characterized in that: vibrating disc has can make crystal grain form inversion state, up big and down small stepped filling perforation, filling perforation can be inserted for the salient point of crystal grain down, and the top then can be inserted for the crystal grain body.
12, the diode fabricating method of described tool ceramic substrate of claim 1 and grainiess; it is characterized in that: replace with the following step with the step on conductive paste lower floor's conductor that the crystal grain bottom surface of diode is bonding; be about to conductor and be printed on lower floor's conductor and the protective material, and this crystal grain is arranged on the conductor.
13, the diode fabricating method of described tool ceramic substrate of claim 1 and grainiess is characterized in that: when crystal grain top salient point is manifested, can adopt modes such as grinding, radium-shine or chemical etching.
14, the diode fabricating method of described tool ceramic substrate of claim 1 and grainiess, it is characterized in that: when on lower floor's conductor, being covered cover closing material, can avoid on the salient point of crystal grain top, covering cover closing material, so that the crystal grain salient point reveals naturally, can omit the step that crystal grain top salient point is manifested.
15, the diode fabricating method of described tool ceramic substrate of claim 1 and grainiess is characterized in that: top conductor is to adopt printing or evaporation mode that conductor is connected with at crystal grain top salient point to form.
16, the diode fabricating method of described tool ceramic substrate of claim 1 and grainiess is characterized in that: when the protection glue surface, is to adopt modes such as printing ink or radium-shine indentation with polarity and label character.
17, the diode fabricating method of described tool ceramic substrate of claim 1 and grainiess is characterized in that: when forming terminal in the strip shape body side, be to adopt mode at strip shape body side attachment conductor paste or conductor to form terminal, again through thermal sintering.
18, the diode fabricating method of described tool ceramic substrate of claim 1 and grainiess is characterized in that: also can form the die array structure; That is, after the strip shape body side forms terminal, strip shape body jackknifing is become to contain the die array of several unit.
19, the diode fabricating method of described tool ceramic substrate of claim 18 and grainiess, it is characterized in that: the crystal grain of every unit is except diode, still can be resistor, capacitor or inductor, promptly mix into multiple combination with the need, and be arranged in the simple grain array that contains several crystal grain.
20, the diode fabricating method of described tool ceramic substrate of claim 1 and grainiess is characterized in that: after strip shape body jackknifing being become single diode, but the metal that still can adhere to solderability is in terminal surfaces.
21, the diode fabricating method of described tool ceramic substrate of claim 20 and grainiess is characterized in that: but after terminal surfaces is adhered to the metal of solderability, still can adopt electrical detection and packaging and other steps.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 00109203 CN1133205C (en) | 2000-06-13 | 2000-06-13 | Process for preparing diode with ceramic substrate and crystal grain structure |
| HK02102598.0A HK1041105B (en) | 2000-06-13 | 2002-04-08 | Encapsulation method for element having ceramic baseplate and grain structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 00109203 CN1133205C (en) | 2000-06-13 | 2000-06-13 | Process for preparing diode with ceramic substrate and crystal grain structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1328342A true CN1328342A (en) | 2001-12-26 |
| CN1133205C CN1133205C (en) | 2003-12-31 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 00109203 Expired - Lifetime CN1133205C (en) | 2000-06-13 | 2000-06-13 | Process for preparing diode with ceramic substrate and crystal grain structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN1133205C (en) |
| HK (1) | HK1041105B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100438078C (en) * | 2004-07-05 | 2008-11-26 | 广东风华高新科技股份有限公司 | Thick film chip diode and its manufacturing method |
| CN105632946A (en) * | 2015-12-25 | 2016-06-01 | 南通富士通微电子股份有限公司 | Jig for package structure and production method of package structure |
| CN113853365A (en) * | 2019-05-20 | 2021-12-28 | 罗杰斯德国有限公司 | Method for producing a metal-ceramic substrate and metal-ceramic substrate produced by said method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007056890A1 (en) * | 2005-11-16 | 2007-05-24 | Tak Cheong Electronics (Shanwei) Co., Ltd. | Surface mounting plastic packaging diode and manufacture method of the same |
-
2000
- 2000-06-13 CN CN 00109203 patent/CN1133205C/en not_active Expired - Lifetime
-
2002
- 2002-04-08 HK HK02102598.0A patent/HK1041105B/en not_active IP Right Cessation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100438078C (en) * | 2004-07-05 | 2008-11-26 | 广东风华高新科技股份有限公司 | Thick film chip diode and its manufacturing method |
| CN105632946A (en) * | 2015-12-25 | 2016-06-01 | 南通富士通微电子股份有限公司 | Jig for package structure and production method of package structure |
| CN105632946B (en) * | 2015-12-25 | 2018-09-28 | 通富微电子股份有限公司 | For the jig of encapsulating structure and the preparation method of encapsulating structure |
| CN113853365A (en) * | 2019-05-20 | 2021-12-28 | 罗杰斯德国有限公司 | Method for producing a metal-ceramic substrate and metal-ceramic substrate produced by said method |
Also Published As
| Publication number | Publication date |
|---|---|
| HK1041105A1 (en) | 2002-06-28 |
| HK1041105B (en) | 2004-04-30 |
| CN1133205C (en) | 2003-12-31 |
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Owner name: GUAN BAO TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: XU SHENGXIONG Effective date: 20080516 |
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Effective date of registration: 20080516 Address after: Taipei County of Taiwan Province Patentee after: Crown Polytron Technologies Inc Address before: Taipei County of Taiwan Province Patentee before: Xu Shengxiong |
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| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: LIZ Electronics (Kunshan) Co., Ltd. Assignor: Crown Polytron Technologies Inc Contract fulfillment period: 2008.12.1 to 2013.11.30 Contract record no.: 2009990000926 Denomination of invention: Process for preparing diode with ceramic substrate and crystal grain structure Granted publication date: 20031231 License type: Exclusive license Record date: 20090817 |
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| LIC | Patent licence contract for exploitation submitted for record |
Free format text: EXCLUSIVE LICENSE; TIME LIMIT OF IMPLEMENTING CONTACT: 2008.12.1 TO 2013.11.30; CHANGE OF CONTRACT Name of requester: LIZHI ELECTRONICS( KUNSHAN ) CO., LTD. Effective date: 20090817 |
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| CX01 | Expiry of patent term |
Granted publication date: 20031231 |
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| CX01 | Expiry of patent term |