CN102569272B - Multilayer spacer type IC (Integrated Circuit) chip stacked package of substrate and production method of package - Google Patents

Multilayer spacer type IC (Integrated Circuit) chip stacked package of substrate and production method of package Download PDF

Info

Publication number
CN102569272B
CN102569272B CN201110455062.8A CN201110455062A CN102569272B CN 102569272 B CN102569272 B CN 102569272B CN 201110455062 A CN201110455062 A CN 201110455062A CN 102569272 B CN102569272 B CN 102569272B
Authority
CN
China
Prior art keywords
chip
partition
bonding
insulating cement
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201110455062.8A
Other languages
Chinese (zh)
Other versions
CN102569272A (en
Inventor
郭小伟
朱文辉
慕蔚
王永忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tianshui Huatian Technology Co Ltd
Huatian Technology Xian Co Ltd
Original Assignee
Tianshui Huatian Technology Co Ltd
Huatian Technology Xian Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tianshui Huatian Technology Co Ltd, Huatian Technology Xian Co Ltd filed Critical Tianshui Huatian Technology Co Ltd
Priority to CN201110455062.8A priority Critical patent/CN102569272B/en
Publication of CN102569272A publication Critical patent/CN102569272A/en
Application granted granted Critical
Publication of CN102569272B publication Critical patent/CN102569272B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Wire Bonding (AREA)

Abstract

The invention discloses a multilayer spacer type IC (Integrated Circuit) chip stacked package of a substrate and a production method of the package. The package comprises a BT (Bismaleimide Triazine) substrate, wherein at least two IC chips are bonded onto a carrier of the BT substrate, all the IC chips are stacked and bonded in sequence, a bonding pad on each IC chip is connected with a bonding pad on the BT substrate through a bonding wire, a plastic package body is fixedly packaged on the BT substrate, and a spacer is bonded between every two adjacent IC chips. The production method comprises the steps of: thinning and scribing wafers and the spacers, bonding the IC chips onto the carrier of the BT substrate, then bonding the spacers onto the IC chips, and bonding the IC chips onto the spacers again to make the stacking layer number meet a use requirement, wherein the processes of baking, plasma cleaning and pressure welding are needed once each IC chip is bonded; and then bonding the IC chips continuously, and performing subsequent procedures by adopting the prior art to prepare the multilayer spacer type IC chip stacked package of the substrate with the required layer number. According to the package disclosed by the invention, the height of the bonding wire is not influenced, and the heat radiation and insulation performances of the chips are improved.

Description

A kind of multilayer spacer-type IC chip stacked packaging piece and production method thereof of substrate
Technical field
The invention belongs to electronic information Element of automatic control manufacturing technology field, relate to a kind of IC chip integrated circuit packaging part, be specifically related to a kind of multilayer spacer-type IC chip stacked packaging piece of substrate, the invention still further relates to a kind of production method of this stack package.
Background technology
Along with the growth of the electronic device of less, lighter and more powerful all kinds of mobile phone market expanded demand and palmtop PC (PAD), more miniaturization of Electronic Encapsulating Technology, multi-purpose research and development are promoted, stacked package has been to meet less, lighter, the multi-purpose a kind of important technical of product, and more and more obtaining each encapsulation corporate client's attention, all kinds of mobile phone digital cameras, various smart card and portable instrument are the applications of stacked package product.The multifunction technology of mobile phone has promoted again fast development and the skill upgrading of stacked package.
At present, stacked package is all directly IC chip to be carried out stacking bondingly by adhesive sheet, and impact connects the height of the bonding line of IC chip and carrier pad, and the insulation property between adjacent chips are bad, also have influence on the heat radiation of chip.
Summary of the invention
In order to overcome above-mentioned problems of the prior art, the object of this invention is to provide a kind of multilayer spacer-type IC chip stacked packaging piece of substrate, bonding line height meets the requirements, the insulation property of chip chamber and the heat dispersion of chip.
Another object of the present invention is to provide a kind of production method of multilayer spacer-type IC chip stacked packaging piece of aforesaid substrate.
For achieving the above object, the technical solution adopted in the present invention is, a kind of multilayer spacer-type IC chip stacked packaging piece of substrate, comprise BT substrate, on the carrier of BT substrate, be bonded with at least two IC chips, all IC chips stack gradually stickup, and the pad on each IC chip is connected with the pad on BT substrate by bonding line, on BT substrate, be sealed with plastic-sealed body, between adjacent two IC chips, be pasted with partition.
Another technical scheme of the present invention is, a kind of production method of multilayer spacer-type IC chip stacked packaging piece of aforesaid substrate is specifically carried out according to the following steps:
Step 1: wafer attenuate and Wafer Dicing and partition attenuate and partition scribing
For 3 layers of spacer-type IC chip stacked packaging piece: wafer attenuate final thickness is 100 μ m, and the wafer after attenuate is carried out to scribing;
Partition adopts single-chip: in the time that single-chip is used for 3 layers of stack package, the final thickness after single-chip attenuate is 110 μ m ± 10 μ m; In the time that single-chip is used for 5 layers of stack package, the final thickness after single-chip attenuate is 75 μ m; In the time that single-chip is used for more than 5 layers stack package, the final thickness after single-chip attenuate is 50 μ m;
When partition adopts microcrystalline glass or potsherd, thickness customizes as required, does not need attenuate;
Step 2: upper core, cleaning, pressure welding
For 3 layers of spacer-type IC chip stacked packaging piece:
Insulating cement or conducting resinl on putting on the carrier of BT substrate, by bonding to an IC chip and carrier, and adopt anti-absciss layer baking process to carry out 175 DEG C of bakings by this insulating cement or conducting resinl; After baking, carry out plasma cleaning, then from the pad of an IC chip to first substrate pad routing, formation camber is no more than the first key zygonema of 110 μ m, then, pastes successively the first partition and the 2nd IC chip on an IC chip:
If adopt insulating cement to paste the first partition and the 2nd IC chip, on an IC chip, put insulating cement, the first partition after scribing is placed on an IC chip, make the first partition and an IC die bonding by insulating cement, do not toast; Then, on the first partition, put insulating cement, the 2nd IC chip be placed on the first partition, by insulating cement make the 2nd IC chip and the first partition bonding, send baking; The thickness of twice bonding insulating cement is 20 μ m～30 μ m; Plasma cleaning, then from the pad of the 2nd IC chip to first substrate pad routing, formation camber is no more than the second bonding line of 110 μ m;
If adopt glue film to paste the first partition and the 2nd IC chip, will be placed on an IC chip with the first partition of glue film, make the first partition by glue film and an IC die bonding, do not toast; Again the 2nd IC chip with glue film is placed on the first partition, makes the 2nd IC chip and the first partition bonding; Then at the temperature of 150 DEG C, toast; Plasma cleaning, then from the pad of the 2nd IC chip to first substrate pad routing, formation camber is no more than the second bonding line of 110 μ m;
For 5 layers of spacer-type IC chip stacked packaging piece:
Adopt the upper core method of 3 layers of spacer-type IC chip stacked packaging piece on carrier, to paste an IC chip, pressure welding first key zygonema, stickup the first partition and the 2nd IC chip, pressure welding the second bonding line, then paste the second partition and the 3rd IC chip:
If adopt insulating cement to paste the second partition and the 3rd IC chip, on the 2nd IC chip, put insulating cement, the second partition is placed on this insulating cement, make the second partition and the 2nd IC die bonding, do not toast; Insulating cement on putting on the second partition, is placed on the 3rd IC chip on this insulating cement, makes the 3rd IC chip and the second partition bonding; Baking at 175 DEG C, plasma cleaning; From the pad of the 3rd IC chip to first substrate pad routing, formation camber is no more than the 3rd bonding line of 120 μ m again; The thickness of the insulating cement of twice bonding use is 20 μ m～30 μ m.
If adopt glue film to paste the second partition and the 3rd IC chip, will be placed on the 2nd IC chip with the second partition of glue film, make the second partition and the 2nd IC die bonding; Again the 3rd IC chip with glue film is placed on the second partition, makes the 3rd IC chip and the second partition bonding; Anti-absciss layer baking at 150 DEG C of temperature; Plasma cleaning; From the pad of the 3rd IC chip to first substrate pad routing, formation camber is no more than the 3rd bonding line of 120 μ m again;
For more than 5 layers spacer-type IC chip stacked packaging piece
On 5 layers of spacer-type IC chip stack package, on the basis of core, paste partition and IC chip:
If adopt insulating cement to paste partition and IC chip, on the 3rd IC chip, put insulating cement, partition is placed on this insulating cement, make this partition and the 3rd IC die bonding, do not toast; Then on partition, put insulating cement, IC chip is placed on this insulating cement, make IC chip and this partition bonding, then adopt the baking process identical with 5 layers of spacer-type IC chip stack package to toast, after baking, carry out plasma cleaning; After cleaning, from the pad of this IC chip to first substrate pad routing, formation camber is no more than the bonding line of 120 μ m; The rest may be inferred, stacking more multi-layered IC chip;
If adopt glue film to paste partition and IC chip, will be placed on the partition of glue film on the 3rd IC chip, this partition, by glue film and the 3rd IC chip attach, does not toast; The IC chip with glue film is placed on this partition, this IC chip is bonding by glue film and partition again, at 150 DEG C of temperature, toasts, and roasting plant is identical with 5 layers of spacer-type IC chip stack package with other baking process; After baking, carry out plasma cleaning; After cleaning, from the pad of this IC chip to first substrate pad routing, formation camber is no more than the bonding line of 120 μ m; According to said method, stacking more multi-layered IC chip;
Step 3: plastic packaging
Select low water absorption (water absorption rate≤0.25%), low stress (coefficient of expansion α 1≤ 1), the length of flow environmental protection plastic packaging material that is 70cm～120cm, use full-automatic encapsulation system and the anti-warpage technique of ultrathin encapsulation, carry out erosion control silk, anti-warpage and anti-absciss layer plastic packaging, obtain semi-finished product framework;
Step 4: solidify afterwards
At the temperature of 150 DEG C to after the semi-finished product framework of step 3 solidify 5h;
Step 5: plant ball and Reflow Soldering
Adopt existing common BGA Package to plant ball and reflow soldering process is planted ball and Reflow Soldering;
Step 6: clean
Adopt the cleaning of existing common BGA Package to clean;
Step 7: print
Adopt the printing technique of existing common BGA Package to print;
Step 8: products of separated
Use the technique cutting and separating product of existing common BGA Package cutting and separating;
Step 9: test
Product to cutting and separating is tested;
Step 10: inspection
The product having tested is tested, reject substandard product;
Step 11: packaging warehouse-in
Pack, put in storage by the requirement of common BGA packages packaging warehouse-in.
Size, the thickness of the stacking multiple IC chip sizes used of packaging part of the present invention are basic identical, between adjacent two IC chips, be provided with partition, height between these adjacent two IC chips is increased, for bonding line provides enough spaces, not only solve the height problem of bonding line, and be beneficial to the heat radiation of IC chip; , make because partition adopts non electrically conductive material meanwhile, further improved the insulation property of adjacent two IC chip chambers.
Brief description of the drawings
Fig. 1 is the structural representation of three layers of spacer-type stack package in stack package of the present invention.
Fig. 2 is the structural representation of five layers of spacer-type stack package in stack package of the present invention.
In figure, 1. carrier, 2. the first adhesive sheet, 3. an IC chip, 4. the second adhesive sheet, 5. first key zygonema, 6. the first partition, 7. first substrate pad, 8. the 2nd IC chip, 9. the second bonding line, 10. the 3rd adhesive sheet, 11. plastic-sealed bodies, 12. second substrate pads, 13. salient points, 14. scolders, 15. tin balls, 16.BT substrate, 17. the 4th adhesive sheets, 18. second partitions, 19. the 5th adhesive sheets, 20. the 3rd IC chips, 21. the 3rd bonding lines.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
As shown in Figure 1, the structure of three layers of spacer-type stack package in stack package of the present invention, comprise BT substrate 16, on the carrier 1 of BT substrate 16, be pasted with an IC chip 3, the one IC chip 3 is bonding with carrier 1 by the first adhesive sheet 2, is pasted with the first partition 6, the first partitions 6 bonding by the second adhesive sheet 4 and an IC chip 3 on an IC chip 3, on the first partition 6, be pasted with the 2nd IC chip 8, the two IC chips 8 bonding by the 3rd adhesive sheet 10 and the first partition 6; Above BT substrate 16, be provided with first substrate pad 7, first substrate pad 7 is connected with the second substrate pad 12 that is arranged at BT substrate 16 bottom surfaces, and second substrate pad 12 is provided with salient point (UBM) 13, and salient point 13 is welded with tin ball 15 by scolder 14; The one IC chip 3 is connected with first substrate pad 7 by first key zygonema 5, and the 2nd IC chip 8 is connected with first substrate pad 7 by the second bonding line 9.On BT substrate 16, be sealed with plastic-sealed body 11; Above carrier 1, BT substrate 16 above, the first adhesive sheet 2, an IC chip 3, the second adhesive sheet 4, the first partition 6, the 3rd adhesive sheet 10, the 2nd IC chip 8, first substrate pad 7, first key zygonema 5 and the second bonding line 9 be all packaged in plastic-sealed body 11, and form circuit entirety.Plastic-sealed body 11 has played protection and supporting role to an IC chip 3, first key zygonema 5, the 2nd IC chip 8 and the second bonding line 9.First substrate pad 7, an IC chip 3, first key zygonema 5, the 2nd IC chip 8, the second bonding line 9, second substrate pad 12, salient point (UBM) 13, scolder 14 and tin ball 15 have formed power supply and the signalling channel of circuit.
As shown in Figure 2, the structure of five layers of spacer-type stack package in stack package of the present invention, comprise BT substrate 16, on the carrier 1 of BT substrate 16, be bonded with an IC chip 3, the one IC chip 3 is bonding with carrier 1 by the first bonding die glue 2, is bonded with the first partition 6, the first partitions 6 bonding by the second adhesive sheet 4 and an IC chip 3 on an IC chip 3, on the first partition 6, be bonded with the 2nd IC chip 8, the two IC chips 8 bonding by the 3rd adhesive sheet 10 and the first partition 6; On the 2nd IC chip 8, be bonded with the second partition 18, the second partitions 18 bonding by the 4th adhesive sheet 17 and the 2nd IC chip 8, on the second partition 18, be bonded with the 3rd IC chip 20, the three IC chips 20 bonding by the 5th adhesive sheet 19 and the second partition 18; Above BT substrate 16, be provided with first substrate pad 7, first substrate pad 7 is connected with the second substrate pad 12 that is arranged at BT substrate 16 bottom surfaces, and second substrate pad 12 is provided with salient point (UBM) 13, and salient point 13 is welded with tin ball 15 by scolder 14; The one IC chip 3 is connected with first substrate pad 7 by first key zygonema 5, and the 2nd IC chip 8 is connected with first substrate pad 7 by the second bonding line 9, and the 3rd IC chip 20 is connected with first substrate pad 7 by the 3rd bonding line 21.On carrier 1 and BT substrate 16, be sealed with plastic-sealed body 11; Above carrier 1, BT substrate 14 above, the first adhesive sheet 2, an IC chip 3, the second adhesive sheet 4, the first partition 6, the 3rd adhesive sheet 10, the 2nd IC chip 8, the 4th adhesive sheet 17, the second partition 18, the 5th adhesive sheet 19, the 3rd IC chip 20, first substrate pad 7, first key zygonema 5, the second bonding line 9 and the 3rd bonding line 21 be all packaged in plastic-sealed body 11, and form circuit entirety.Plastic-sealed body 11 has played protection and supporting role to an IC chip 3, first key zygonema 5, the 2nd IC chip 8, the second bonding line 9, the 3rd IC chip 20 and the 3rd bonding line 21.First substrate pad 7, an IC chip 3, first key zygonema 5, the 2nd IC chip 8, the second bonding line 9, the 3rd IC chip 20, the 3rd bonding line 21, second substrate pad 12, salient point 13, scolder 14 and tin ball 15 have formed power supply and the signalling channel of circuit.
The first adhesive sheet 2 adopts insulating cement or conducting resinl, when IC chip has heat radiation or uses conducting resinl when power requirement, when IC chip uses insulating cement during without heat radiation or power requirement; The second adhesive sheet 4 adopts insulating cement or glue film; The 3rd adhesive sheet 10 adopts insulating cement or glue film; The first adhesive sheet 17 adopts insulating cement or glue film; The 5th adhesive sheet 19 adopts insulating cement or glue film; It is between neighbouring two-layer IC chip, to occur unwanted conducting in order to prevent that the first adhesive sheet 2, the second adhesive sheet 4, the 3rd adhesive sheet 10, the 4th adhesive sheet 17 and the 5th adhesive sheet 19 adopt insulating cement or glue film.
BT substrate 16 is a kind of Multi-stacking compaction formula seamless link wiring boards, the insulating material isolation that parts and parts arrange by interlayer and interlayer and with interlayer, so there is carrier 1 on BT substrate 16, carrier 1 is the position of bonding IC chip, it is pad that the BT substrate 16 of carrier 1 surrounding is provided with golden finger, and the pad on IC chip is connected by the golden finger realization on bonding line and BT substrate 16 and circuit and extraneous electricity, signal.
The first partition 6 adopts single-chip, microcrystalline glass or potsherd, and the second partition 18 adopts single-chip, microcrystalline glass or potsherd.The cost of microcrystalline glass is minimum, and potsherd cost is the highest, but potsherd is applicable to heat radiation and power package; When actual use, the first partition 6 and the second partition 18 adopt single-chip simultaneously, or adopt microcrystalline glass simultaneously, or adopt potsherd simultaneously.The size of the first partition 6 and the second partition 18 is less than the size of the two IC chips that are adjacent, and does not affect the IC of lower floor chip routing, this adjacent two layers IC chip in the same size or approaching.The size of partition is than the little 0.5mm～1.2mm of the size of IC chip.
The encapsulation number of plies of this packaging part is 2n+1, and n is partition number, and chip-count is n+1; Work as n=1, partition number is 1 o'clock, and chip-count is 2, and it is the packing forms of two-layer IC chip and one deck partition that the formation number of plies is 3 layers; Work as n=2, partition number is 2 o'clock, and chip-count is 3, and form the number of plies being 5 layers is the packing forms of three layers of IC chip and two-layer partition; In the time that partition number is n (n > 2), chip-count is n+1, and forming the number of plies is that 2n+1 is the packing forms of n+1 layer chip and n layer partition.More than 5 layers packaging part is on the basis of 5 layers of partition encapsulation, increases by 2 layers at every turn, and one deck partition and one deck IC chip increase one deck bonding line and two-layer insulating cement simultaneously, or two-layer glue film increases one deck bonding line and two-layer glue film.
Size, the thickness of the stacking multiple IC chip sizes used of packaging part of the present invention are basic identical, in order to solve the height problem of bonding wire and the problem of chip chamber insulation or heat radiation, between adjacent two IC chips, are provided with one deck partition.According to the difference of the application function of chip (common, heat radiation or power), partition can adopt three kinds of materials, the first is common single-chip, the second is microcrystalline glass, the third is potsherd, and wherein potsherd thermal diffusivity is good, the packaging part that is mainly used in power circuit and has heat radiation to require, but material price is higher, adopt customization; Microcrystalline glass is the most cheap, adopts outsourcing customization; The convenient processing of single-chip, thickness and size can be controlled, and the front back side of scribing glue diaphragm in advance.
Package structure of the present invention is rationally simple, has the distinguishing features such as anti-layering, anti-friendship silk, good heat dissipation (ceramic partition), test yield height, is suitable for the encapsulation of high density thin space product.
The production procedure of above-mentioned packaging part is as follows:
1) 3 layers of spacer-type IC chip stacked packaging piece
Wafer attenuate, Wafer Dicing ,partition attenuate and partition scribing -go up for the first time core (conducting resinl or insulating cement) and baking -plasma cleaning for the first time -pressure welding for the first time -bonding partition (insulating cement or glue film) -go up for the second time core (insulating cement or glue film) and baking -plasma cleaning for the second time -pressure welding for the second time -plastic packaging and rear solidifying -plant ball and Reflow Soldering -clean -print -products of separated -test -inspection -packaging -warehouse-in.
2) 5 layers of spacer-type IC chip stacked packaging piece
Wafer attenuate, Wafer Dicing, partition attenuate and partition scribing -go up for the first time core (conducting resinl or insulating cement) and baking -plasma cleaning for the first time -pressure welding for the first time -bonding partition (insulating cement or glue film) for the first time -go up for the second time core (insulating cement or glue film) and baking -plasma cleaning for the second time -pressure welding for the second time -bonding partition (insulating cement or glue film) for the second time -go up for the third time core (insulating cement or glue film) and baking -plasma cleaning for the third time -pressure welding for the third time -plastic packaging and rear solidifying -plant ball and Reflow Soldering -clean -print -products of separated -test -inspection -packaging -warehouse-in.
More than 5 layers spacer-type IC chip stacked packaging piece, adopt 3 layers and 5 layers of spacer-type IC chip stack package technology, on the 3rd IC chip 20, put adhesives (insulating cement or glue film), first place partition, then on this partition again on adhesives (insulating cement or glue film), place again IC chip and baking, the 4th plasma cleaning -the 4th pressure welding -plastic packaging and rear solidifying -plant ball and Reflow Soldering -clean -print -products of separated -test -inspection -packaging -warehouse-in.
The present invention also provides a kind of production method of above-mentioned packaging part, specific as follows:
Step 1: wafer attenuate and Wafer Dicing and partition attenuate and partition scribing
For 3 layers of stack package: chip original wafer thickness is 600 μ m ± 10 μ m, and wafer attenuate final thickness is 100 μ m; Corase grind scope is from original wafer thickness to final thickness+film thickness+50 μ m, corase grind speed 2 μ m/s～5 μ m/s; Fine grinding thickness range is from final thickness+film thickness+50 μ m to wafer final thickness+film thickness, and fine grinding speed 0.3 μ m/s～0.6 μ m/s, adopts and prevent chip warpage technique in wafer thinning process; The roughness Ra of the wafer after attenuate is 0.10mm～0.05mm,
Wafer after 8 inch and the attenuate below 8 inch adopts DISC 3350 or the scribing of double-pole scribing machine, obtains being with the separation IC chip of the zona that stretches tight; 8 inch adopt the scribing of A-WD-3000TXB scribing machine to the wafer after the attenuate of 12 inch; Obtain being with the separation IC chip of the zona that stretches tight; When scribing, adopt anti-fragment, Anti-cracking scribing process software controlling technique, scribing feed velocity≤10mm/s;
When partition adopts single-chip, the stacking number of plies that the final thickness of the single-chip of attenuate uses according to this partition is determined; In the time that single-chip is used for 3 layers of stack package, the final thickness of single-chip is 110 μ m ± 10 μ m; In the time that single-chip is used for 5 layers of stack package, the final thickness of single-chip is 75 μ m; In the time that single-chip is used for more than 5 layers stack package, the final thickness of single-chip is 50 μ m; In single-chip thinning process, corase grind scope is from single-chip original thickness to final single-chip thickness+film thickness+50 μ m, corase grind speed 3 μ m/s～5 μ m/s; Refine thickness range from final single-chip thickness+film thickness+50 μ m to final single-wafer thickness+film thickness, fine grinding speed 12 μ m/s～15 μ m/ s;
When partition adopts microcrystalline glass or potsherd, its thickness customizes as required, does not need attenuate;
Step 2: upper core, cleaning, pressure welding
For 3 layers of partition IC chip stacked packaging piece:
First on the carrier 1 of BT substrate 16, put the first adhesive sheet 2 by bonding die glue chip feeder, chip feeder automatic sucking the one IC chip 3 is placed on the first adhesive sheet 2, makes an IC chip 3 bonding with carrier 1; And adopting anti-absciss layer baking process to carry out 175 DEG C of bakings, roasting plant used and technique are with toasting after core on common pcb board; After baking, adopt existing method to carry out plasma cleaning, after cleaning, adopt gold thread or copper cash from the pad of an IC chip 3 to first substrate pad 7 routings, form first key zygonema 5, then, on an IC chip 3, paste successively the first partition 6 and the 2nd IC chip 8:
If adopt insulating cement paste the first partition 6 and the 2nd IC chip 8, on an IC chip 3, put insulating cement, the first partition 6 after scribing is placed on an IC chip 3, by insulating cement make the first partition 6 and an IC chip 3 bonding, do not toast; Then, on the first partition 6, put insulating cement, the 2nd IC chip 8 be placed on the first partition 6, by insulating cement make the 2nd IC chip 8 and the first partition 6 bonding; After having glued batch whole a 2nd IC chip 8, be transported to baking, the baking on the same IC chip 3 of baking process after core; The thickness of twice bonding insulating cement is 20 μ m～30 μ m; After baking, adopt existing method to carry out plasma cleaning, after cleaning, adopt gold thread or copper cash, from the pad of the 2nd IC chip 8 to first substrate pad 7 routings, form the second bonding line 9;
Paste the first partition 6 and the 2nd IC chip 8 if adopt glue film, use the chip feeder with core function on glue film, the semi-finished product BT substrate 16 of pressure welding first key zygonema 5 is served to this chip feeder, making the heating-up temperature of substrate according to the performance of glue film used is 120 DEG C～150 DEG C or higher, chip feeder is drawn and is placed on an IC chip 3 with the first partition 6 of glue film, make the first partition 6 bonding by glue film and an IC chip 3, do not toast; And then be that the 2nd IC chip 8 is placed on the first partition 6 by the IC chip with glue film, make the 2nd IC chip 8 and the first partition 6 bonding; After having glued batch whole a 2nd IC chip 8, at the temperature of 150 DEG C, toast the baking on the same IC chip 3 of baking time and other process conditions after core; After baking, adopt existing method to carry out plasma cleaning, after cleaning, adopt gold thread or copper cash, from the pad of the 2nd IC chip 8 to first substrate pad 7 routings, form the second bonding line 9;
When pressure welding, adopt the pellet bonding machine that possesses low radian short length bonding wire, adopt height arc or the anti-mode of beating from the pad of an IC chip 3 to first substrate pad 7 routings, form first key zygonema 5; The camber of first key zygonema 5 is no more than 110 μ m; Adopt height arc or the anti-mode of beating from the pad of the 2nd IC chip 8 to first substrate pad 7 routings, the camber that forms the second bonding line 9, the second bonding lines 9 is no more than 110 μ m;
For 5 layers of spacer-type IC chip stacked packaging piece:
Adopt the upper core method of 3 layers of spacer-type IC chip stacked packaging piece on the carrier 1 of BT substrate 16, to paste an IC chip 3, pressure welding first key zygonema 5, paste the first partition 6 and the 2nd IC chip 8, pressure welding the second bonding line 9, then paste the second partition 18 and the 3rd IC chip 20:
If adopt insulating cement to paste the second partition 18 and the 3rd IC chip 20, by bonding die glue chip feeder; On the 2nd IC chip 8, put insulating cement, the second partition 18 is placed on this insulating cement, make the second partition 18 and the 2nd IC chip 8 bonding, do not toast, the insulating cement between the second partition 18 and the 2nd IC chip 8 forms the 4th adhesive sheet 17; On the second partition 18, put insulating cement, the 3rd IC chip 20 is placed on this insulating cement, make the 3rd IC chip 20 and the second partition 18 bonding, insulating cement between the 3rd IC chip 20 and the second partition 18 forms the 5th adhesive sheet 19, then send baking, baking at 175 DEG C, its roasting plant and other baking process, with the baking of 3 layers of partition IC chip stacked packaging piece, carry out plasma cleaning after baking; After cleaning, adopt gold thread or copper cash, from the pad of the 3rd IC chip 20 to first substrate pad 7 routings, form the 3rd bonding line 21; The thickness of the 5th adhesive sheet 19 that the thickness of the 4th adhesive sheet 17 that insulating cement forms and insulating cement form is 20 μ m～30 μ m.
Paste the second partition 18 and the 3rd IC chip 20 if adopt glue film, to be placed on the 2nd IC chip 8 with the second partition 18 of glue film, the second partition 18 and the 2nd IC chip 8 are bonding by this glue film, and the glue film between the second partition 18 and the 2nd IC chip 8 forms the 4th adhesive sheet 17; Then will be placed on the second partition 18 with the 3rd IC chip 20 of glue film, the 3rd IC chip 20 and the second partition 18 are bonding by this glue film, and the glue film between the 3rd IC chip 20 and the second partition 18 forms the 5th adhesive sheet 19; Then anti-absciss layer baking at 150 DEG C of temperature, roasting plant and other baking process toast with after 3 layers of spacer-type stacked package glue film bonding die; After baking, carry out plasma cleaning, after cleaning, adopt gold thread or copper cash, from the pad of the 3rd IC chip 20 to first substrate pad 7 routings, form the 3rd bonding line 21;
When pressure welding, use the pellet bonding machine that possesses low radian short length bonding wire, adopt height arc or the anti-mode of beating from the pad of an IC chip 3 to first substrate pad 7 routings, form first key zygonema 5; The camber of first key zygonema 5 be no more than the second adhesive sheet 4, the 3rd adhesive sheet 10 and the first partition 6 thickness and or the camber of first key zygonema 5 be no more than 110 μ m; Adopt height arc or the anti-mode of beating from the pad of the 2nd IC chip 8 to first substrate pad 7 routings, form the second bonding line 9, the camber of the second bonding line 9 is no more than the thickness sum of the 4th adhesive sheet 17, the 5th adhesive sheet 19 and the second partition 18, or the camber of the second bonding line 9 is no more than 110 μ m; Adopt height arc or the anti-mode of beating from the pad of the 3rd IC chip 20 to first substrate pad 7 routings, the camber that forms the 3rd bonding line 21, the three bonding lines 21 is no more than 120 μ m;
For more than 5 layers spacer-type IC chip stacked packaging piece
On 5 layers of spacer-type IC chip stack package, on the basis of core, paste partition and IC chip:
If adopt insulating cement to paste partition and IC chip, on the 3rd IC chip 20, put insulating cement, partition is placed on this insulating cement, make this partition and the 3rd IC chip 20 bonding, do not toast; Then on bonding partition, put insulating cement, IC chip is placed on this insulating cement, make IC chip and this partition bonding, then adopt the baking process identical with 5 layers of spacer-type IC chip stack package to toast, after baking, carry out plasma cleaning; After cleaning, adopt gold thread or copper cash, from the pad of this IC chip to first substrate pad 7 routings, form bonding line; The rest may be inferred, stacking more multi-layered IC chip;
If adopt glue film to paste partition and IC chip, will be placed on the partition of glue film on the 3rd IC chip 20, this partition is pasted by glue film and the 3rd IC chip 20, does not toast; The IC chip with glue film is placed on this partition, this IC chip is bonding by glue film and partition again, at 150 DEG C of temperature, toasts, and roasting plant is identical with 5 layers of spacer-type IC chip stack package with other baking process; After baking, carry out plasma cleaning; After cleaning, adopt gold thread or copper cash, from the pad of this IC chip to first substrate pad 7 routings, form bonding line; According to said method, stacking more multi-layered IC chip;
When pressure welding, adopt the equipment and process of 5 layers of spacer-type IC chip stacked packaging piece pressure welding to form first key zygonema 5, the second bonding line 9 and the 3rd bonding line 21; When 5 layers of above IC chip pressure welding, use the pellet bonding machine that possesses low radian short length bonding wire, adopt height arc or the anti-mode of beating from the pad of this IC chip to first substrate pad 7 routings, form camber and be no more than the bonding line of 120 μ m; According to said method, stacking more multi-layered IC chip;
Step 3: plastic packaging
Select low water absorption (water absorption rate≤0.25%), low stress (coefficient of expansion α 1≤ 1), the length of flow environmental protection plastic packaging material that is 70cm～120cm, use full-automatic encapsulation system and the anti-warpage technique of ultrathin encapsulation, carry out erosion control silk, anti-warpage and anti-absciss layer plastic packaging, obtain semi-finished product framework;
Step 4: solidify afterwards
Use Ace peck IPH-201 series to wait baking oven, at the temperature of 150 DEG C to solidifying 5h after the semi-finished product framework of step 3;
Step 5: plant ball and Reflow Soldering
Adopt existing common BGA Package (BGA) to plant ball and Reflow Soldering equipment and process is planted ball and Reflow Soldering;
Step 6: clean
Adopt cleaning equipment and the technique of existing common BGA Package (BGA) to clean;
Step 7: print
Adopt the printing technique of existing common BGA Package (BGA) to print;
Step 8: products of separated
Use the equipment and process cutting and separating product of existing common BGA Package (BGA) cutting and separating product;
Step 9: test
According to product type and test program, select suitable test machine and separator to test;
Step 10: inspection
The product having tested is carried out to apparent size and thermodynamic state verification, reject substandard product;
Step 11: packaging warehouse-in
The packaging of this packaging part, warehouse-in, with packaging, the warehouse-in of common BGA product.
Stacked package is to solve the miniaturization of current Electronic Packaging product, many I/O, realize the important technical of high density, multi-functional encapsulation, in stacked chip packages technology, applied low annular Wire Bonding, Wafer Thinning technology, thin substrate and low viscosity modelling technique.Stack package of the present invention is rational in infrastructure simple, has the distinguishing features such as anti-layering, anti-friendship silk, good heat dissipation (ceramic partition), and test yield advantages of higher, is suitable for the encapsulation of high density thin space product.
embodiment 1
Final thickness by chip thickness from original wafer reduced thickness to 100 μ m; Corase grind scope is from original wafer thickness to 150 μ m+film thickness, corase grind speed 2 μ m/s; Fine grinding thickness range is from 150 μ m+ film thickness to 100 μ m+film thickness, and fine grinding speed 0.6 μ m/s, adopts and prevent chip warpage technique in wafer thinning process; The roughness of the wafer after attenuate is 0.10mm, adopts DISC 3350 scribing machine scribings, adopts anti-fragment, Anti-cracking scribing process software controlling technique, scribing feed velocity≤10mm/s; Obtain being with the separation IC chip of the zona that stretches tight; It is 110 μ m that attenuate single-chip makes its final thickness; In single-chip thinning process, corase grind scope is from single-chip original thickness to 160 μ m+film thickness, corase grind speed 3 μ m/s; Refine thickness range from 160 μ m+film thickness to 110 μ m+film thickness, fine grinding speed 15 μ m/ s; First on the carrier 1 of BT substrate 16, put conducting resinl by bonding die glue chip feeder, chip feeder automatic sucking the one IC chip 3 is placed on this conducting resinl, makes an IC chip 3 bonding with carrier 1; And adopting anti-absciss layer baking process to carry out 175 DEG C of bakings, roasting plant used and other baking process are with toasting after core on common pcb board; After baking, adopt existing method to carry out plasma cleaning, after cleaning, adopt the pellet bonding machine that possesses low radian short length bonding wire, by height arc mode, gold thread is got to first substrate pad 7 from the pad of an IC chip 3, formation camber is no more than the first key zygonema 5 of 110 μ m; On an IC chip 3, put insulating cement, the thickness of this insulating cement is 20 μ m, the first partition 6 after scribing is placed on an IC chip 3, by insulating cement make the first partition 6 and an IC chip 3 bonding, do not toast; Then, on the first partition 6, putting thickness is the insulating cement of 30 μ m, the 2nd IC chip 8 is placed on the first partition 6, by insulating cement make the 2nd IC chip 8 and the first partition 6 bonding; After having glued batch whole a 2nd IC chip 8, be transported to baking, the baking on the same IC chip 3 of baking process after core; After baking, carry out plasma cleaning, after cleaning, adopt and possess the pellet bonding machine of low radian short length bonding wire, by the mode of instead beating by gold thread from the pad of the 2nd IC chip 8 to first substrate pad 7 routings, formation camber is no more than the second bonding line 9 of 110 μ m.Select water absorption rate≤0.25%, coefficient of expansion α 1≤ 1, the environmental protection plastic packaging material that length of flow is 70cm～120cm, uses full-automatic encapsulation system and the anti-warpage technique of ultrathin encapsulation, carries out erosion control silk, anti-warpage and anti-absciss layer plastic packaging, obtains semi-finished product framework; Use Ace peck IPH-201 series baking oven, at the temperature of 150 DEG C to solidifying 5h after this semi-finished product framework; Adopt existing common BGA Package (BGA) to plant ball and Reflow Soldering equipment and process is planted ball and Reflow Soldering; Adopt cleaning equipment and the technique of existing common BGA Package (BGA) to clean; Adopt the printing technique of existing common BGA Package (BGA) to print; Use the equipment and process cutting and separating product of existing common BGA Package (BGA) cutting and separating product; Then test ,inspection ,packaging warehouse-in, makes 3 layers of spacer-type IC chip stacked packaging piece.
embodiment 2
Final thickness by chip thickness from original wafer reduced thickness to 100 μ m; Corase grind scope is from original wafer thickness to 150 μ m+film thickness, corase grind speed 5 μ m/s; Fine grinding thickness range is from 150 μ m+film thickness to 100 μ m+film thickness, and fine grinding speed 0.3 μ m/s, adopts and prevent chip warpage technique in wafer thinning process; The roughness of the wafer after attenuate is 0.05mm; Adopt the scribing of double-pole scribing machine, adopt anti-fragment, Anti-cracking scribing process software controlling technique, scribing feed velocity≤10mm/s; Obtain being with the separation IC chip of the zona that stretches tight.It is 120 μ m that attenuate single-chip makes its final thickness; In single-chip thinning process, corase grind scope is from single-chip original thickness to 170 μ m+film thickness, corase grind speed 5 μ m/s; Refine thickness range from 170 μ m+film thickness to 120 μ m+film thickness, fine grinding speed 12 μ m/s; First on the carrier 1 of BT substrate 16, put insulating cement by bonding die glue chip feeder, chip feeder automatic sucking the one IC chip 3 is placed on this insulating cement, makes an IC chip 3 bonding with carrier 1; And adopting anti-absciss layer baking process to carry out 175 DEG C of bakings, roasting plant used and other baking process are with toasting after core on common pcb board; After baking, adopt existing method to carry out plasma cleaning; After cleaning, with the pellet bonding machine that possesses low radian short length bonding wire, adopt height arc mode by copper cash from the pad of an IC chip 3 to first substrate pad 7 routings, form the first key zygonema 5 that camber is no more than 110 μ m, on an IC chip 3, put insulating cement, the thickness of this insulating cement is 30 μ m, and the first partition 6 after scribing is placed on an IC chip 3, by insulating cement make the first partition 6 and an IC chip 3 bonding, do not toast; Then, on the first partition 6, putting thickness is the insulating cement of 20 μ m, the 2nd IC chip 8 is placed on the first partition 6, by insulating cement make the 2nd IC chip 8 and the first partition 6 bonding; After having glued batch whole a 2nd IC chip 8, be transported to baking, the baking on the same IC chip 3 of baking process after core; After baking, adopt existing method to carry out plasma cleaning, after cleaning, use the pellet bonding machine that possesses low radian short length bonding wire, adopt the mode of instead beating by gold thread from the pad of the 2nd IC chip 8 to first substrate pad 7 routings, formation camber is no more than the second bonding line 9 of 110 μ m; Select low water absorption≤0.25%, coefficient of expansion α 1≤ 1, the environmental protection plastic packaging material that length of flow is 70cm～120cm, uses full-automatic encapsulation system and the anti-warpage technique of ultrathin encapsulation, carries out erosion control silk, anti-warpage and anti-absciss layer plastic packaging, obtains semi-finished product framework; Use Ace peck IPH-201 series to wait baking oven, at the temperature of 150 DEG C to solidifying 5h after semi-finished product framework; Adopt existing common BGA Package (BGA) to plant ball and Reflow Soldering equipment and process is planted ball and Reflow Soldering; Adopt cleaning equipment and the technique of existing common BGA Package (BGA) to clean; Adopt the printing technique of existing common BGA Package (BGA) to print; Use the equipment and process cutting and separating product of existing common BGA Package (BGA) cutting and separating product; Then test ,inspection ,packaging warehouse-in, makes 3 layers of spacer-type IC chip stacked packaging piece.
embodiment 3
Final thickness by chip thickness from original wafer reduced thickness to 100 μ m; Corase grind scope is from original wafer thickness to 150 μ m+film thickness, corase grind speed 3.5 μ m/s; Fine grinding thickness range is from 150 μ m+film thickness to 100 μ m+film thickness, and fine grinding speed 0.45 μ m/s, adopts and prevent chip warpage technique in wafer thinning process; The roughness of the wafer after attenuate is 0.08mm, adopts the scribing of A-WD-3000TXB scribing machine; Adopt anti-fragment, Anti-cracking scribing process software controlling technique, scribing feed velocity≤10mm/s; Obtain being with the separation IC chip of the zona that stretches tight; It is 100 μ m that attenuate single-chip makes its final thickness; In single-chip thinning process, corase grind scope is from single-chip original thickness to 150 μ m+ film thickness, corase grind speed 4 μ m/s; Refine thickness range from 150 μ m+film thickness to 100 μ m+film thickness, fine grinding speed 14 μ m/ s.First on the carrier 1 of BT substrate 16, put insulating cement by bonding die glue chip feeder, chip feeder automatic sucking the one IC chip 3 is placed on this insulating cement, makes an IC chip 3 bonding with carrier 1; And adopting anti-absciss layer baking process to carry out 175 DEG C of bakings, roasting plant used and other baking process are with toasting after core on common pcb board; After baking, adopt existing method to carry out plasma cleaning; After cleaning, with the pellet bonding machine that possesses low radian short length bonding wire, adopt height arc mode by gold thread from the pad of an IC chip 3 to first substrate pad 7 routings, form the first key zygonema 5 that camber is no more than 110 μ m, on an IC chip 3, put insulating cement, the thickness of this insulating cement is 25 μ m, and the first partition 6 after scribing is placed on an IC chip 3, by insulating cement make the first partition 6 and an IC chip 3 bonding, do not toast; Then, on the first partition 6, putting thickness is the insulating cement of 25 μ m, the 2nd IC chip 8 is placed on the first partition 6, by insulating cement make the 2nd IC chip 8 and the first partition 6 bonding; After having glued batch whole a 2nd IC chip 8, be transported to baking, the baking on the same IC chip 3 of baking process after core; After baking, adopt existing method to carry out plasma cleaning, after cleaning, with the pellet bonding machine that possesses low radian short length bonding wire, adopt the mode of instead beating by gold thread from the pad of the 2nd IC chip 8 to first substrate pad 7 routings, formation camber is no more than the second bonding line 9 of 110 μ m; Select low water absorption≤0.25%, coefficient of expansion α 1≤ 1, the environmental protection plastic packaging material that length of flow is 70cm～120cm, uses full-automatic encapsulation system and the anti-warpage technique of ultrathin encapsulation, carries out erosion control silk, anti-warpage and anti-absciss layer plastic packaging, obtains semi-finished product framework; Use Ace peck IPH-201 series to wait baking oven, at the temperature of 150 DEG C to solidifying 5h after semi-finished product framework; Adopt existing common BGA Package (BGA) to plant ball and Reflow Soldering equipment and process is planted ball and Reflow Soldering; Adopt cleaning equipment and the technique of existing common BGA Package (BGA) to clean; Adopt the printing technique of existing common BGA Package (BGA) to print; Use the equipment and process cutting and separating product of existing common BGA Package (BGA) cutting and separating product; Then test ,inspection ,packaging warehouse-in, makes 3 layers of spacer-type IC chip stacked packaging piece.
embodiment 4
The first partition 6 adopts the microcrystalline glass of customization, adopts the technique of embodiment 1 to carry out wafer reduction scribing, and pastes an IC chip 3, pressure welding first key zygonema 5; Use has the chip feeder of core function on glue film, and the first partition 6 that is pasted with glue film is placed on an IC chip 3, makes the first partition 6 bonding by the second glue film 12 and an IC chip 3, does not toast; Again the 2nd IC chip 8 with glue film is placed on the first partition 6, makes the 2nd IC chip 8 and the first partition 6 bonding; After having glued batch whole a 2nd IC chip 8, at the temperature of 150 DEG C, toast the baking on the same IC chip 3 of baking time and other process conditions after core; After baking, adopt method pressure welding the second bonding line 9 of embodiment 1; Make 3 layers of spacer-type IC chip stacked packaging piece by the follow-up method of embodiment 1 again.
embodiment 5
The potsherd of the first partition 6 use customizations, adopts the technique of embodiment 2 to make 3 layers of spacer-type IC chip stacked packaging piece.
embodiment 6
Final thickness by chip thickness from original wafer reduced thickness to 100 μ m; Corase grind scope is from original wafer thickness to 150 μ m+film thickness, corase grind speed 3 μ m/s; Fine grinding thickness range is from 150 μ m+film thickness to 100 μ m+film thickness, and fine grinding speed 0.4 μ m/s, adopts and prevent chip warpage technique in wafer thinning process; The roughness of the wafer after attenuate is 0.06mm, adopts DISC 3350 scribing machine scribings, obtains being with the separation IC chip of the zona that stretches tight; When scribing, adopt anti-fragment, Anti-cracking scribing process software controlling technique, scribing feed velocity≤10mm/s; It is 75 μ m that attenuate single-chip makes its final thickness; In single-chip thinning process, corase grind scope is from single-chip original thickness to 125 μ m+film thickness, corase grind speed 3.5 μ m/s; Refine thickness range from 125 μ m+film thickness to 75 μ m+film thickness, fine grinding speed 13 μ m/s.First on the carrier 1 of BT substrate 16, put insulating cement by bonding die glue chip feeder, chip feeder automatic sucking the one IC chip 3 is placed on this insulating cement, makes an IC chip 3 bonding with carrier 1; And adopting anti-absciss layer baking process to carry out 175 DEG C of bakings, roasting plant used and other baking process are with toasting after core on common pcb board; After baking, adopt existing method to carry out plasma cleaning; After cleaning, with the pellet bonding machine that possesses low radian short length bonding wire, adopt height arc mode by gold thread from the pad of an IC chip 3 to first substrate pad 7 routings, form the first key zygonema 5 that camber is no more than 110 μ m, on an IC chip 3, put insulating cement, the thickness of this insulating cement is 25 μ m, and the first partition 6 after scribing is placed on an IC chip 3, by insulating cement make the first partition 6 and an IC chip 3 bonding, do not toast; Then, on the first partition 6, putting thickness is the insulating cement of 22 μ m, the 2nd IC chip 8 is placed on the first partition 6, by insulating cement make the 2nd IC chip 8 and the first partition 6 bonding; After having glued batch whole a 2nd IC chip 8, be transported to baking, the baking on the same IC chip 3 of baking process after core; After baking, adopt existing method to carry out plasma cleaning, after cleaning, with the pellet bonding machine that possesses low radian short length bonding wire, adopt the mode of instead beating by gold thread from the pad of the 2nd IC chip 8 to first substrate pad 7 routings, formation camber is no more than the second bonding line 9 of 110 μ m.Use bonding die glue chip feeder, on the 2nd IC chip 8, putting thickness is 25 μ m insulating cements, and the second partition 18 is placed on this insulating cement, makes the second partition 18 and the 2nd IC chip 8 bonding, do not toast, the insulating cement between the second partition 18 and the 2nd IC chip 8 forms the 4th adhesive sheet 17; On the second partition 18, putting thickness is the insulating cement of 20 μ m, the 3rd IC chip 20 is placed on this insulating cement, make the 3rd IC chip 20 and the second partition 18 bonding, insulating cement between the 3rd IC chip 20 and the second partition 18 forms the 5th adhesive sheet 19, then send baking, baking at 175 DEG C, its roasting plant and other baking process, with the baking of 3 layers of partition IC chip stacked packaging piece, carry out plasma cleaning after baking; After cleaning, use the pellet bonding machine that possesses low radian short length bonding wire, adopt height arc mode that gold thread is beaten to first substrate pad 7 from the pad of the 3rd IC chip 20, formation camber is no more than the 3rd bonding line 21 of 120 μ m.Select water absorption rate≤0.25%, coefficient of expansion α 1≤ 1, the environmental protection plastic packaging material that length of flow is 70cm～120cm, uses full-automatic encapsulation system and the anti-warpage technique of ultrathin encapsulation, carries out erosion control silk, anti-warpage and anti-absciss layer plastic packaging, obtains semi-finished product framework; Use Ace peck IPH-201 baking oven, at the temperature of 150 DEG C to solidifying 5h after semi-finished product framework; Adopt existing common BGA Package (BGA) to plant ball and Reflow Soldering equipment and process is planted ball and Reflow Soldering; Adopt cleaning equipment and the technique of existing common BGA Package (BGA) to clean; Adopt the printing technique of existing common BGA Package (BGA) to print; Use the equipment and process cutting and separating product of existing common BGA Package (BGA) cutting and separating product; Then, test, check, pack warehouse-in, make 5 layers of spacer-type IC chip package.
embodiment 7
Use conducting resinl to paste an IC chip 3, make 5 layers of spacer-type IC chip package by the method for embodiment 6.
embodiment 8
Adopt the method stacking stickup identical with embodiment 6 the one IC chip 3, the first partition 6, the 2nd IC chip 8, and difference pressure welding first key zygonema 5 and the second bonding line 9, first key zygonema 5 and the second bonding line 9 all adopt copper cash.Then will be placed on the 2nd IC chip 8 with the second partition 18 of glue film, the second partition 18 and the 2nd IC chip 8 are bonding by this glue film, and the glue film between the second partition 18 and the 2nd IC chip 8 forms the 4th adhesive sheet 17; Then will be placed on the second partition 18 with the 3rd IC chip 20 of glue film, the 3rd IC chip 20 and the second partition 18 are bonding by this glue film, and the glue film between the 3rd IC chip 20 and the second partition 18 forms the 5th adhesive sheet 19; Then anti-absciss layer baking at 150 DEG C of temperature, roasting plant and other baking process toast with after 3 layers of spacer-type IC chip stacked packaging piece glue film bonding die; After baking, carry out plasma cleaning, after cleaning, use the pellet bonding machine that possesses low radian short length bonding wire, adopt the anti-mode of beating that copper cash is beaten to first substrate pad 7 from the pad of the 3rd IC chip 20, formation camber is no more than the 3rd bonding line 21 of 120 μ m.Adopt again the method identical with embodiment 6 to carry out plastic packaging, solidify, plant ball and Reflow Soldering, cleaning, printing, cutting and separating, test, inspection afterwards, packaging is put in storage, makes 5 layers of spacer-type IC chip package.
embodiment 9
Adopt 5 layers of encapsulation of the stacking formation of method of embodiment 6, and pressure welding the 3rd bonding line 21, on the 3rd IC chip 20, put insulating cement, partition is placed on this insulating cement, make this partition and the 3rd IC chip 20 bonding, do not toast; Then on bonding partition, put insulating cement, IC chip is placed on this insulating cement, make IC chip and this partition bonding, then toast, after baking, carry out plasma cleaning; After cleaning, use the pellet bonding machine that possesses low radian short length bonding wire, adopt height arc mode that gold thread is beaten to first substrate pad 7 from the pad of this IC chip, form bonding line; Carry out plastic packaging, solidify, plant ball and Reflow Soldering, cleaning, printing, cutting and separating, test, inspection, packaging warehouse-in afterwards by the method for embodiment 6 again, make 7 layers of spacer-type IC chip package.
embodiment 10
Adopt 5 layers of encapsulation of the stacking formation of method of embodiment 8, and pressure welding the 3rd bonding line 21, being placed on the partition of glue film on the 3rd IC chip 20, this partition is pasted by glue film and the 3rd IC chip 20, does not toast; The IC chip with glue film is placed on this partition, this IC chip is bonding by glue film and partition again, at 150 DEG C of temperature, toasts, and roasting plant is identical with 5 layers of spacer-type IC chip stack package with other baking process; After baking, carry out plasma cleaning; After cleaning, use the pellet bonding machine that possesses low radian short length bonding wire, adopt height arc mode that gold thread is beaten to first substrate pad 7 from the pad of this IC chip, form bonding line; Carry out plastic packaging, solidify, plant ball and Reflow Soldering, cleaning, printing, cutting and separating, test, inspection, packaging warehouse-in afterwards by the method for embodiment 8 again, make 7 layers of spacer-type IC chip package.
Although illustrated and described in conjunction with the preferred embodiments the present invention, those skilled in the art can people understand, and under the prerequisite of the spirit and scope of the present invention that limit without prejudice to claims, can modify and convert.

Claims (3)

1. a multilayer spacer-type IC chip stacked packaging piece production method for substrate, is characterized in that, the production of this packaging part is specifically carried out according to the following steps:
Step 1: wafer attenuate and Wafer Dicing and partition attenuate and partition scribing:
For 3 layers of spacer-type IC chip stacked packaging piece: wafer attenuate final thickness is 100 μ m, and the wafer after attenuate is carried out to scribing;
Partition adopts single-chip: in the time that single-chip is used for 3 layers of stack package, the final thickness after single-chip attenuate is 110 μ m ± 10 μ m; In the time that single-chip is used for 5 layers of stack package, the final thickness after single-chip attenuate is 75 μ m; In the time that single-chip is used for more than 5 layers stack package, the final thickness after single-chip attenuate is 50 μ m;
When partition adopts microcrystalline glass or potsherd, thickness customizes as required, does not need attenuate;
Step 2: upper core, cleaning, pressure welding:
For 3 layers of spacer-type IC chip stacked packaging piece:
At the upper insulating cement of the upper point of the carrier (1) of BT substrate (16) or conducting resinl, by bonding to an IC chip (3) and carrier (1), and adopt anti-absciss layer baking process to carry out 175 DEG C of bakings by this insulating cement or conducting resinl; After baking, carry out plasma cleaning, again from the pad of an IC chip (3) to first substrate pad (7) routing, form the first key zygonema (5) that camber is no more than 110 μ m, then, on an IC chip (3), paste successively the first partition (6) and the 2nd IC chip (8):
Paste the first partition (6) and the 2nd IC chip (8) if adopt insulating cement, at the upper insulating cement of the upper point of an IC chip (3), the first partition (6) after scribing is placed on an IC chip (3), make the first partition (6) and an IC chip (3) bonding by insulating cement, do not toast; Then, at the upper insulating cement of the upper point of the first partition (6), the 2nd IC chip (8) is placed on to the first partition (6) upper, makes the 2nd IC chip (8) and the first partition (6) bonding by insulating cement, send baking; The thickness of twice bonding insulating cement is 20 μ m～30 μ m; Plasma cleaning, then from the pad of the 2nd IC chip (8) to first substrate pad (7) routing, formation camber is no more than the second bonding line (9) of 110 μ m;
If adopt glue film to paste the first partition (6) and the 2nd IC chip (8), the first partition (6) with glue film is placed on to an IC chip (3) upper, make the first partition (6) bonding by glue film and an IC chip (3), do not toast; Upper by be placed on the first partition (6) with the 2nd IC chip (8) of glue film again, make the 2nd IC chip (8) and the first partition (6) bonding; Then at the temperature of 150 DEG C, toast; Plasma cleaning, then from the pad of the 2nd IC chip (8) to first substrate pad (7) routing, formation camber is no more than the second bonding line (9) of 110 μ m;
For 5 layers of spacer-type IC chip stacked packaging piece:
Adopt the upper core method of 3 layers of spacer-type IC chip stacked packaging piece at a upper IC chip (3), pressure welding first key zygonema (5), stickup the first partition (6) and the 2nd IC chip (8), pressure welding the second bonding line (9) pasted of carrier (1), then paste the second partition (18) and the 3rd IC chip (20):
If adopt insulating cement to paste the second partition (18) and the 3rd IC chip (20), at the upper insulating cement of the upper point of the 2nd IC chip (8), the second partition (18) is placed on this insulating cement, make the second partition (18) and the 2nd IC chip (8) bonding, do not toast; At the upper insulating cement of the upper point of the second partition (18), the 3rd IC chip (20) is placed on this insulating cement, make the 3rd IC chip (20) and the second partition (18) bonding; Baking at 175 DEG C, plasma cleaning; From the pad of the 3rd IC chip (20) to first substrate pad (7) routing, formation camber is no more than the 3rd bonding line (21) of 120 μ m again; The thickness of the insulating cement of twice bonding use is 20 μ m～30 μ m;
If adopt glue film to paste the second partition (18) and the 3rd IC chip (20), the second partition (18) with glue film is placed on to the 2nd IC chip (8) upper, make the second partition (18) and the 2nd IC chip (8) bonding; Upper by be placed on the second partition (18) with the 3rd IC chip (20) of glue film again, make the 3rd IC chip (20) and the second partition (18) bonding; Anti-absciss layer baking at 150 DEG C of temperature; Plasma cleaning; From the pad of the 3rd IC chip (20) to first substrate pad (7) routing, formation camber is no more than the 3rd bonding line (21) of 120 μ m again;
For more than 5 layers spacer-type IC chip stacked packaging piece:
On 5 layers of spacer-type IC chip stack package, on the basis of core, paste partition and IC chip:
If adopt insulating cement to paste partition and IC chip,, at the upper insulating cement of the upper point of the 3rd IC chip (20), partition is placed on this insulating cement, make this partition and the 3rd IC chip (20) bonding, do not toast; Then on partition, put insulating cement, IC chip is placed on this insulating cement, make IC chip and this partition bonding, then adopt the baking process identical with 5 layers of spacer-type IC chip stack package to toast, after baking, carry out plasma cleaning; After cleaning, from the pad of this IC chip to first substrate pad (7) routing, form bonding line; The rest may be inferred, stacking more multi-layered IC chip;
If adopt glue film to paste partition and IC chip, upper by be placed on the 3rd IC chip (20) with the partition of glue film, this partition is pasted by glue film and the 3rd IC chip (20), does not toast; The IC chip with glue film is placed on this partition, this IC chip is bonding by glue film and partition again, at 150 DEG C of temperature, toasts, and roasting plant is identical with 5 layers of spacer-type IC chip stack package with other baking process; After baking, carry out plasma cleaning; After cleaning, from the pad of this IC chip to first substrate pad (7) routing, formation camber is no more than the bonding line of 120 μ m;
Step 3: plastic packaging:
Select water absorption rate≤0.25%, coefficient of expansion α 1≤ 1, the environmental protection plastic packaging material that length of flow is 70cm～120cm, uses full-automatic encapsulation system and the anti-warpage technique of ultrathin encapsulation, carries out erosion control silk, anti-warpage and anti-absciss layer plastic packaging, obtains semi-finished product framework;
Step 4: solidify afterwards:
At the temperature of 150 DEG C to after the semi-finished product framework of step 3 solidify 5h;
Step 5: plant ball and Reflow Soldering:
Adopt common BGA Package to plant ball and reflow soldering process is planted ball and Reflow Soldering;
Step 6: clean:
Adopt the cleaning of common BGA Package to clean;
Step 7: print:
Adopt the printing technique of common BGA Package to print;
Step 8: products of separated:
Use the technique cutting and separating product of common BGA Package cutting and separating;
Step 9: test:
Product to cutting and separating is tested;
Step 10: inspection:
The product having tested is tested, reject substandard product;
Step 11: packaging warehouse-in:
Pack, put in storage by the requirement of common BGA packages packaging warehouse-in.
2. production method according to claim 1, is characterized in that, in described step 1 when wafer attenuate, corase grind scope is from original wafer thickness to final thickness+film thickness+50 μ m, corase grind speed 2 μ m/s～5 μ m/s; Fine grinding thickness range is from final thickness+film thickness+50 μ m to wafer final thickness+film thickness, and fine grinding speed 0.3 μ m/s～0.6 μ m/s, adopts and prevent chip warpage technique in wafer thinning process; The roughness of the wafer after attenuate is 0.10mm～0.05mm; In described single-chip thinning process, corase grind scope is from single-chip original thickness to final single-chip thickness+film thickness+50 μ m, corase grind speed 3 μ m/s～5 μ m/s; Refine thickness range from final single-chip thickness+film thickness+50 μ m to final single-wafer thickness+film thickness, fine grinding speed 12 μ m/s～15 μ m/s.
3. production method according to claim 1, is characterized in that, in described step 2, when pressure welding, uses the pellet bonding machine that possesses low radian short length bonding wire, adopts height arc or the anti-mode routing of beating, and forms bonding line.
CN201110455062.8A 2011-12-31 2011-12-31 Multilayer spacer type IC (Integrated Circuit) chip stacked package of substrate and production method of package Active CN102569272B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201110455062.8A CN102569272B (en) 2011-12-31 2011-12-31 Multilayer spacer type IC (Integrated Circuit) chip stacked package of substrate and production method of package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110455062.8A CN102569272B (en) 2011-12-31 2011-12-31 Multilayer spacer type IC (Integrated Circuit) chip stacked package of substrate and production method of package

Publications (2)

Publication Number Publication Date
CN102569272A CN102569272A (en) 2012-07-11
CN102569272B true CN102569272B (en) 2014-06-25

Family

ID=46414304

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110455062.8A Active CN102569272B (en) 2011-12-31 2011-12-31 Multilayer spacer type IC (Integrated Circuit) chip stacked package of substrate and production method of package

Country Status (1)

Country Link
CN (1) CN102569272B (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104091791A (en) * 2012-08-31 2014-10-08 天水华天科技股份有限公司 Lead frame pagoda type IC chip stacked package part and production method thereof
CN104219888B (en) * 2014-08-15 2017-07-28 安徽广德威正光电科技有限公司 A kind of BT plates sheet material sawing sheet technique
JP6290758B2 (en) * 2014-09-19 2018-03-07 ルネサスエレクトロニクス株式会社 Semiconductor device
TWI653721B (en) * 2017-11-29 2019-03-11 南茂科技股份有限公司 Wafer stack package structure
CN110021548B (en) * 2019-04-03 2020-09-11 江苏纳沛斯半导体有限公司 Process for reducing edge breakage of chip cutting edge
CN111863715A (en) * 2020-07-28 2020-10-30 南通通富微电子有限公司 Chip interconnection method
CN112466759A (en) * 2020-11-09 2021-03-09 太极半导体（苏州）有限公司 Packaging method for preventing bonding wires from collapsing and bending after surface mounting
CN113369220A (en) * 2021-05-31 2021-09-10 厦门香翎贸易有限公司 Medical glass sheet cleaning and sterilizing machine and using method thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100214562B1 (en) * 1997-03-24 1999-08-02 구본준 Stacked semiconductor chip package and making method thereof
DE102007018914B4 (en) * 2007-04-19 2019-01-17 Infineon Technologies Ag Semiconductor device with a semiconductor chip stack and method for producing the same
US20080265393A1 (en) * 2007-04-24 2008-10-30 Advanced Chip Engineering Technology Inc. Stack package with releasing layer and method for forming the same
KR101096042B1 (en) * 2010-03-18 2011-12-19 주식회사 하이닉스반도체 Semiconductor package and method for manufacturing thereof
CN102163591B (en) * 2010-12-02 2014-06-25 天水华天科技股份有限公司 Spherical grating array IC (integrated circuit) chip packaging part and production method thereof
CN202394964U (en) * 2011-12-31 2012-08-22 天水华天科技股份有限公司 Multilayer-spacer IC (integrated circuit) chip laminated package for substrate

Also Published As

Publication number Publication date
CN102569272A (en) 2012-07-11

Similar Documents

Publication Publication Date Title
CN102569272B (en) Multilayer spacer type IC (Integrated Circuit) chip stacked package of substrate and production method of package
CN102222657B (en) Multi-ring-arranged double-integrated circuit (IC) chip packaging piece and production method thereof
CN100583431C (en) Manufacture method of stacking chip encapsulation structure
CN103346181B (en) Solar cell module without welding strips and preparation method thereof
WO2012071759A1 (en) High density sim card package module and producing method thereof
CN104615981B (en) A kind of fingerprint recognition modular structure and preparation method thereof
CN102163591B (en) Spherical grating array IC (integrated circuit) chip packaging part and production method thereof
CN107622957A (en) The manufacture method of two-sided SiP three-dimension packaging structure
TWI395316B (en) Multi-chip module package
WO2012068763A1 (en) Gird-array ic chip package without carrier and manufacturing method thereof
TW200924082A (en) Multiple chips stack structure and method for fabricating the same
CN103329263A (en) Stitch bump stacking design for overall package size reduction for multiple stack
TW201218317A (en) Method of multi-chip stacking for decreasing void between chips
CN101221945A (en) Packaging body capable of repeatedly stacking
CN103426871B (en) A kind of high density mixing laminated packaging structure and preparation method thereof
CN103250246A (en) Method and system for thin multi chip stack package with film on wire and copper wire
CN103594447B (en) IC chip stacked packaging piece that the big high frequency performance of packaging density is good and manufacture method
CN202394964U (en) Multilayer-spacer IC (integrated circuit) chip laminated package for substrate
CN104900624A (en) System-level MEMS dual-carrier chip encapsulation component and production method thereof
CN102231376B (en) Multi-cycle arrangement carrier-free double-integrated chip (IC) package and production method
CN203165882U (en) Stacked package structure
CN116936377A (en) Board-level fan-out packaging method
US10297566B2 (en) Semiconductor structure and manufacturing method thereof
CN104981102B (en) A kind of Embedded flexible PCB of multi-chip and its manufacturing method
CN110299364A (en) Semiconductor device and its manufacturing method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant