CN202394964U - Multilayer-spacer IC (integrated circuit) chip laminated package for substrate - Google Patents
Multilayer-spacer IC (integrated circuit) chip laminated package for substrate Download PDFInfo
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- CN202394964U CN202394964U CN201120568213.6U CN201120568213U CN202394964U CN 202394964 U CN202394964 U CN 202394964U CN 201120568213 U CN201120568213 U CN 201120568213U CN 202394964 U CN202394964 U CN 202394964U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
The utility model discloses a multilayer-spacer IC (integrated circuit) chip laminated package for a substrate, which comprises a BT substrate, wherein at least two IC chips are attached to a carrier of the BT substrate; the IC chips are sequentially laminated and attached; a bonding pad of each IC chip is connected with a bonding pad of the BT substrate through a bonding wire; a plastic packaging body is fixedly packaged on the BT substrate; and a spacer is attached between every two adjacent IC chips. The package does not influence the height of the bonding wire, and enhances the heat dissipation and electric insulating properties of the chips.
Description
Technical field
The utility model belongs to electronic information Element of automatic control manufacturing technology field; Relate to a kind of IC chip ic package; Be specifically related to a kind of chip-stacked packaging part of multilayer spacer IC of substrate, the utility model also relates to a kind of production method of this stack package.
Background technology
Growth along with the electronic device of littler, lighter and more powerful all kinds of mobile phone market expanded demand and palmtop PC (PAD); The more miniaturization of Electronic Packaging technology, multi-purpose research and development have been promoted; Stacked package has been to satisfy littler, lighter, the multi-purpose a kind of important technical of product; And more and more respectively being encapsulated corporate client's attention, all kinds of mobile phone digital cameras, various smart card and portable instrument are the applications of stacked package product.The multifunction technology of mobile phone has promoted the fast development and the skill upgrading of stacked package again.
At present, stacked package all is directly the IC chip to be piled up bondingly through adhesive sheet, and influence connects the height of the bonding line of IC chip and carrier pad, and the insulation property between adjacent chips are bad, also have influence on the heat radiation of chip.
The utility model content
In order to overcome the problem that exists in the above-mentioned prior art, the purpose of the utility model provides a kind of chip-stacked packaging part of multilayer spacer IC of substrate, and the bonding line height meets the requirements, the insulation property of chip chamber and the heat dispersion of chip.
For realizing above-mentioned purpose, the technical scheme that the utility model adopted is a kind of chip-stacked packaging part of multilayer spacer IC of substrate; Comprise the BT substrate; Be bonded with at least two IC chips on the carrier of BT substrate, all IC chips stack gradually stickup, and the pad on each IC chip is connected with pad on the BT substrate through bonding line; Be sealed with plastic-sealed body on the BT substrate, be pasted with partition between the adjacent two IC chips.
Partition is through insulating cement or glue film and IC chip attach.
Partition adopts single-chip, microcrystalline glass or potsherd.
The camber that the camber of the bonding line that the IC chip that piles up links to each other with the BT substrate by first IC chip away from the order of carrier is no more than the bonding line that 110 μ m, second IC chip link to each other with the BT substrate is no more than 110 μ m; From the 3rd IC chip, the camber of the bonding line that every IC chip links to each other with the BT substrate is no more than 120 μ m.
It is basic identical that the packaging part of the utility model piles up size, the thickness of used a plurality of IC chip sizes; Be provided with partition between the adjacent two IC chips; Height between these adjacent two IC chips is increased; For bonding line provides enough spaces, not only solved the height problem of bonding line, and be beneficial to the heat radiation of IC chip; Simultaneously, because partition adopts non electrically conductive material to process, the insulation property of adjacent two IC chip chambers have further been improved.
Description of drawings
Fig. 1 is the structural representation of three layers of spacer stack package in the utility model stack package.
Fig. 2 is the structural representation of five layers of spacer stack package in the utility model stack package.
Among the figure, 1. carrier, 2. first adhesive sheet, 3. an IC chip, 4. second adhesive sheet, 5. first bonding line; 6. first partition, 7. first substrate pads, 8. the 2nd IC chip, 9. second bonding line, 10. the 3rd adhesive sheet, 11. plastic-sealed bodies; 12. second substrate pads, 13. salient points, 14. scolders, 15. tin balls, 16.BT substrate; 17. the 4th adhesive sheet, 18. second partitions, 19. the 5th adhesive sheets, 20. the 3rd IC chips, 21. triple bond zygonemas.
Embodiment
Below in conjunction with accompanying drawing and embodiment the utility model is elaborated.
As shown in Figure 1, the structure of three layers of spacer stack package in the utility model stack package comprises BT substrate 16; Be pasted with an IC chip 3 on the carrier 1 of BT substrate 16; The one IC chip 3 is bonding with carrier 1 through first adhesive sheet 2, and it is bonding through second adhesive sheet 4 and an IC chip 3 to be pasted with first partition, 6, the first partitions 6 on the IC chip 3; It is bonding through the 3rd adhesive sheet 10 and first partition 6 to be pasted with the 2nd IC chip 8, the two IC chips 8 on first partition 6; Be provided with first substrate pads, 7, the first substrate pads 7 above the BT substrate 16 and be connected with second substrate pads 12 that is arranged at BT substrate 16 bottom surfaces, second substrate pads 12 is provided with salient point (UBM) 13, and salient point 13 is welded with tin ball 15 through scolder 14; The one IC chip 3 is connected with first substrate pads 7 through first bonding line 5, and the 2nd IC chip 8 is connected with first substrate pads 7 through second bonding line 9.Be sealed with plastic-sealed body 11 on the BT substrate 16; Top, first adhesive sheet 2 of top, the BT substrate 16 of carrier 1, an IC chip 3, second adhesive sheet 4, first partition 6, the 3rd adhesive sheet 10, the 2nd IC chip 8, first substrate pads 7, first bonding line 5 and second bonding line 9 all are packaged in the plastic-sealed body 11, and it is whole to form circuit.11 pairs the one IC chips of plastic-sealed body 3, first bonding line 5, the 2nd IC chip 8 and second bonding line 9 have played protection and supporting role.First substrate pads 7, an IC chip 3, first bonding line 5, the 2nd IC chip 8, second bonding line 9, second substrate pads 12, salient point (UBM) 13, scolder 14 and tin ball 15 have constituted the power supply and the signalling channel of circuit.
As shown in Figure 2, the structure of five layers of spacer stack package in the utility model stack package comprises BT substrate 16; Be bonded with an IC chip 3 on the carrier 1 of BT substrate 16; The one IC chip 3 is bonding with carrier 1 through the first bonding die glue 2, and it is bonding through second adhesive sheet 4 and an IC chip 3 to be bonded with first partition, 6, the first partitions 6 on the IC chip 3; It is bonding through the 3rd adhesive sheet 10 and first partition 6 to be bonded with the 2nd IC chip 8, the two IC chips 8 on first partition 6; It is bonding through the 4th adhesive sheet 17 and the 2nd IC chip 8 to be bonded with second partition, 18, the second partitions 18 on the 2nd IC chip 8, is bonded with on second partition 18 that the 3rd IC chip 20, the three IC chips 20 pass through the 5th adhesive sheet 19 and second partition 18 is bonding; Be provided with first substrate pads, 7, the first substrate pads 7 above the BT substrate 16 and be connected with second substrate pads 12 that is arranged at BT substrate 16 bottom surfaces, second substrate pads 12 is provided with salient point (UBM) 13, and salient point 13 is welded with tin ball 15 through scolder 14; The one IC chip 3 is connected with first substrate pads 7 through first bonding line 5, and the 2nd IC chip 8 is connected with first substrate pads 7 through second bonding line 9, and the 3rd IC chip 20 is connected with first substrate pads 7 through triple bond zygonema 21.Be sealed with plastic-sealed body 11 on carrier 1 and the BT substrate 16; Top, first adhesive sheet 2 of top, the BT substrate 14 of carrier 1, an IC chip 3, second adhesive sheet 4, first partition 6, the 3rd adhesive sheet 10, the 2nd IC chip 8, the 4th adhesive sheet 17, second partition 18, the 5th adhesive sheet 19, the 3rd IC chip 20, first substrate pads 7, first bonding line 5, second bonding line 9 and triple bond zygonema 21 all are packaged in the plastic-sealed body 11, and it is whole to form circuit.11 pairs the one IC chips of plastic-sealed body 3, first bonding line 5, the 2nd IC chip 8, second bonding line 9, the 3rd IC chip 20 and triple bond zygonema 21 have played protection and supporting role.First substrate pads 7, an IC chip 3, first bonding line 5, the 2nd IC chip 8, second bonding line 9, the 3rd IC chip 20, triple bond zygonema 21, second substrate pads 12, salient point 13, scolder 14 and tin ball 15 have constituted the power supply and the signalling channel of circuit.
First adhesive sheet 2 adopts insulating cement or conducting resinl, when the IC chip has heat radiation or power requirement, uses conducting resinl, when the IC chip does not have heat radiation or power requirement, uses insulating cement; Second adhesive sheet 4 adopts insulating cement or glue film; The 3rd adhesive sheet 10 adopts insulating cement or glue film; First adhesive sheet 17 adopts insulating cement or glue film; The 5th adhesive sheet 19 adopts insulating cement or glue film; It is to occur unwanted conducting between the neighbouring two-layer IC chip in order to prevent that first adhesive sheet 2, second adhesive sheet 4, the 3rd adhesive sheet 10, the 4th adhesive sheet 17 and the 5th adhesive sheet 19 adopt insulating cements or glue film.
BT substrate 16 is a kind of multilayer laminated type seamless link wiring boards; Parts and parts reach the insulating material that is provided with interlayer through interlayer and interlayer isolates; So carrier 1 is arranged on the BT substrate 16; Carrier 1 is the position of bonding IC chip, and it is pad that the BT substrate 16 around the carrier 1 is provided with golden finger, and the pad on the IC chip is electric with the circuit and the external world with the golden finger realization on the BT substrate 16 through bonding line, being connected of signal.
The encapsulation number of plies of this packaging part is 2n+1, and n is the partition number, and chip-count is n+1; Work as n=1, promptly the partition number is 1 o'clock, and chip-count is 2, and it is the packing forms of two-layer IC chip and one deck partition that the formation number of plies is 3 layers; Work as n=2, promptly the partition number is 2 o'clock, and chip-count is 3, and constitute the number of plies being 5 layers is the packing forms of three layers of IC chip and two-layer partition; When the partition number was n (n＞2), chip-count was n+1, and constituting the number of plies is that 2n+1 is the packing forms of n+1 layer chip and n layer partition.Packaging part is on the basis of 5 layers of partition encapsulation more than 5 layers, increases by 2 layers at every turn, and promptly one deck partition and one deck IC chip increase one deck bonding line and two-layer insulating cement simultaneously, and perhaps two-layer glue film increases one deck bonding line and two-layer glue film.
It is basic identical that the utility model packaging part piles up size, the thickness of used a plurality of IC chip sizes, for the height problem that solves bonding wire and the problem of chip chamber insulation or heat radiation, is provided with one deck partition between the adjacent two IC chips.According to the difference of the application function of chip (common, heat radiation or power), partition can adopt three kinds of materials, and first kind is common single-chip; Second kind is microcrystalline glass; The third is a potsherd, and wherein the potsherd thermal diffusivity is good, is mainly used in power circuit and the packaging part that has heat radiation to require; But material price is higher, adopts customization; Microcrystalline glass is the most cheap, adopts the outsourcing customization; The convenient processing of single-chip, thickness and size can be controlled, and the preceding back side of scribing can be pasted glue film in advance.
The utility model package structure is rationally simple, has anti-layering, the anti-distinguishing features such as silk, good heat dissipation (ceramic partition), testing yield height of handing over, and is suitable for the encapsulation of high density thin space product.
The production procedure of above-mentioned packaging part is following:
1) 3 layers of chip-stacked packaging part of spacer IC
Wafer attenuate, wafer scribing
,Partition attenuate and partition scribing
-Core on the first time (conducting resinl or insulating cement) and baking
-Plasma cleans for the first time
-Pressure welding for the first time
-Bonding partition (insulating cement or glue film)
-Core on the second time (insulating cement or glue film) and baking
-Plasma cleans for the second time
-Pressure welding for the second time
-Solidify plastic packaging and back
-Plant ball and Reflow Soldering
-Clean
-Print
-Products of separated
-Test
-Check
-Packing
-Warehouse-in.
2) 5 layers of chip-stacked packaging part of spacer IC
Wafer attenuate, wafer scribing, partition attenuate and partition scribing
-Core on the first time (conducting resinl or insulating cement) and baking
-Plasma cleans for the first time
-Pressure welding for the first time
-Bonding partition (insulating cement or glue film) for the first time
-Core on the second time (insulating cement or glue film) and baking
-Plasma cleans for the second time
-Pressure welding for the second time
-Bonding partition (insulating cement or glue film) for the second time
-Go up for the third time core (insulating cement or glue film) and baking
-Plasma cleans for the third time
-Pressure welding for the third time
-Solidify plastic packaging and back
-Plant ball and Reflow Soldering
-Clean
-Print
-Products of separated
-Test
-Check
-Packing
-Warehouse-in.
The chip-stacked packaging part of spacer IC more than 5 layers; Adopt 3 layers and 5 layers of chip-stacked encapsulation technology of spacer IC; Putting adhesives (insulating cement or glue film) on the 3rd IC chip 20, placing earlier partition, then on this partition again on adhesives (insulating cement or glue film); Place IC chip and baking again, the 4th time plasma cleans
-The 4th pressure welding
-Solidify plastic packaging and back
-Plant ball and Reflow Soldering
-Clean
-Print
-Products of separated
-Test
-Check
-Packing
-Warehouse-in.
The utility model also provides a kind of production method of above-mentioned packaging part, and is specific as follows:
Step 1: wafer attenuate and wafer scribing and partition attenuate and partition scribing
For 3 layers of stack package: chip original wafer thickness is 600 μ m ± 10 μ m, and wafer attenuate final thickness is 100 μ m; The corase grind scope from original wafer thickness to final thickness+film thickness+50 μ m, corase grind speed 2 μ m/s～5 μ m/s; To wafer final thickness+film thickness, correct grinding speed 0.3 μ m/s～0.6 μ m/s adopts in the wafer thinning process and prevents chip warpage technology the correct grinding thickness range from final thickness+film thickness+50 μ m; The roughness Ra of the wafer behind the attenuate is 0.10mm～0.05mm,
Wafer behind the attenuate below 8 inch and 8 inch adopts DISC 3350 or the scribing of double-pole scribing machine, obtains the separation IC chip with the zona that stretches tight; The wafer of 8 inch behind the attenuate of 12 inch adopts the scribing of A-WD-3000TXB scribing machine; Obtain separation IC chip with the zona that stretches tight; Adopt anti-fragment, anti-crackle scribing process software controlling technique during scribing, scribing feed velocity≤10mm/s;
When partition adopted single-chip, the final thickness of the single-chip of attenuate was decided according to the number of plies of piling up that this partition uses; When single-chip was used for 3 layers of stack package, the final thickness of single-chip was 110 μ m ± 10 μ m; When single-chip was used for 5 layers of stack package, the final thickness of single-chip was 75 μ m; When single-chip was used for more than 5 layers stack package, the final thickness of single-chip was 50 μ m; In the single-chip thinning process, the corase grind scope from the single-chip original thickness to final single-chip thickness+film thickness+50 μ m, corase grind speed 3 μ m/s～5 μ m/s; The correct grinding thickness range from final single-chip thickness+film thickness+50 μ m to final single-wafer thickness+film thickness, correct grinding speed 12 μ m/s～15 μ m/ s;
When partition adopted microcrystalline glass or potsherd, its thickness customized as required, does not need attenuate;
Step 2: go up core, cleaning, pressure welding
For 3 layers of chip-stacked packaging part of partition IC:
Earlier putting first adhesive sheet 2 on the carrier 1 of BT substrate 16 through bonding die glue chip feeder, chip feeder is drawn an IC chip 3 automatically and is placed on first adhesive sheet 2, makes an IC chip 3 bonding with carrier 1; And adopting anti-absciss layer baking process to carry out 175 ℃ of bakings, used roasting plant and technology are with toasting behind the core on the common pcb board; After the baking; The existing method of employing is carried out the plasma cleaning, and employing gold thread or copper cash to first substrate pads, 7 routings, form first bonding line 5 from the pad of an IC chip 3 after cleaning; Then, on an IC chip 3, paste first partition 6 and the 2nd IC chip 8 successively:
If adopt insulating cement to paste first partition 6 and the 2nd IC chip 8, then, first partition 6 after the scribing is placed on the IC chip 3 putting insulating cement on the IC chip 3, make first partition 6 and an IC chip 3 bonding through insulating cement, do not toast; Then,, the 2nd IC chip 8 is placed on first partition 6, makes the 2nd IC chip 8 and first partition 6 bonding through insulating cement putting insulating cement on first partition 6; Be transported to baking after having glued whole the 2nd IC chips 8 of this batch, the baking on the same IC chip 3 of baking process behind the core; The thickness of twice bonding insulating cement is 20 μ m～30 μ m; Baking back is adopted existing method to carry out plasma and is cleaned, and cleans the back and adopts gold thread or copper cash, to first substrate pads, 7 routings, forms second bonding line 9 from the pad of the 2nd IC chip 8;
Paste first partition 6 and the 2nd IC chip 8 if adopt glue film; Then use chip feeder with core function on the glue film; The semi-finished product BT substrate 16 of pressure welding first bonding line 5 is served this chip feeder, and making the heating-up temperature of substrate according to the performance of used glue film is 120 ℃～150 ℃ or higher, and first partition 6 that chip feeder is drawn the band glue film is placed on the IC chip 3; Make first partition 6 bonding, do not toast through a glue film and an IC chip 3; And then will be that the 2nd IC chip 8 is placed on first partition 6 with the IC chip of glue film, make the 2nd IC chip 8 and first partition 6 bonding; Glue whole the 2nd IC chips 8 of this batch and then under 150 ℃ temperature, toasted the baking on the same IC chip 3 of stoving time and other process conditions behind the core; Baking back is adopted existing method to carry out plasma and is cleaned, and cleans the back and adopts gold thread or copper cash, to first substrate pads, 7 routings, forms second bonding line 9 from the pad of the 2nd IC chip 8;
During pressure welding, adopt the ball bonding machine possess low radian short length bonding wire, adopt height arc or counter beat mode from the pad of an IC chip 3 to first substrate pads, 7 routings, form first bonding line 5; The camber of first bonding line 5 is no more than 110 μ m; Adopt height arc or counter beat mode from the pad of the 2nd IC chip 8 to first substrate pads, 7 routings, the camber that forms second bonding line, 9, the second bonding lines 9 is no more than 110 μ m;
For 5 layers of chip-stacked packaging part of spacer IC:
Adopt the last core method of 3 layers of chip-stacked packaging part of spacer IC on the carrier 1 of BT substrate 16, to paste an IC chip 3; Pressure welding first bonding line 5; Paste first partition 6 and the 2nd IC chip 8, pressure welding second bonding line 9, paste second partition 18 and the 3rd IC chip 20 then:
If adopt insulating cement to paste second partition 18 and the 3rd IC chip 20, then through bonding die glue chip feeder; Putting insulating cement on the 2nd IC chip 8, second partition 18 is placed on this insulating cement, make second partition 18 and the 2nd IC chip 8 bonding, do not toast, the insulating cement between second partition 18 and the 2nd IC chip 8 forms the 4th adhesive sheet 17; Putting insulating cement on second partition 18; The 3rd IC chip 20 is placed on this insulating cement, makes the 3rd IC chip 20 and second partition 18 bonding, the insulating cement between the 3rd IC chip 20 and second partition 18 forms the 5th adhesive sheet 19; Send baking then; 175 ℃ of bakings down, its roasting plant and the baking of other baking process with 3 layers of chip-stacked packaging part of partition IC carry out plasma and clean after the baking; After the cleaning, adopt gold thread or copper cash, to first substrate pads, 7 routings, form triple bond zygonema 21 from the pad of the 3rd IC chip 20; The thickness of the 5th adhesive sheet 19 that the thickness of the 4th adhesive sheet 17 that insulating cement forms and insulating cement form is 20 μ m～30 μ m.
Paste second partition 18 and the 3rd IC chip 20 if adopt glue film; Second partition 18 of band glue film is placed on the 2nd IC chip 8; Second partition 18 and the 2nd IC chip 8 are bonding through this glue film, and the glue film between second partition 18 and the 2nd IC chip 8 forms the 4th adhesive sheet 17; To be placed on the 3rd IC chip 20 of glue film on second partition 18 then, the 3rd IC chip 20 and second partition 18 are bonding through this glue film, and the glue film between the 3rd IC chip 20 and second partition 18 forms the 5th adhesive sheet 19; Anti-absciss layer baking under 150 ℃ of temperature then, roasting plant toasts with behind 3 layers of spacer stacked package glue film bonding die with other baking process; Carry out plasma after the baking and clean, after the cleaning, adopt gold thread or copper cash, to first substrate pads, 7 routings, form triple bond zygonema 21 from the pad of the 3rd IC chip 20;
During pressure welding, use the ball bonding machine possess low radian short length bonding wire, adopt height arc or counter beat mode from the pad of an IC chip 3 to first substrate pads, 7 routings, form first bonding line 5; The camber of first bonding line 5 be no more than second adhesive sheet 4, the 3rd adhesive sheet 10 and first partition 6 thickness and or the camber of first bonding line 5 be no more than 110 μ m; Adopt height arc or counter beat mode from the pad of the 2nd IC chip 8 to first substrate pads, 7 routings; Form second bonding line 9; The camber of second bonding line 9 is no more than the thickness sum of the 4th adhesive sheet 17, the 5th adhesive sheet 19 and second partition 18, and perhaps the camber of second bonding line 9 is no more than 110 μ m; Adopt height arc or counter beat mode from the pad of the 3rd IC chip 20 to first substrate pads, 7 routings, the camber that forms triple bond zygonema 21, the triple bond zygonemas 21 is no more than 120 μ m;
For the chip-stacked packaging part of spacer IC more than 5 layers
On the basis of core in 5 layers of chip-stacked encapsulation of spacer IC, paste partition and IC chip:
If adopt insulating cement to paste partition and IC chip, then, partition is placed on this insulating cement putting insulating cement on the 3rd IC chip 20, make this partition and the 3rd IC chip 20 bonding, do not toast; Then, the IC chip is placed on this insulating cement, makes IC chip and this partition bonding, adopt then and toast, carry out plasma after the baking and clean with 5 layers of identical baking process of the chip-stacked encapsulation of spacer IC putting insulating cement on the bonding partition; After the cleaning, adopt gold thread or copper cash, to first substrate pads, 7 routings, form bonding line from this IC bonding pads; The rest may be inferred, piles up the more IC chip of multilayer;
If adopt glue film to paste partition and IC chip, the partition that then will have glue film is placed on the 3rd IC chip 20, and this partition is pasted through glue film and the 3rd IC chip 20, does not toast; The IC chip that will have glue film again is placed on this partition, and this IC chip is bonding through glue film and partition, under 150 ℃ of temperature, toasts, and roasting plant is identical with 5 layers of chip-stacked encapsulation of spacer IC with other baking process; Carrying out plasma after the baking cleans; After the cleaning, adopt gold thread or copper cash, to first substrate pads, 7 routings, form bonding line from this IC bonding pads; According to said method, pile up the more IC chip of multilayer;
During pressure welding, adopt equipment and the technology of 5 layers of chip-stacked packaging part pressure welding of spacer IC to form first bonding line 5, second bonding line 9 and the triple bond zygonema 21; During IC chip pressure welding more than 5 layers, use the ball bonding machine that possesses low radian short length bonding wire, adopt height arc or counter beat mode from this IC bonding pads to first substrate pads, 7 routings, form the bonding line that camber is no more than 120 μ m; According to said method, pile up the more IC chip of multilayer;
Step 3: plastic packaging
Select low water absorption (water absorption rate≤0.25%), low stress (coefficient of expansion α for use
1≤1), length of flow be 70cm～120cm the environmental protection plastic packaging material, use full-automatic encapsulation system and the anti-warpage technology of ultrathin encapsulation, carry out erosion control silk, anti-warpage and anti-absciss layer plastic packaging, obtain the semi-finished product framework;
Step 4: solidify the back
Use baking ovens such as Ace peck IPH-201 series, behind the semi-finished product framework to step 3 under 150 ℃ the temperature, solidify 5h;
Step 5: plant ball and Reflow Soldering
Adopt existing common BGA Package (BGA) to plant ball and Reflow Soldering equipment and technology and plant ball and Reflow Soldering;
Step 6: clean
Adopt the cleaning equipment and the technology of existing common BGA Package (BGA) to clean;
Step 7: print
Adopt the printing technology of existing common BGA Package (BGA) to print;
Step 8: products of separated
Use the equipment and the technology cutting and separating product of existing common BGA Package (BGA) cutting and separating product;
Step 9: test
According to product type and test program, select for use suitable test machine and separator to test;
Step 10: check
Product to having tested carries out apparent size and thermodynamic state verification, rejects substandard product;
Step 11: packing warehouse-in
The packing of this packaging part, warehouse-in are with packing, the warehouse-in of common BGA product.
Stacked package is to solve the miniaturization of current Electronic Packaging product; Many I/O; Realize the important technical of high density, multi-functional encapsulation, used low annular wire bond technology, disk thinning technique, thin substrate and low viscosity modelling technique in the stacked chips encapsulation technology.The utility model stack package is rational in infrastructure simple, has anti-layering, anti-silk, the good heat dissipation distinguishing features such as (ceramic partitions) handed over, and the testing yield advantages of higher is suitable for the encapsulation of high density thin space product.
Though illustrated and described the present invention in conjunction with the preferred embodiments, those skilled in the art can the people understand, and under the prerequisite of the spirit and scope of the present invention that limit without prejudice to accompanying claims, can make amendment and conversion.
Claims (4)
1. the chip-stacked packaging part of multilayer spacer IC of a substrate; Comprise BT substrate (16), be bonded with at least two IC chips on the carrier (1) of BT substrate (16), all IC chips stack gradually stickup; Pad on each IC chip is connected with pad on the BT substrate (16) through bonding line; Be sealed with plastic-sealed body (11) on the BT substrate (16), it is characterized in that, be pasted with partition between the adjacent two IC chips.
2. the chip-stacked packaging part of multilayer spacer IC according to claim 1 is characterized in that, described partition is through insulating cement or glue film and IC chip attach.
3. the chip-stacked packaging part of multilayer spacer IC according to claim 1 and 2 is characterized in that, described partition adopts single-chip, microcrystalline glass or potsherd.
4. the chip-stacked packaging part of multilayer spacer IC according to claim 1; It is characterized in that the camber that the camber of the bonding line that the said IC chip that piles up links to each other with BT substrate (16) by first IC chip away from the order of carrier (1) is no more than the bonding line that 110 μ m, second IC chip link to each other with BT substrate (16) is no more than 110 μ m; From the 3rd IC chip, the camber of the bonding line that every IC chip links to each other with BT substrate (16) is no more than 120 μ m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201120568213.6U CN202394964U (en) | 2011-12-31 | 2011-12-31 | Multilayer-spacer IC (integrated circuit) chip laminated package for substrate |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201120568213.6U CN202394964U (en) | 2011-12-31 | 2011-12-31 | Multilayer-spacer IC (integrated circuit) chip laminated package for substrate |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569272A (en) * | 2011-12-31 | 2012-07-11 | 天水华天科技股份有限公司 | Multilayer spacer type IC (Integrated Circuit) chip stacked package of substrate and production method of package |
| CN106419838A (en) * | 2016-08-30 | 2017-02-22 | 福州瑞芯微电子股份有限公司 | Integrated chip for intestinal tract detection and implementation method of integrated chip |
| CN109727913A (en) * | 2017-10-30 | 2019-05-07 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
-
2011
- 2011-12-31 CN CN201120568213.6U patent/CN202394964U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569272A (en) * | 2011-12-31 | 2012-07-11 | 天水华天科技股份有限公司 | Multilayer spacer type IC (Integrated Circuit) chip stacked package of substrate and production method of package |
| CN106419838A (en) * | 2016-08-30 | 2017-02-22 | 福州瑞芯微电子股份有限公司 | Integrated chip for intestinal tract detection and implementation method of integrated chip |
| CN109727913A (en) * | 2017-10-30 | 2019-05-07 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
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