CN1309059C - 端子基板的加工方法 - Google Patents

端子基板的加工方法 Download PDF

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CN1309059C
CN1309059C CNB038229056A CN03822905A CN1309059C CN 1309059 C CN1309059 C CN 1309059C CN B038229056 A CNB038229056 A CN B038229056A CN 03822905 A CN03822905 A CN 03822905A CN 1309059 C CN1309059 C CN 1309059C
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荒井一尚
山铜英之
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147Assembling terminal to base
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147Assembling terminal to base
    • Y10T29/49149Assembling terminal to base by metal fusion bonding
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49204Contact or terminal manufacturing
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49204Contact or terminal manufacturing
    • Y10T29/49208Contact or terminal manufacturing by assembling plural parts
    • Y10T29/49222Contact or terminal manufacturing by assembling plural parts forming array of contacts or terminals
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T82/00Turning
    • Y10T82/10Process of turning

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Abstract

关于配置了形成多个球形电极的端子的基板,可在使多个端子(4)从被覆了抗蚀剂膜的基板(2)表面突出之后,在保留抗蚀剂膜的状态下,通过将基板(2)保持在可旋转的卡盘台(17)上边使卡盘台(17)旋转,边将车刀(19)抵在被覆了抗蚀剂膜的面上车削多个端子(4),可使转接板(1)之类的多个端子以极其小的间隔突出的端子基板的头部高度一致的情况下,既不造成端子间短路,又可高效而又经济地进行加工。

Description

端子基板的加工方法
技术领域
本发明涉及多个配置了形成球形电极的端子基板的加工方法。
背景技术
将表面形成多个集成电路的半导体晶片,使用切割装置分割为各个半导体芯片之后,通常情况下每个芯片被封装后用于各种电子设备,但近年来开发出通过将同一种半导体芯片多层层迭封装从而提高每一个封装件的存储容量及处理能力,或者在收容多个种功能各异的半导体芯片的状态下,通过封装,使一个封装件的功能提高的技术,在这些技术之中,将半导体芯片安装到称之为转接板的基板上的同时,再将该转接板安装到印制板等安装基板上,从而形成转接板介于半导体芯片与安装基板间的结构。
在转接板的表面及底面上分别形成端子,两种端子靠转接板内部的电路连接。此外,底面的端子上形成球形电极,表面的端子与半导体芯片下面形成的突起连接,通过将底面的端子上形成的球形电极与安装基板的电极接线座连接,即可将半导体芯片与安装基板导通。通过使用该转接板可使各种电子设备实现小型轻量化。
为了可靠连接转接板的表面端子与在半导体芯片上形成的突起或在转接板背面形成的球形电极与安装基板的电极,需要在转接板的加工阶段使表面与背面的多个端子的头部平坦而又均匀一致。因而有人建议采用切削装置来切削端子(参照特开2002-203922号公报第7页、第11图)。
另一方面,当并不针对转接板的端子,而是在使CSP底面上形成的突起外露,平坦而又均匀地对齐的情况下,也公示出使用切削刃的方法(参照特开2000-173954号公报、第3~4页)。
然而,由于在转接板上形成的多个端子与在CSP的底部上形成的突起并不相同,相邻的端子间的间隔仅有几十μm,几乎近到肉眼无法看清的地步,因此,当用切削装置切削端子头部使之高度一致的情况下,存在着因构成端子的金属延展性而使端子短路的问题。
此外,当使用CMP(Chemical Mechanical Polishing)使端子头部整齐一致时,由于需花费相当长的时间因而生产效率差,同时也存在废液处理增加成本的问题。
此类问题并不局限于转接板,而是端子以极小间隔形成的端子基板存在的共同问题。因此在此类端子基板的加工中如何不使端子间短路,可高效而又经济地使端子头部一致即成为研究课题。
发明内容
作为用来解决上述课题的具体手段,本发明目的是提供一种端子基板的加工方法,其特征在于:这是配置了形成多个球形电极的端子的端子基板加工方法,端子基板是介于半导体芯片的电极与贴装基板的电极间的转接板,使多个端子从被覆了抗蚀剂膜的基板表面突出之后,将该端子基板保持在可旋转的卡盘台上,边使该卡盘台旋转边将车刀抵在该多个端子的突出面上,通过车削使多个端子的头部处于相对于基板同一高度的平面。
而且该端子基板的加工方法,将下列各项作为附加要点:在保留抗蚀剂膜的状态下进行车削以便多个端子的头部一致;端子基板是介于半导体芯片的电极与贴装基板的电极间的转接板;端子为铜电极,车刀为单晶金刚石车刀;卡盘台的转速为500RPM,车刀的进给速度从卡盘台的外圆到圆心,该卡盘台每转一圈为50μm,该车刀的切入量为5μm~15μm。
若采用具有此种构成的端子基板加工方法,由于可通过用车刀切削从被覆在基板上的抗蚀剂膜表面突出的多个端子,使其头部高度一致,来对抗金属的延展性,因而不会使相邻的端子短路。
此外,由于是在保留抗蚀剂膜的状态下进行切削,端子可在抗蚀剂膜的支持下被切削,因而不会产生因在不稳定状态下进行切削而出现的头部形状与高度不一致等问题。
附图说明
图1是形成本发明所适用的转接板的晶片的示意图,
图2是该转接板的剖视图,
图3是举例说明本发明实施方式中使用的切削装置的示意图,
图4是切削后的转接板的剖视图,
图5是在该转接板的端子上形成球形电极时的剖视图,
图6是使用本发明加工出的转接板的使用方法的第1例示的剖视图,
图7是该使用方法的第2例示的剖视图。
具体实施方式
下面就本发明的实施方式之一,加工图1所示多个形成端子基板之一的转接板的晶片W时的情况加以说明。
在构成该晶片W的各转接板1之中,正如图2所示,在由硅等构成的基板2的表面上全部被覆了抗蚀剂膜3,多个端子4从其表面突出。端子4是在基板2的一面上被覆了抗蚀剂膜3之后,通过曝光等手段去除打算形成端子4位置上的抗蚀剂膜;再将由铜、铝、金、银等金属构成的端子填充到该去除部分后形成的。虽未图示,但在转接板1的另一个面上同样可形成端子。
接着用图3所示的切削装置10,通过切削去除端子4的突出部分使其头部的高度同样平坦,成为可形成球形电极的状态。
切削装置10上配置了可朝底座11的X轴方向移动的X轴移动件12、可朝底座11的Y轴方向移动的Y轴移动件13、以及可朝X移动件12的Z轴方向移动的Z轴移动件14。
Y轴移动件13支持着主轴罩15,主轴罩15可旋转地支持着主轴16。此外,主轴16的端部上配置了可保持板状件的卡盘台17。
Z轴移动件14上固定着车刀支持件18,车刀支持件18的端部上固定着刃部朝卡盘台17方向的车刀19。作为该车刀19可使用单晶金刚石之类的车刀。
图1所示的晶片W被保持在卡盘台17上。此时未形成打算切削的端子4的面保持在卡盘台17上,而形成端子4的面则与车刀19对峙。
并通过主轴16的高速旋转,保持在卡盘台17上的晶片W亦随之旋转,通过Z轴移动件14的上下运动,车刀亦上下运动的同时,通过X轴移动件12朝X方向移动,边与多个转接板1的面接触边切削从抗蚀剂膜3突出的端子4,正如图4所示,多个端子4的头部变得平坦,形成高度一致的状态。
车削时的卡盘台17的转速最好设定为500RPM。此外若能与该卡盘台17的转速相适应,使X轴移动件12以卡盘台17每转一圈车刀19从卡盘台17的外圆朝圆心移动50μm的速度朝X轴方向移动,则可更有效地进行所有端子4的车削。
车刀19的切入量可通过图3所示的Y轴移动件13的Y轴方向上的移动实现高精度控制。例如车刀19对应于端子4的切入量为5μm~15μm。
若如上述用车19切削端子头部,则与用磨削砂轮进行磨削时不同,不会因构成端子4的金属的延展性而使相邻端子短路。
而且由于端子4是在被抗蚀剂膜3固定其周围的状态下被切削其头部的,因而不会出现由于在不稳定的状态下切削,头部形状与高度不一致之类的问题。
如上所述,使端子4的头部的高度一致之后,可如图5所示,通过在端子4上形成球形电极5,即可介于安装基板上形成的电极与半导体芯片上形成的电极之间,形成具有导通两电极功能的转接板。
采用上述方法形成的转接板1的使用方法如下:例如图6所示,当层迭了多个半导体芯片C1、C2、C3的情况下,连接最下层的半导体芯片C1的底面上形成的电极与在转接板1的表面的端子4的上部形成的球形电极5,并进而将转接板1底面的球形电极6与印制板等的安装基板7的电极连接。
此外如图7所示,当转接板被用于CSP8的情况下,也可将半导体芯片C的底面上形成的电极与转接板1的表面上的端子4上部形成的球形电极5连接,并进而将转接板1的底面上的球形电极9与安装基板1的电极连接。
无论是在图6还是图7的情况下,由于转接板1的表面的端子4与半导体芯片的底面端子对应,因而尽管彼此相邻的端子之间只有肉眼几乎看不到的几十μm,但由于采用本发明将端子4切削为其高度一致,不会出现端子间的短路,因而可维持作为转接板的功能,不会使电路的动作产生故障。
如上所述,若采用本发明涉及的端子基板加工方法,由于用车刀切削从被覆在基板上的抗蚀剂膜突出的多个端子,使其头部的高度一致,因而可克服金属的延展性对端子头部进行切削,正因如此,既不会使相邻的端子间发生短路,也不会使半导体芯片上形成的电路动作产生故障。
此外,通过在保留抗蚀剂膜的状态下进行端子的切削,可在端子受抗蚀剂膜支持的状态下进行切削,因而不会出现由于在不稳定的状态下进行切削从而使头部形状及高度不一的情况,端子基板的质量绝不会下降。

Claims (4)

1、一种端子基板的加工方法,其特征在于:这是配置了形成多个球形电极的端子的端子基板加工方法,端子基板是介于半导体芯片的电极与贴装基板的电极间的转接板,使多个端子从被覆了抗蚀剂膜的基板表面突出之后,将该端子基板保持在可旋转的卡盘台上,边使该卡盘台旋转边将车刀抵在该多个端子的突出面上,通过车削使多个端子的头部处于相对于基板同一高度的平面。
2、根据权利要求1所述的端子基板加工方法,其特征在于:在留有抗蚀剂膜的状态下进行车削以便使多个端子的头部处于相对于基板同一高度的平面。
3、根据权利要求1或2所述的端子基板加工方法,其特征在于:端子为铜电极,车刀为单晶金刚石车刀。
4、根据权利要求1或2所述的端子基板加工方法,其特征在于:卡盘台的转速为500RPM,该卡盘台每转一圈,车刀从卡盘台的外圆到圆心的进给速度为50μm,在与基板表面垂直的方向上该车刀的切入量为5μm~15μm。
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