CN1279593C - Producing process for SOI MOSFET device with channels with electric and heating channels - Google Patents
Producing process for SOI MOSFET device with channels with electric and heating channels Download PDFInfo
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- CN1279593C CN1279593C CN 03137307 CN03137307A CN1279593C CN 1279593 C CN1279593 C CN 1279593C CN 03137307 CN03137307 CN 03137307 CN 03137307 A CN03137307 A CN 03137307A CN 1279593 C CN1279593 C CN 1279593C
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- oxygen
- silicon
- masking layer
- oxide
- heat
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- 238000000034 method Methods 0.000 title claims abstract description 17
- 238000010438 heat treatment Methods 0.000 title abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 46
- 239000001301 oxygen Substances 0.000 claims abstract description 46
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 46
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 38
- 239000010703 silicon Substances 0.000 claims abstract description 38
- 230000000873 masking effect Effects 0.000 claims abstract description 28
- 238000000137 annealing Methods 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 25
- -1 silicon metal-oxide Chemical class 0.000 claims description 25
- 230000000295 complement effect Effects 0.000 claims description 19
- 230000005669 field effect Effects 0.000 claims description 17
- 229910044991 metal oxide Inorganic materials 0.000 claims description 16
- 235000012239 silicon dioxide Nutrition 0.000 claims description 16
- 239000000377 silicon dioxide Substances 0.000 claims description 16
- 238000005516 engineering process Methods 0.000 claims description 15
- 230000004888 barrier function Effects 0.000 claims description 14
- 238000004140 cleaning Methods 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 238000001816 cooling Methods 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 239000003595 mist Substances 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 10
- 238000004377 microelectronic Methods 0.000 abstract description 2
- 238000002347 injection Methods 0.000 abstract 3
- 239000007924 injection Substances 0.000 abstract 3
- 238000009933 burial Methods 0.000 abstract 1
- 239000012212 insulator Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005352 clarification Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
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- Thin Film Transistor (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention discloses a manufacturing process for an SOI MOSFET device with a channel with an electric and a heating paths, which belongs to the technical field of the manufacture of a micro-electronic device. The manufacturing process and a body silicon and SOI process are completely compatible, and only four process steps need manufacturing the SOI MOSFET device with a channel with an electric and a heating paths. The process steps are that a patterned oxygen injecting mask is added on the basis of a conventional CMOS process, an oxygen injection masking layer is hot grown or deposited on a Si sheet, the oxygen injection masking layer is photoetched by the patterned oxygen injecting mask, and a burial SiO#-[2] layer is formed by oxyanion injection and high-temperature annealing. The present invention is simple, and is easy to control. The present invention overcomes the floating body effect and the self-heating effect of an SOI device, and enables the thermal stability of the SOI MOSFET device and the reliability of device stable operation to greatly improve.
Description
Technical field
The invention belongs to microelectronic component manufacturing technology scope, particularly a kind of raceway groove has silicon metal-oxide semiconductor fieldeffect transistor manufacturing process on the insulating barrier of heat, electric channel.
Technical background
Traditional silicon-on-insulator (SOI) metal-oxide semiconductor fieldeffect transistor (MOSFET) has one deck buried insulator layer below device, be generally silicon dioxide, is called the buried silicon dioxide layer.The existence of this layer has reduced the parasitic junction capacitance in leakage, source region, and device isolated fully, has therefore improved device speed, has eliminated latch-up.Yet, the buried silicon dioxide layer has also brought self-heating effect (at L.T.Su to silicon metal-oxide semiconductor fieldeffect transistor on the insulating barrier, J.E.Chung, D.A.Antoniadis, etal., " Measurement and modeling of self-heating in SOI nMOSFET ' s ", IEEETransactions on Electron Devices, 1994,41 (1): existing report among the 69-75) and floater effect (at T.Matsumoto, S.Maeda, Y.Hirano, et al., " Clarification offloating-body effects on drive current and short channel effect in deepsub-O.25 μ m partially depleted SOI MOSFETs ", IEEE Transactions on ElectronDevices, 2002,49 (1): two important disadvantages existing report among the 55-60), cause the thermal stability of this device and the reliability of device steady operation to be affected, for floater effect and the self-heating effect that overcomes SOI device, we have proposed raceway groove in the utility model patent of application before this have heat, silicon metal-oxide semiconductor fieldeffect transistor structure on the insulating barrier of electric channel.The technology that we adopt graphical oxonium ion to inject has realized that raceway groove has silicon metal-oxide semiconductor fieldeffect transistor on the insulating barrier of heat, electric channel.
Summary of the invention
The purpose of this invention is to provide a kind of raceway groove and have silicon metal-oxide semiconductor fieldeffect transistor manufacturing process on the insulating barrier of heat, electric channel, this technology and body silicon and silicon-on-insulator process are compatible fully, promptly increase by one and annotate the mask of oxygen and heat growth or oxygen masking layer film is annotated in deposit, the oxygen masking layer is annotated in the photoetching of oxygen mask, oxonium ion injects and high annealing forms 4 processing step of buried silicon dioxide layer with annotating on silicon chip on complementary metal-oxide-semiconductor technology basis.Its manufacture craft flow process is:
1. use the silicon chip cleaning cleaning silicon chip of complementary metal-oxide-semiconductor;
2. the oxygen masking layer is annotated in heat growth or deposit: the oxygen masking layer is annotated in growth of complementary metal-oxide-semiconductor process heat or deposit, annotates the oxygen masking layer for heat growth silicon dioxide, and annotating oxygen masking layer thickness is 0.5～1 micron;
3. photoetching:, adopt the etching technics etching of complementary metal-oxide-semiconductor to annotate the oxygen masking layer with the graphical mask of annotating oxygen;
4. oxonium ion injects: the dosage range that oxonium ion injects is every square centimeter 2 * 10
17～2 * 10
18Individual, energy range is 50～200 kilo electron volts, and silicon temperature is 400 ℃～700 ℃.
5. annealing: high annealing forms the buried silicon dioxide layer.Annealing is that the volume content at oxygen is in the mist of 0.5%～5% nitrogen and oxygen, or carries out in argon gas, and in annealing process, insulation was 1 hour when temperature was raised to 1000 ℃; Continue then to heat up, insulation is 1～24 hour in the time of 1200～1375 ℃.Rate of temperature fall: more than 1200 ℃ be 1.5 ℃/minute; 1200～1000 ℃ is 2 ℃/minute; 1000～700 ℃ is 3 ℃/minute; Naturally cooling below 700 ℃;
6. remove with complementary metal-oxide-semiconductor technology and annotate oxygen masking layer and silicon chip cleaning;
7. make metal-oxide semiconductor fieldeffect transistor with complementary metal-oxide-semiconductor technology.
Described notes oxygen masking layer injects mask as oxonium ion, can be silicon dioxide, silicon nitride or silicon oxynitride or coating photoresist.
Beneficial effect of the present invention is that this technology and body silicon and silicon-on-insulator process are compatible fully, only needing increases mask and 4 processing steps of annotating oxygen on complementary metal-oxide-semiconductor technology basis, can produce raceway groove and have silicon metal-oxide semiconductor fieldeffect transistor on the insulating barrier of heat, electric channel structure.This device has overcome the floater effect and the self-heating effect of SOI device, and the thermal stability of silicon metal-oxide semiconductor fieldeffect transistor on the insulating barrier and the reliability of device steady operation are improved greatly.
Description of drawings
Fig. 1 has silicon metal-oxide semiconductor fieldeffect transistor structural representation on the insulating barrier of heat, electric channel for raceway groove.
Embodiment
The present invention has silicon metal-oxide semiconductor fieldeffect transistor manufacturing process on the insulating barrier of heat, electric channel for a kind of raceway groove.Increase mask and 4 processing steps of annotating oxygen on complementary metal-oxide-semiconductor device technology basis, that is: the oxygen masking layer is annotated in heat growth or deposit on silicon chip, the oxygen masking layer is annotated in the photoetching of oxygen mask, oxonium ion injects and high annealing forms the buried silicon dioxide layer with annotating.Its manufacture craft flow process is:
1. silicon chip cleans: with the silicon chip cleaning cleaning silicon chip of complementary metal-oxide-semiconductor;
2. the oxygen masking layer is annotated in heat growth or deposit: the oxygen masking layer is annotated in growth of complementary metal-oxide-semiconductor process heat or deposit, and annotating oxygen masking layer thickness is 0.5～1 micron;
3. photoetching:, adopt the etching technics etching of complementary metal-oxide-semiconductor to annotate the oxygen masking layer with annotating the oxygen mask.For the notes oxygen masking layer of heat growth silicon dioxide, use the reactive ion etching process etching silicon dioxide;
4. oxonium ion injects: it is to be every square centimeter 2 * 10 at dosage respectively that oxonium ion injects
17Individual, energy 50 kilo electron volts, dosage are every square centimeter 2.5 * 10
17Individual, energy 70 kilo electron volts, dosage are every square centimeter 4.8 * 10
17Individual, energy 140 kilo electron volts and dosage are every square centimeter 2 * 10
18Individual, energy 200 kilo electron volts, and the silicon chip substrate temperature remains on respectively and carries out oxonium ion under 400 ℃, 500 ℃, 600 ℃ and 700 ℃ and inject, and forms the buried silicon dioxide layer.
5. annealing: in the annealing process, high annealing is in argon gas, or the volume content of oxygen is respectively in the mist of 0.5%, 1%, 2%, 3%, 4%, 5% nitrogen and oxygen and carries out, and is incubated 1 hour when temperature is raised to 1000 ℃; Continue to heat up then, in the time of 1200 ℃, 1300 ℃, 1375 ℃, under 5,10,20,24 hours conditions of insulation, all can form the buried silicon dioxide layer again.Rate of temperature fall: more than 1200 ℃ be 1.5 ℃/minute; 1000～1200 ℃ is 2 ℃/minute; 1000～700 ℃ is 3 ℃/minute; Naturally cooling below 700 ℃;
6. remove with complementary metal-oxide-semiconductor technology and annotate oxygen masking layer and silicon chip cleaning;
7. make metal-oxide semiconductor fieldeffect transistor (as shown in Figure 1) with complementary metal-oxide-semiconductor technology.
Figure 1 shows that raceway groove has silicon Metal-oxide-semicondutor field effect transistor on the insulating barrier of heat, electric channel The tubular construction schematic diagram is shown in the figure: 1: the source region; 2: grid; 3: the drain region; 4: the buried silicon dioxide layer; 5: Silicon substrate.
Claims (2)
1. a raceway groove has silicon metal-oxide semiconductor fieldeffect transistor manufacturing process on the insulating barrier of heat, electric channel, it is characterized in that: silicon technology is compatible fully on this technology and body silicon and the insulating barrier, promptly increases by one and annotate the oxygen mask and heat growth or oxygen masking layer film is annotated in deposit, the oxygen masking layer is annotated in the photoetching of oxygen mask, oxonium ion injects and high annealing forms 4 processing step of buried silicon dioxide layer with annotating on silicon chip on complementary metal-oxide-semiconductor technology basis; Annotating oxygen masking layer manufacture craft flow process is:
1. use the silicon chip cleaning cleaning silicon chip of complementary metal-oxide-semiconductor;
2. the oxygen masking layer is annotated in heat growth or deposit: the oxygen masking layer is annotated in growth of complementary metal-oxide-semiconductor process heat or deposit, and annotating oxygen masking layer thickness is 0.5～1 micron;
3. photoetching:, adopt the etching technics etching of complementary metal-oxide-semiconductor to annotate the oxygen masking layer with annotating the oxygen mask; Energy range is 50～200 kilo electron volts, and silicon temperature is 400 ℃～700 ℃;
4. oxonium ion injects: the dosage range that oxonium ion injects is every square centimeter 2 * 10
17～2 * 10
18Individual, energy range is 50～200 kilo electron volts, and silicon temperature is 400 ℃～700 ℃;
5. annealing: high annealing forms the buried silicon dioxide layer, annealing be the volume content at oxygen be 0.5%～5% nitrogen with the mist of oxygen in, or in argon gas, carry out, in annealing process, be incubated 1 hour when temperature is raised to 1000 ℃; Continue then to heat up, insulation is 1～24 hour in the time of 1200～1375 ℃, rate of temperature fall: more than 1200 ℃ be 1.5 ℃/minute; 1200～1000 ℃ is 2 ℃/minute; 1000～700 ℃ is 3 ℃/minute; Naturally cooling below 700 ℃;
6. remove with complementary metal-oxide-semiconductor technology and annotate oxygen masking layer and silicon chip cleaning;
7. make metal-oxide semiconductor fieldeffect transistor with complementary metal-oxide-semiconductor technology.
2. according to the described raceway groove of claim 1 silicon metal-oxide semiconductor fieldeffect transistor manufacturing process on the insulating barrier of heat, electric channel is arranged, it is characterized in that: described notes oxygen masking layer, the mask that injects as oxonium ion is silicon dioxide, silicon nitride, silicon oxynitride or applies photoresist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03137307 CN1279593C (en) | 2003-06-10 | 2003-06-10 | Producing process for SOI MOSFET device with channels with electric and heating channels |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03137307 CN1279593C (en) | 2003-06-10 | 2003-06-10 | Producing process for SOI MOSFET device with channels with electric and heating channels |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1457088A CN1457088A (en) | 2003-11-19 |
| CN1279593C true CN1279593C (en) | 2006-10-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03137307 Expired - Fee Related CN1279593C (en) | 2003-06-10 | 2003-06-10 | Producing process for SOI MOSFET device with channels with electric and heating channels |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102006019937B4 (en) * | 2006-04-28 | 2010-11-25 | Advanced Micro Devices, Inc., Sunnyvale | Method for producing an SOI transistor with embedded deformation layer and a reduced effect of the potential-free body |
| CN101924138B (en) * | 2010-06-25 | 2013-02-06 | 中国科学院上海微系统与信息技术研究所 | MOS (Metal Oxide Semiconductor) device structure for preventing floating-body effect and self-heating effect and preparation method thereof |
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