CN1251077C - 实现数据处理中的中断的方法和数据处理系统 - Google Patents

实现数据处理中的中断的方法和数据处理系统 Download PDF

Info

Publication number
CN1251077C
CN1251077C CNB011016914A CN01101691A CN1251077C CN 1251077 C CN1251077 C CN 1251077C CN B011016914 A CNB011016914 A CN B011016914A CN 01101691 A CN01101691 A CN 01101691A CN 1251077 C CN1251077 C CN 1251077C
Authority
CN
China
Prior art keywords
hardware
interrupt
memory device
interruption
look
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB011016914A
Other languages
English (en)
Chinese (zh)
Other versions
CN1309350A (zh
Inventor
威廉·C.·莫耶尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of CN1309350A publication Critical patent/CN1309350A/zh
Application granted granted Critical
Publication of CN1251077C publication Critical patent/CN1251077C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
CNB011016914A 2000-01-24 2001-01-22 实现数据处理中的中断的方法和数据处理系统 Expired - Fee Related CN1251077C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/490,132 2000-01-24
US09/490,132 US6845419B1 (en) 2000-01-24 2000-01-24 Flexible interrupt controller that includes an interrupt force register

Publications (2)

Publication Number Publication Date
CN1309350A CN1309350A (zh) 2001-08-22
CN1251077C true CN1251077C (zh) 2006-04-12

Family

ID=23946756

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB011016914A Expired - Fee Related CN1251077C (zh) 2000-01-24 2001-01-22 实现数据处理中的中断的方法和数据处理系统

Country Status (5)

Country Link
US (1) US6845419B1 (enExample)
JP (1) JP4749556B2 (enExample)
KR (1) KR100734158B1 (enExample)
CN (1) CN1251077C (enExample)
TW (1) TW563029B (enExample)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040117532A1 (en) * 2002-12-11 2004-06-17 Bennett Steven M. Mechanism for controlling external interrupts in a virtual machine system
JP2004199187A (ja) * 2002-12-16 2004-07-15 Matsushita Electric Ind Co Ltd Cpu内蔵lsi
US7739438B2 (en) * 2003-02-12 2010-06-15 Hewlett-Packard Development Company, L.P. Method for priority-encoding interrupts and vectoring to interrupt code
US7584316B2 (en) * 2003-10-14 2009-09-01 Broadcom Corporation Packet manager interrupt mapper
GB2409543B (en) * 2003-12-23 2006-11-01 Advanced Risc Mach Ltd Interrupt masking control
JP2005242806A (ja) * 2004-02-27 2005-09-08 Renesas Technology Corp データ処理装置
US7162559B1 (en) * 2005-03-08 2007-01-09 Emc Corporation System for controlling interrupts between input/output devices and central processing units
US20060256876A1 (en) * 2005-05-13 2006-11-16 Andre Szczepanek Fast Decode of Pending Interrupts
US7913255B2 (en) * 2005-10-20 2011-03-22 Qualcomm Incorporated Background thread processing in a multithread digital signal processor
CN100365604C (zh) * 2005-12-02 2008-01-30 北京中星微电子有限公司 一种中断控制处理装置和方法
CN100365605C (zh) * 2005-12-02 2008-01-30 北京中星微电子有限公司 多级中断申请装置和方法
CN100397375C (zh) * 2005-12-02 2008-06-25 北京中星微电子有限公司 多中断处理单元的中断处理的装置和方法
EP2225645B1 (en) 2007-12-17 2011-07-27 Continental Teves AG & Co. oHG Memory mapping system, request controller, multi-processing arrangement, central interrupt request controller, apparatus, method for controlling memory access and computer program product
US7793025B2 (en) * 2008-03-28 2010-09-07 Freescale Semiconductor, Inc. Hardware managed context sensitive interrupt priority level control
US8135884B1 (en) * 2009-05-04 2012-03-13 Cypress Semiconductor Corporation Programmable interrupt routing system
US8112551B2 (en) 2009-05-07 2012-02-07 Cypress Semiconductor Corporation Addressing scheme to allow flexible mapping of functions in a programmable logic array
JP4897851B2 (ja) * 2009-05-14 2012-03-14 インターナショナル・ビジネス・マシーンズ・コーポレーション コンピュータ・システム及びコンピュータ・システムの制御方法
US8135894B1 (en) * 2009-07-31 2012-03-13 Altera Corporation Methods and systems for reducing interrupt latency by using a dedicated bit
CN101699418B (zh) * 2009-10-30 2011-11-16 曙光信息产业(北京)有限公司 一种中断处理方法、系统及设备
CN102822802B (zh) * 2010-03-30 2016-08-03 富士通株式会社 多核处理器系统以及控制方法
US8738830B2 (en) * 2011-03-03 2014-05-27 Hewlett-Packard Development Company, L.P. Hardware interrupt processing circuit
US9645823B2 (en) 2011-03-03 2017-05-09 Hewlett-Packard Development Company, L.P. Hardware controller to choose selected hardware entity and to execute instructions in relation to selected hardware entity
US9189283B2 (en) 2011-03-03 2015-11-17 Hewlett-Packard Development Company, L.P. Task launching on hardware resource for client
CN102314399A (zh) * 2011-07-07 2012-01-11 曙光信息产业股份有限公司 一种龙芯刀片设备中断分配的实现方法
US9146776B1 (en) * 2011-08-16 2015-09-29 Marvell International Ltd. Systems and methods for controlling flow of message signaled interrupts
WO2013038589A1 (ja) * 2011-09-14 2013-03-21 パナソニック株式会社 資源要求調停装置、資源要求調停システム、資源要求調停方法、集積回路およびプログラム
US9128920B2 (en) 2011-11-30 2015-09-08 Marvell World Trade Ltd. Interrupt handling systems and methods for PCIE bridges with multiple buses
US8762615B2 (en) * 2011-12-21 2014-06-24 International Business Machines Corporation Dequeue operation using mask vector to manage input/output interruptions
KR101356541B1 (ko) * 2012-01-09 2014-01-29 한국과학기술원 멀티 코어 프로세서, 이를 포함하는 멀티 코어 시스템, 전자 장치 및 멀티 코어 프로세서의 캐시 공유 방법
CN102932599A (zh) * 2012-11-09 2013-02-13 北京百纳威尔科技有限公司 基于gpio模拟数据总线实现照相机功能的装置及方法
JP6056576B2 (ja) * 2013-03-18 2017-01-11 富士通株式会社 割り込み要因を特定する方法及び装置
US9665509B2 (en) * 2014-08-20 2017-05-30 Xilinx, Inc. Mechanism for inter-processor interrupts in a heterogeneous multiprocessor system
US10078605B2 (en) * 2014-10-22 2018-09-18 Cavium, Inc. Multiple-interrupt propagation scheme in a network ASIC
US10591892B2 (en) 2015-06-05 2020-03-17 Renesas Electronics America Inc. Configurable mapping of timer channels to protection groups
GB2550904B (en) * 2016-05-27 2020-07-15 Arm Ip Ltd Methods and Apparatus for Creating Module Instances
GB2561881A (en) * 2017-04-27 2018-10-31 Airbus Group Ltd Microcontroller
CN112130904B (zh) * 2020-09-22 2024-04-30 黑芝麻智能科技(上海)有限公司 处理系统、处理器间通信方法、以及共享资源管理方法
CN116151390A (zh) * 2023-01-30 2023-05-23 澎峰(北京)科技有限公司 一种计算图划分方法、装置及存储介质

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5057997A (en) * 1989-02-13 1991-10-15 International Business Machines Corp. Interruption systems for externally changing a context of program execution of a programmed processor
EP0535821B1 (en) * 1991-09-27 1997-11-26 Sun Microsystems, Inc. Method and apparatus for dynamically steering undirected interrupts
AU3424693A (en) 1992-01-02 1993-07-28 Amdahl Corporation Software control of hardware interruptions
JPH064306A (ja) * 1992-06-19 1994-01-14 Furukawa Electric Co Ltd:The 割り込み処理の分割方法
CA2123447C (en) * 1993-09-20 1999-02-16 Richard L. Arndt Scalable system interrupt structure for a multiprocessing system
US5671424A (en) 1994-02-02 1997-09-23 Advanced Micro Devices, Inc. Immediate system management interrupt source with associated reason register
US6185629B1 (en) * 1994-03-08 2001-02-06 Texas Instruments Incorporated Data transfer controller employing differing memory interface protocols dependent upon external input at predetermined time
JPH07262023A (ja) * 1994-03-23 1995-10-13 Fujitsu Ltd 割込制御方式
JPH08272727A (ja) * 1995-03-29 1996-10-18 Oki Electric Ind Co Ltd システムイベント処理機構
KR960038390U (ko) * 1995-05-10 1996-12-18 인터럽트 처리장치
KR100206964B1 (ko) * 1996-11-19 1999-07-01 구본준 인터럽트 요구 선택회로
US5987601A (en) * 1997-02-14 1999-11-16 Xyron Corporation Zero overhead computer interrupts with task switching
US5937199A (en) * 1997-06-03 1999-08-10 International Business Machines Corporation User programmable interrupt mask with timeout for enhanced resource locking efficiency
FR2775370B1 (fr) * 1998-02-20 2001-10-19 Sgs Thomson Microelectronics Procede de gestion d'interruptions dans un microprocesseur
US6412081B1 (en) * 1999-01-15 2002-06-25 Conexant Systems, Inc. System and method for providing a trap and patch function to low power, cost conscious, and space constrained applications
GB2345992B (en) * 1999-03-10 2001-01-24 Elan Digital Systems Ltd Apparatus and method for handling peripheral device interrupts
US6625149B1 (en) * 1999-11-29 2003-09-23 Lucent Technologies Inc. Signaled receiver processing methods and apparatus for improved protocol processing
JP4693326B2 (ja) * 1999-12-22 2011-06-01 ウビコム インコーポレイテッド 組込み型プロセッサにおいてゼロタイムコンテクストスイッチを用いて命令レベルをマルチスレッド化するシステムおよび方法

Also Published As

Publication number Publication date
TW563029B (en) 2003-11-21
KR100734158B1 (ko) 2007-07-03
CN1309350A (zh) 2001-08-22
US6845419B1 (en) 2005-01-18
KR20010074544A (ko) 2001-08-04
JP4749556B2 (ja) 2011-08-17
JP2001229031A (ja) 2001-08-24

Similar Documents

Publication Publication Date Title
CN1251077C (zh) 实现数据处理中的中断的方法和数据处理系统
US5448732A (en) Multiprocessor system and process synchronization method therefor
US6192442B1 (en) Interrupt controller
CN1098487C (zh) 用于影响数据处理器中的顺序指令处理的方法和装置
US7853743B2 (en) Processor and interrupt controlling method
EP0203304B1 (en) Data processor controller
KR100617357B1 (ko) 태스크 스위칭에 의한 제로 오버헤드 컴퓨터 인터럽트
CN1316074A (zh) 中断/软件控制的线程处理
CN110928816B (zh) 一种片上可配置中断控制系统电路
JPH06290076A (ja) デバッグ装置
US5568643A (en) Efficient interrupt control apparatus with a common interrupt control program and control method thereof
US5072365A (en) Direct memory access controller using prioritized interrupts for varying bus mastership
CN1272720C (zh) 用于中断的动态优先权排序的方法及装置
CN1100294C (zh) 能防止程序故障的中央处理单元
CN1308828C (zh) 用于处理事件的方法和装置
KR20100068365A (ko) 토큰 프로토콜
CN1099080C (zh) 采用带有pico码的智能桥接器改进中断响应的系统和方法
JP2872259B2 (ja) マルチプロセッサシステム
JP3105554B2 (ja) 割込みコントローラ
KR101061133B1 (ko) 인터럽트 처리 시스템
WO2009004628A2 (en) Multi-core cpu
JPH044630B2 (enExample)
CN120631808A (zh) 中断控制器及电子设备
CN1720503A (zh) 在多线程处理器中用于高速线程间中断的方法和设备
CN120066579A (zh) 一种基于risc-v的中断及异常处理系统、方法及处理器

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: FREEDOM SEMICONDUCTORS CO.

Free format text: FORMER OWNER: MOTOROLA, INC.

Effective date: 20040820

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20040820

Address after: Texas in the United States

Applicant after: FreeScale Semiconductor

Address before: Illinois Instrunment

Applicant before: Motorola, Inc.

C14 Grant of patent or utility model
GR01 Patent grant
C56 Change in the name or address of the patentee

Owner name: FISICAL SEMICONDUCTOR INC.

Free format text: FORMER NAME: FREEDOM SEMICONDUCTOR CORP.

CP01 Change in the name or title of a patent holder

Address after: Texas in the United States

Patentee after: FREESCALE SEMICONDUCTOR, Inc.

Address before: Texas in the United States

Patentee before: FreeScale Semiconductor

ASS Succession or assignment of patent right

Owner name: INTEL CORP .

Free format text: FORMER OWNER: FISICAL SEMICONDUCTOR INC.

Effective date: 20150326

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20150326

Address after: American California

Patentee after: INTEL Corp.

Address before: Texas in the United States

Patentee before: FREESCALE SEMICONDUCTOR, Inc.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20060412

Termination date: 20180122