CN1229251A - 具有能减少功耗的动态数据放大器的半导体存储装置 - Google Patents
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Abstract
在半导体存储装置中包括:一对数据输入/输出线(GIO,/GIO),用来放大数据输入/输出线上的电压的数据放大器电路(11,12),和用来保持数据放大器电路的输出信号(D1,/D1)的数据保持电路(17,18)。数据确定电路(19)在数据保持电路保持数据放大器电路的输出信号以后,产生一个数据确定信号(SD)并将数据确定信号传输至数据放大器电路,从而使数据放大器电路的工作暂停。
Description
本发明涉及半导体存储装置，如动态随机存取存储器(DRAM)装置，更具体地说，涉及其中的动态数据放大器电路。
一般地说，在DRAM装置中，一个动态数据放大器被连接至数据输入/输出线，用来放大它们之间的电压差。
现有技术的动态数据放大电路是由电流镜像型差分放大器构成的。这一点将在下面详细说明。
但是，在上述现有技术的DRAM装置中，即使在差分放大器的输出信号被确定之后，差分放大器仍然是可以工作的。这样，功率耗散就增加了。特别是在1吉位的DRAM装置中，这种功率耗散的增加是不能忽略的。
本发明的一个目的是减少半导体存储器装置中的动态数据放大器电路的功耗。
根据本发明，在半导体存储装置中包括：一对数据输入/输出线、一个用来放大数据输入/输出线上的电压的数据放大器电路、以及一个用来保持数据放大器电路的输出信号数据保持电路，在数据保持电路保持数据放大器电路的输出信号以后，有一个数据确定电路产生一个数据确定信号，并将数据确定信号传输至数据放大器电路，由此暂停数据放大器电路的工作。
从下面参考附图并对比现有技术所提出的说明中，本发明将能更清楚地被理解，附图中：
图1是表示现有技术的半导体存储装置的电路图；
图2是图1的动态数据放大器电路的电路图；
图3是表示图2的动态数据器放大器电路工作的时序图；
图4是表示根据本发明的半导体存储装置第一实施例的电路图；
图5A是图4的动态数据放大器电路的电路图；
图5B是表示图5A中的电路的一种变型的电路图；
图6是表示图5A(5B)的动态数据器放大器电路工作的时序图；
图7是表示根据本发明的半导体存储装置第二实施例的电路图；以及
图8是表示根据本发明的半导体存储装置第三实施例的电路图。
在描述优选实施例之前，参看图1、2和3对现有半导体存储器做些说明。
在说明现有技术的DRAM(动态随机存储器)的图1中，全局输入/输出线GIO和/GIO与动态数据放大器1相连，而该数据放大器与读/写线RWB和/RWB相连。由P型沟道MOS(金属氧化物半导体)晶体管形成的均衡器2也与全局输入/输出线GIO和/GIO相连。也就是，当预充电信号PIO为低时，均衡器2导通，使得全局输入/输出线GIO和/GIO的电压相等。另外，箝拉电路3由两个N型沟道晶体管组成，与全局输入/输出线GIO和/GIO相连。也就是，当箝位起动信号PEN为高时，箝位电路3导通，使全局输入/输出线GIO和/GIO的电压被箝位。
此外，多对本地输入/输出线LIO1和/LIO1、LIO2和/LIO2、...通过传输门电路4-1，4-2，...与全局输入/输出线GIO和/GIO相连。例如，当控制信号C1为高时，本地输入/输出线LIO1和/LIO1分别被连接到全局输入/输出线GIO和/GIO。
每对本地输入/输出线例如LIO1和/LIO1，与存储体相连接，该存储体的组成是：列选择电路5；读出放大器6；每个连接到一个列选择电路5、本地传输门电路7-1和7-2、以及存储单元阵列8-1和8-2上的放大器；以及列选择驱动器9。每个列选择电路5由列选择驱动器9产生的列选择信号CSL起动，列选择驱动器9受到列译码器(未表示)控制。并且，读出放大器6由两个起动信号SAP和SAP起动。另外，传输门电路7-1和7-2中的一个分别由控制信号TG-1和TG-2操作，致使存储单元控制阵列8-1的位线BL和/BL或者存储单元阵列8-2的位线BL’和/BL’与读出放大器6相连。
在图2中是图1动态数据放大器1的详细电路图，电流镜像型差分放大器11被提供用于放大全局输入/输出线GIO和/GIO之间的电压。而且，电流镜像型差分放大器12也被提供用于放大输入/输出线GIO和/GIO之间的电压。差分放大器11和12的输出信号D1和/D1输送到反相器13a、13b、14a、和14b，这些反相器分别控制由一个P沟道MOS晶体管和一个N型沟道MOS晶体管形成的读/写总线驱动器15和16，从而控制读/写总线RWB和/RWB的电压。
差分放大器11和12的起动和无效由预充电信号PIO控制。
现在参看图3说明图2的动态数据放大器的操作。这里，假定图1的传输门电路4-1、列选择电路5和传输门电路7-1都被操作，所以，数据从存储单元阵列8-1被传输至输入/输出线GIO和/GIO。
首先，在时刻t1，当预充电信号PIO从高转变到低时，控制开始进入预充电方式，因此，全局输入/输出线GIO和/GIO上的电压是相等的。在这个情况下，箝位起动信号PEN使箝位电路3也与预充电信号PIO同步操作。另外，差分放大器11和12被预充电信号PIO禁止。所以差分放大器11和12的输出信号D1和/D1都变高。
其次，在时刻t2，当预充电信号PIO从低转变到高时，控制由预充电方式转变到数据放大器电路工作方式。也就是，差分放大器11和12由预充电信号PIO起动，因此，输出信号中只有一个变低(例如，/D1)。所以，读/写总线中的一个变低(例如，/RWB)。这个状态延续到预充电信号从高转变到低的时刻t3。
但是，在图1和图2的动态数据放大器1中，即使在差分放大器11和12的输出信号在时刻t0被确定以后，差分放大器11和12在时刻t3至时刻t4之间仍然能被预充电信号PIO起动工作，这就增加了功率耗散。换句话说，差分放大器11和12仅在时刻t1至时刻t2这个时间周期内暂停工作。
图4表示本发明的第一实施例，图中用一个动态数据放大器电路10代替图1中的动态数据放大器电路1。
图4中的动态数据放大器电路10的细节表示在图5A中，即触发器17和18作为数据保持装置，被分别用来代替图2中的反相器13a和14a。还有，“与”门电路19作为数据确定信号产生装置，被连接至触发器17和18。“与”门电路19也接收预充电信号PIO。
差分放大器11和12的起动和禁止，由“与”门19产生的数据确定信号SD控制，而不是由预充电信号PIO控制。
更详细地说，触发器17是由两个交叉耦合的“与非”门电路171和172构成的，其中，“与非”门电路171的输出信号D2，经过一个延迟电路173被送至“与非”门电路172的一个输入端，而“与非”门电路172的输出信号D3，则直接被送至“与非”门电路171的一个输入端。“与非”门电路171的另一个输入端作为触发器17的置位端，接收差分放大器11的输出信号D1，“与非”门电路172的另一个输入端作为触发器17的复位端，接收预充电信号PIO。
另一方面，触发器18是由两个交叉耦合的“与非”门电路181和182构成的，其中，“与非”门电路181的输出信号D2，经过一个延迟电路183被送至“与非”门电路182的一个输入端，而“与非”门电路182的输出信号/D3则直接被送至“与非”门电路181的一个输入端。“与非”门电路181的另一个输入端作为触发器18的置位端，接收差分放大器12的输出信号/D1，“与非”门电路182的另一个输入端作为触发器18的复位端，接收预充电信号PIO。
请注意，如图5B所示，如果延迟电路173(183)通过反相器13b(14b)和反相器13c(14c)连接到“与非”门电路171(181)，则该延迟电路173(183)可以减小尺寸。
现在参考图6解释图5A(5B)的动态数据放大器电路10的操作。这里，假设图4中的传输门电路4-1、列选择电路5和传输门电路7-1都起动操作，使得数据从存储单元阵列8-1被传输至全局输入/输出线GIO和/GIO。
首先，在时刻t1，当预充电信号PIO从高转变到低时，控制开始进入预充电方式，因此，全局输入/输出线GIO和/GIO上的电压是相等的。在这种情况下，箝位起动信号PEN使箝位电路8也与预充电信号PIO同步操作。另外，预充电信号PIO使数据确定信号SD变低，所以差分放大器11和12被数据确定信号SD禁止。差分放大器11和12的输出信号D1和/D1因而都变高。在这种情况下，注意“与非”门电路172和182的输出信号D3和/D3也都是高，所以，差分放大器11和12的输出信号D1和/D1使“与非”门电路171和181的输出信号D2和/D2变低。
其次，在时刻t2，当预充电信号PIO从低转变到高时，控制方式由预充电方式转变到数据放大器电路工作方式。也就是，数据确定信号SD从低转变到高，所以，差分放大器11和12由数据确定信号SD起动。因此，输出信号中只有一个变低(例如，/D1)。结果，“与非”门电路181的输出信号/D2变高，它使读/写总线驱动器16导通。
其次，在经过由延迟电路183确定的时间周期τ以后的时刻t3，“与非”门电路181的输出信号/D2到达“与非”门电路182，致使“与非”门电路182的输出信号/D3变低，因此，使数据确定信号SD在时刻t4从高转变为低。
当数据确定信号SD从高转变为低时，差分放大器11和12被禁止，随之，差分放大器12的输出信号/D1从低转变高。
在图4和图5的动态数据放大器电路10中，在差分放大器11和12的输出信号D1和/D1在时刻t4被确定以后，差分放大器11和12在从时刻t4到t5过段时间内，被数据确定信号SD禁止，这就减少了功率耗散。换句话说，差分放大器11和12在从时刻t4至时刻t1’这面时间周期内，在预充电信号PIO再次从低转变为高之前，暂停工作。
在图7中表示的是本发明的第二实施例，一个由N沟道MOS晶体管形成的的均衡器2’被用来代替图4中的均衡器2，并且在图4的元件上加了一个控制均衡器2’的“与非”门电路21。“与非”门电路21除了接收预充电信号PIO以外，还从动态数据放大器电路10接收数据确定信号SD。所以当动态数据放大器10的差分放大器11和12的工作暂停时，全局输入/输出线GIO和/GIO得以均衡，使动态数据放大器电路10的工作稳定。
在图8中表示的是本发明的第三个实施例，图7中的数据确定信号SD也被送至列选择驱动器9。当数据确定信号SD为低时，列选择电路5的工作是不必要的。所以在这种情况下，列选择驱动器9的工作暂停，以使列选择电路5的工作停止。结果，从箝位电路3经过列选择电路5到读出放大器6的渗透电流被截止，这进一步减少了功率耗散。
如上所述，根据本发明，由于在动态数据放大器电路中产生的数据确定信号使动态数据放大器电路的差分放大器工作暂停，所以功率耗散能够减少。
Claims (10)
1、一种半导体存储装置包括：
一对数据输入/输出线GIO和/GIO；
一个数据放大器电路(11，12)，连接到所述数据输入/输出线，用来放大所述数据输入/输出线上的电压；
一个数据保持电路(17，18)，连接到所述数据放大器电路，用来保持所述数据放大器电路的输出信号(D1，/D1)；以及
一个数据确定电路(19)，连接在所述数据保持电路和所述数据放大器电路之间，用于在所述数据保持电路保持所述数据放大器的输出信号之后，产生一个数据确定信号(SD)，并将所述数据确定信号传输至所述数据放大器电路，使所述数据放大器电路的工作暂停。
2、如权利要求1中所述的装置，其特征在于，在所述数据保持电路保持所述数据放大器电路的输出信号之后，经过一个确定的时间周期(τ)，所述数据确定电路产生所述数据确定信号。
3、如权利要求1中所述的装置，其特征在于，所述数据保持电路和所述数据确定电路，在接收到一个预充电信号(PIO)时被复位。
4、如权利要求1中所述的装置，其特征在于，所述数据放大器电路包括：
第一电流镜像型差分放大器(11)，用于对所述数据输入/输出线的输出电压之间的第一差量进行放大；以及
第二电流镜像型差分放大器(12)，用于对与所述数据输入/输出线的输出电压之间的所述第一差量反相的第二差量进行放大；
所述第一和第二电流镜像型差分放大器由所述数据确定电路起动。
5、如权利要求3中所述的装置，其特征在于，其中所述数据保持电路包括：
第一触发器(17)，连接至所述第一电流镜像型差分放大器的输出端，并有一个用于接收所述第一电流镜像型差分放大器的输出信号(D1)的置位端，和一个用于接收预充电信号(PIO)的复位端；以及
第二触发器(18)，连接至所述第二电流镜像型差分放大器的输出端，并有一个用于接收所述第二电流镜像型差分放大器的输出信号(/D1)的置位端，和一个用于接收所述预充电信号的复位端。
6、如权利要求5中所述的装置，其特征在于，其中第一和第二触发器各自包括：
第一“与非”门电路(171，181)，具有与所述置位端相连的第一输入端和第二输入端；
延迟电路(173，183)，与所述第一“与非”门电路相连；以及
第二“与非”门电路(172，182)，具有接收所述预充电信号的第一输入和与所述延迟电路相连的第二输入端。
7、如权利要求6中所述的装置，其特征在于，其中所述数据确定电路与所述第一和第二触发器的所述第二“与非”门电路的输出端相连。
8、如权利要求6中所述的装置，其特征在于，其中所述数据确定电路由一个“与”门电路组成，它具有分别与所述第一和第二触发器的所述第二“与非”门电路的输出端相连接的第一和第二输入端，以及用来接收所述预充电信号的第三输入端。
9、如权利要求1中所述的装置，其特征在于，其中还包括：
均衡器(2’)，它与所述数据输入/输出线相连，用来均衡所述数据输入/输出线上的电压；以及
控制电路(21)，它与所述数据确定电路和所述均衡器相连，用于根据所述数据确定信号和所述预充电信号，对所述均衡器进行操作。
10、如权利要求1中所述的装置，其特征在于，其中还包括：
存储单元(8-1，8-2)；
列选择电路(5)，它操作性地与所述数据输入/输出线相连，用于将数据从所述存储单元向所述数据输入/输出线传输；以及
列选择驱动器(9)，每个列选择驱动器与所述数据确定电路和所述列选择电路之一相连，用于驱动所述列选择电路，
所述列选择驱动器根据所述数据确定信号而动作。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP062636/98 | 1998-03-13 | ||
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| JP062636/1998 | 1998-03-13 |
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| TW (1) | TW440844B (zh) |
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| CN101192447B (zh) * | 2006-11-28 | 2010-05-12 | 中芯国际集成电路制造(上海)有限公司 | 动态随机存储器 |
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| KR960001860B1 (ko) * | 1993-06-05 | 1996-02-06 | 삼성전자주식회사 | 반도체집적회로의 데이타 입출력선 센싱회로 |
| JP2663838B2 (ja) * | 1993-07-27 | 1997-10-15 | 日本電気株式会社 | 半導体集積回路装置 |
| US5619466A (en) * | 1996-01-19 | 1997-04-08 | Sgs-Thomson Microelectronics, Inc. | Low-power read circuit and method for controlling a sense amplifier |
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1999
- 1999-03-12 US US09/266,731 patent/US6009020A/en not_active Expired - Fee Related
- 1999-03-12 TW TW088103920A patent/TW440844B/zh active
- 1999-03-13 KR KR1019990008493A patent/KR100295126B1/ko not_active IP Right Cessation
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101192447B (zh) * | 2006-11-28 | 2010-05-12 | 中芯国际集成电路制造(上海)有限公司 | 动态随机存储器 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11260057A (ja) | 1999-09-24 |
| US6009020A (en) | 1999-12-28 |
| KR19990077860A (ko) | 1999-10-25 |
| CN1169158C (zh) | 2004-09-29 |
| TW440844B (en) | 2001-06-16 |
| KR100295126B1 (ko) | 2001-07-12 |
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Effective date of registration: 20030615 Address after: Kanagawa, Japan Applicant after: NEC Corp. Address before: Tokyo, Japan Applicant before: NEC Corp. |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CI01 | Publication of corrected invention patent application |
Correction item: Patentee Correct: Scarlett Yixi electronic Limited by Share Ltd False: NEC Corp. Number: 39 Page: 503 Volume: 20 Correction item: Address Correct: Kanagawa False: Tokyo, Japan, Japan Number: 39 Page: 503 Volume: 20 |
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| CI03 | Correction of invention patent |
Correction item: Patentee Correct: Scarlett Yixi electronic Limited by Share Ltd False: NEC Corp. Number: 39 Page: The title page Volume: 20 Correction item: Address Correct: Kanagawa False: Tokyo, Japan, Japan Number: 39 Page: The title page Volume: 20 |
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| COR | Change of bibliographic data |
Free format text: CORRECT: PATENTEE ADDRESS; FROM: NIPPON ELECTRIC CO., LTD. TOKYO, JAPAN TO: NEC ELECTRONICS TAIWAN LTD. KANAGAWA, JAPAN |
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| ERR | Gazette correction |
Free format text: CORRECT: PATENTEE ADDRESS; FROM: NIPPON ELECTRIC CO., LTD. TOKYO, JAPAN TO: NEC ELECTRONICS TAIWAN LTD. KANAGAWA, JAPAN |
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| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |