TW344048B - Method for controlling write path of semiconductor memory system with an address transition detector - Google Patents

Method for controlling write path of semiconductor memory system with an address transition detector

Info

Publication number
TW344048B
TW344048B TW085114866A TW85114866A TW344048B TW 344048 B TW344048 B TW 344048B TW 085114866 A TW085114866 A TW 085114866A TW 85114866 A TW85114866 A TW 85114866A TW 344048 B TW344048 B TW 344048B
Authority
TW
Taiwan
Prior art keywords
data
semiconductor memory
memory system
write path
writing
Prior art date
Application number
TW085114866A
Other languages
Chinese (zh)
Inventor
Jaiwhan You
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of TW344048B publication Critical patent/TW344048B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Abstract

A method for controlling the write path of a semiconductor memory system, which comprises the following steps: detecting and amplifying data from a plurality of memory cells through the detection of a detection amplifier connected to a pair of data input/output (I/O) lines; writing the data by a data line driver connected to the pair of data I/O lines; and performing a reading or writing operation through detection of an address transmission by an address transmission detector, in which the address transmission detector is enabled only during a writing period thereby controlling the time for writing the data into the memory cells.
TW085114866A 1995-12-20 1996-12-02 Method for controlling write path of semiconductor memory system with an address transition detector TW344048B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950052596A KR100200919B1 (en) 1995-12-20 1995-12-20 Write road control circuit of semiconductor memory device using address transition sensor

Publications (1)

Publication Number Publication Date
TW344048B true TW344048B (en) 1998-11-01

Family

ID=19441769

Family Applications (1)

Application Number Title Priority Date Filing Date
TW085114866A TW344048B (en) 1995-12-20 1996-12-02 Method for controlling write path of semiconductor memory system with an address transition detector

Country Status (3)

Country Link
JP (1) JPH09282881A (en)
KR (1) KR100200919B1 (en)
TW (1) TW344048B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100590855B1 (en) 2003-10-14 2006-06-19 주식회사 하이닉스반도체 Semiconductor memory device for reducing current consumption
KR100702304B1 (en) * 2005-01-12 2007-03-30 주식회사 하이닉스반도체 Setup time control device
KR100712539B1 (en) * 2005-11-23 2007-04-30 삼성전자주식회사 Column decoder of semiconductor memory device and method of generating column selection line signal in semiconductor memory device

Also Published As

Publication number Publication date
JPH09282881A (en) 1997-10-31
KR100200919B1 (en) 1999-06-15
KR970051139A (en) 1997-07-29

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees