CN1225509A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN1225509A
CN1225509A CN98126502A CN98126502A CN1225509A CN 1225509 A CN1225509 A CN 1225509A CN 98126502 A CN98126502 A CN 98126502A CN 98126502 A CN98126502 A CN 98126502A CN 1225509 A CN1225509 A CN 1225509A
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松田修一
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NEC Corp
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Abstract

配有TAB(载带自动键合)带的半导体器件。在TAB带的一个表面上形成布线的预定图形,具有在公共布线层中的两个或更多个芯片电极的半导体芯片设置于TAB带的另一个表面上。布线和芯片电极通过凸点电连接,该凸点以与芯片电极相面对的关系设置于通孔中。这防止了芯片电极与凸点之间连接失效。

Description

半导体器件
本发明涉及半导体器件，特别涉及可防止在芯片电极和布线基片之间的任何失效连接的半导体器件。
目前已知称为芯片尺寸封装(以下称为CSP)的半导体器件，其尺寸几乎减小到半导体芯片的尺寸。
按照用于安装半导体芯片的插入件的种类将常规的CSP分成若干组。该插入件例如是薄膜载体。
可是，如果在加热条件下模压薄膜载体上的布线和半导体芯片上的芯片电极，使它们相互连接，那么由于可能的应力，这种接点有分离的趋势，从而引起接点电断开。
本说明书的附图7是展示常规的普通型CSP的透视图。
如图7所示，半导体芯片1设置于TAB(载带自动键合)带2上，TAB带2是薄膜载体，芯片1的尺寸大体等于TAB带2的尺寸。
通过在TAB带2的通孔中的未示出的凸点，半导体芯片1的铝(Al)芯片电极(未示出)与凸点9电连接。用诸如环氧树脂之类的密封树脂8密封整个半导体芯片1。
图8是沿图7中的线Ⅷ-Ⅷ截取的局部且放大的剖面图。
在图8中，TAB带2由作为基底的聚酰亚胺带2b和形成在聚酰亚胺带2b上的铜箔布线2a构成，聚酰亚胺带2b用作薄膜载体(布线基片)，在其上将支撑半导体芯片1。
通过在聚酰亚胺带2b的通孔中汽相淀积铜，按预定的布线图形预先在聚酰亚胺带2b上形成布线2a。通过镀敷，在各凸点6的暴露表面上形成另一个镍(Ni)或金(Au)的凸点5。
芯片电极4与半导体芯片1中的布线3电连接，用芯片覆盖膜12覆盖芯片的表面，以便露出芯片电极4。
这样制造的薄膜载体用于如下的半导体封装装配：
首先，凸点5与芯片电极4按相面对的关系对准，使用键合工具在加热或超声波下使布线2a贴压在凸点6上。结果，各凸点5变形，在接触表面上形成金-铝(Au-Al)合金，从而在受热情况下凸点5与相应的芯片电极4相互贴压。然后，用粘接材料11使半导体芯片1和芯片覆盖膜12相互粘接在一起，于是完成半导体封装。同时，用于防腐蚀的焊料保护膜10涂敷在露出的布线2a表面上。
可是，按照该常规技术，当在加热下加压使凸点5与芯片电极4互连之后，因TAB带2可能的应力，这种接点有分离的趋势，结果，在半导体封装装配之后的检测过程中将发现成为失效连接的分离的接点。
鉴于上述问题，本发明的目的在于提供一种在芯片电极和凸点之间无任何失效连接的半导体器件。
按照本发明的第一方案，通过这样的半导体器件实现上述目的，该半导体器件包括：布线基片，具有在一个表面上形成的布线的预定图形；半导体芯片，设置于布线基片的另一个表面上，并具有在公共布线层中的两个或更多个芯片电极；布线基片带有多个通孔：和以与芯片电极相面对的关系分别形成于通孔中的多个凸点，凸点与布线和芯片电极电连接。
按照本发明的第二方案，通过另一种半导体器件实现上述目的，该半导体器件包括：布线基片，具有在一个表面上形成的布线的预定图形；半导体芯片，设置于布线基片的上述表面上，并具有在公共布线层中的两个或更多个芯片电极；和分别以与芯片电极相面对的关系设置于布线上的多个凸点，凸点与布线和芯片电极电连接。
按照本发明的第三方案，通过再一种半导体器件实现上述目的，该半导体器件包括：TAB(载带自动键合)带，具有在一个表面上形成的布线的预定图形；半导体芯片，设置于TAB带的另一个表面上，并具有在公共布线层中的两个或更多个芯片电极；TAB带带有多个通孔；和分别以与芯片电极相面对的关系形成于通孔中的多个凸点，凸点与布线和芯片电极电连接。
按照本发明的第四方案，通过又一种半导体器件实现上述目的，该半导体器件包括：TAB带，具有在一个表面上形成的布线的预定图形；半导体芯片，设置于TAB带的上述表面上，并具有在公共布线层中的两个或更多个芯片电极；和分别以与芯片电极相面对的关系设置于通孔中的多个凸点，凸点与布线和芯片电极电连接。
在本发明第一至第四方案的任一个的半导体器件中，作为优选特征，从半导体芯片的边缘朝向其内侧排列芯片电极。
作为另一个优选特征，芯片电极与半导体芯片的边缘平行地排列，并且布线在至少一个位置弯折。
作为另一个优选特征，芯片电极与半导体芯片的边缘平行地排列，并且布线具有其宽度大于芯片电极之间的内电极距离的端部。
作为另一个优选特征，芯片电极包括选自半导体芯片的接地端、电源接线端和信号接线端中的至少一种接线端。
在本发明的半导体器件的结构中，器件具有至少两组芯片接线端和用于公共布线层的凸点，因而，如果在一个位置的接点发生分离，那其余的接点仍可保持不被分离。因此该半导体封装无任何连接失效。
通过下面参照附图所作的说明，将更加明了本发明的上述和其它目的、优点和特征，其中：
图1是本发明第一实施例的半导体器件的局部平面图；
图2(a)和2(b)是沿图1中线Ⅱ-Ⅱ截取的局部剖面图，表示图1的半导体器件的制造工艺；
图3是表示应用图1中结构的半导体封装的局部剖面图；
图4是本发明第二实施例的半导体器件的局部平面图；
图5是本发明第三实施例的半导体器件的局部平面图；
图6是本发明第四实施例的半导体器件的局部平面图；
图7是常规的普通型CSP(芯片尺寸封装)的透视图；和
图8是沿图7中线Ⅷ-Ⅷ截取的局部且放大的剖面图。
本发明的原理在用于半导体器件上时特别有用，下面参照附图说明本发明的各种优选实施例。
图1是本发明第一实施例的半导体器件的局部平面图。
图1中，与图8中的部件或元件相似的部分被标以相同的参考标号。半导体芯片1设置于作为薄膜载体(布线基片)的TAB(载带自动键合)带2上，芯片1的尺寸大体与TAB带2的尺寸相等。两个为铝(Al)的芯片电极4连接于半导体芯片1的公用布线层3上。
半导体芯片1的各芯片电极4与TAB带2上的公用布线2a电连接，在布线2a的一端形成焊盘2c，在焊盘2c上要粘附凸点。在TAB带2上按预定图形形成铜布线2a。
下面参照图2(a)和2(b)说明第一实施例的半导体器件的制造工艺方法。
图2(a)和2(b)是沿图1的线Ⅱ-Ⅱ截取的剖面图，表示制造图1的半导体器件的工艺方法。
首先，在图2(a)中，用作薄膜载体的TAB带2由将要作为基底的聚酰亚胺带2b和形成在聚酰亚胺带2b上的铜箔布线2a构成。接着，凸点5与芯片电极4对准，用两个键合工具7通过加热或施加超声波使布线2a贴压在凸点6上。这样，将半导体芯片1装配于TAB带2上。
如图2(b)所示，键合工具7的压力使各凸点5变形，在接触表面上形成金-铝(Au·Al)合金，从而在受热情况下凸点5与芯片电极4相互贴压在一起。
为了更牢固的接点强度，在相应于凸点5和6的每一组上可设置三个或更多个芯片电极4。
图3是表示半导体封装的局部剖面图，图1的结构已装入其中。
在图3中，通过凸点5,6的各组，布线2a在两个位置进行连接，其一个与芯片电极4的每一个连接。在布线2a的一端形成焊盘2c，在其上安装用于与封装基片连接的大凸点9。
图4和5是展示本发明第二和第三实施例的局部平面图。
在图4和5中，与图3中的部件或元件相似的部分被标以相同的参考标号。在第二和第三实施例中，两个芯片电极4与一根布线连接，并且相同的布线层3与半导体芯片1的边缘平行。
在图4的第二实施例中，在另一端部弯折(成直角)的布线2a与两个芯片电极4连接。在图5的第三实施例中，布线2a具有其宽度大于两个芯片电极4之间距离的端部。当然，在这两种情况下，通过凸点(未示出)布线2a与芯片电极4互连。
本发明可用于任何接线端，例如半导体芯片1的电源接线端(VCC)，接地端(GND)和信号接线端。如果用于接地端，可获得下列结果。
即，通常，半导体芯片配有多个电源接线端和多个接地端，因此，如果在一个接点发生连接失效，那么另一个接点保持闭合，可充分地执行其原定功能。可是，如果在用户进行的产品检验期间发现即使一个接点连接失效，他或她就可能会怀疑其技术水平和制造者的技术水平。将本发明用于至少电源接线端和接地端，就可避免这样的危险。尽管，其不足是由芯片电极占据的区域会增加，但是，只要本发明仅用于电源接线端和接地端，那么其可能的影响便小得可忽略不计。此外，由于可实现可靠的连接，即使有增加芯片电极占据面积的某些冒险，将本发明应用于电源接线端和接地端也是值得的。
在图示的实施例中，凸点5设置于半导体芯片1的背面。另一方面，也可如图6所示那样，可以按相互面对的关系设置布线2a与凸点5。
按照本发明的半导体器件，在布线基片上的布线与连接到半导体芯片的公共布线层上的两个或多个芯片电极连接，因此，即使发生单个接点的断开，另外的接点仍维持闭合。因而作为整体半导体器件无任何连接失效。
显然，本发明并不限于上述实施例，可以进行改变和修改，而不会脱离本发明的范围和实质。

Claims (20)

1．半导体器件，包括：
布线基片，具有在一个表面上形成的布线的预定图形；
半导体芯片，设置于所述布线基片的另一个表面上，并具有在公共布线层中的两个或更多个芯片电极；
所述布线基片带有多个通孔：和
以与所述芯片电极相面对的关系分别形成于所述通孔中的多个凸点，所述凸点与所述布线和所述芯片电极电连接。
2．如权利要求1所述的半导体器件，其特征在于，从所述半导体芯片的边缘朝向其内侧排列所述芯片电极。
3．如权利要求1所述的半导体器件，其特征在于，所述芯片电极与所述半导体芯片的边缘平行地排列，并且所述布线在至少一个位置弯折。
4．如权利要求1所述的半导体器件，其特征在于，所述芯片电极与所述半导体芯片的边缘平行地排列，并且所述布线具有其宽度大于所述芯片电极之间的内电极距离的端部。
5．如权利要求1所述的半导体器件，其特征在于，所述芯片电极包括选自所述半导体芯片的接地端、电源接线端和信号接线端中的至少一种接线端。
6．半导体器件，包括：
布线基片，具有在一个表面上形成的布线的预定图形；
半导体芯片，设置于所述布线基片的上述表面上，并具有在公共布线层中的两个或更多个芯片电极；和
分别以与所述芯片电极相面对的关系设置于所述布线上的多个凸点，所述凸点与所述布线和所述芯片电极电连接。
7．如权利要求6所述的半导体器件，其特征在于，从所述半导体芯片的边缘朝向其内侧排列所述芯片电极。
8．如权利要求6所述的半导体器件，其特征在于，所述芯片电极与所述半导体芯片的边缘平行地排列，并且所述布线在至少一个位置弯折。
9．如权利要求6所述的半导体器件，其特征在于，所述芯片电极与所述半导体芯片的边缘平行地排列，并且所述布线具有其宽度大于所述芯片电极之间的内电极距离的端部。
10．如权利要求6所述的半导体器件，其特征在于，所述芯片电极包括选自所述半导体芯片的接地端、电源接线端和信号接线端中的至少一种接线端。
11．半导体器件，包括：
TAB(载带自动键合)带，具有在一个表面上形成的布线的预定图形；
半导体芯片，设置于所述TAB带的另一个表面上，并具有在公共布线层中的两个或更多个芯片电极；
所述TAB带带有多个通孔；和
分别以与所述芯片电极相面对的关系设置于所述通孔中的多个凸点，所述凸点与所述布线和所述芯片电极电连接。
12．如权利要求11所述的半导体器件，其特征在于，从所述半导体芯片的边缘朝向其内侧排列所述芯片电极。
13．如权利要求11所述的半导体器件，其特征在于，所述芯片电极与所述半导体芯片的边缘平行地排列，并且所述布线在至少一个位置弯折。
14．如权利要求11所述的半导体器件，其特征在于，所述芯片电极与所述半导体芯片的边缘平行地排列，并且所述布线具有其宽度大于所述芯片电极之间的内电极距离的端部。
15．如权利要求11所述的半导体器件，其特征在于，所述芯片电极包括选自所述半导体芯片的接地端、电源接线端和信号接线端中的至少一种接线端。
16．半导体器件，包括：
TAB带，具有在一个表面上形成的布线的预定图形；
半导体芯片，设置于所述TAB带的上述表面上，并具有在公共布线层中的两个或更多个芯片电极；和
分别以与所述芯片电极相面对的关系设置于所述通孔中的多个凸点，所述凸点与所述布线和所述芯片电极电连接。
17．如权利要求16所述的半导体器件，其特征在于，从所述半导体芯片的边缘朝向其内侧排列所述芯片电极。
18．如权利要求16所述的半导体器件，其特征在于，所述芯片电极与所述半导体芯片的边缘平行地排列，并且所述布线在至少一个位置弯折。
19．如权利要求16所述的半导体器件，其特征在于，所述芯片电极与所述半导体芯片的边缘平行地排列，并且所述布线具有其宽度大于所述芯片电极之间的内电极距离的端部。
20．如权利要求16所述的半导体器件，其特征在于，所述芯片电极包括选自所述半导体芯片的接地端、电源接线端和信号接线端中的至少一种接线端。
CN98126502A 1997-12-26 1998-12-28 半导体器件 Pending CN1225509A (zh)

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