CN1225509A - 半导体器件 - Google Patents

半导体器件 Download PDF

Info

Publication number
CN1225509A
CN1225509A CN98126502A CN98126502A CN1225509A CN 1225509 A CN1225509 A CN 1225509A CN 98126502 A CN98126502 A CN 98126502A CN 98126502 A CN98126502 A CN 98126502A CN 1225509 A CN1225509 A CN 1225509A
Authority
CN
China
Prior art keywords
chip
semiconductor device
wiring
electrode
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN98126502A
Other languages
English (en)
Inventor
松田修一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CN1225509A publication Critical patent/CN1225509A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

配有TAB(载带自动键合)带的半导体器件。在TAB带的一个表面上形成布线的预定图形,具有在公共布线层中的两个或更多个芯片电极的半导体芯片设置于TAB带的另一个表面上。布线和芯片电极通过凸点电连接,该凸点以与芯片电极相面对的关系设置于通孔中。这防止了芯片电极与凸点之间连接失效。

Description

半导体器件
本发明涉及半导体器件，特别涉及可防止在芯片电极和布线基片之间的任何失效连接的半导体器件。
目前已知称为芯片尺寸封装(以下称为CSP)的半导体器件，其尺寸几乎减小到半导体芯片的尺寸。
按照用于安装半导体芯片的插入件的种类将常规的CSP分成若干组。该插入件例如是薄膜载体。
可是，如果在加热条件下模压薄膜载体上的布线和半导体芯片上的芯片电极，使它们相互连接，那么由于可能的应力，这种接点有分离的趋势，从而引起接点电断开。
本说明书的附图7是展示常规的普通型CSP的透视图。
如图7所示，半导体芯片1设置于TAB(载带自动键合)带2上，TAB带2是薄膜载体，芯片1的尺寸大体等于TAB带2的尺寸。
通过在TAB带2的通孔中的未示出的凸点，半导体芯片1的铝(Al)芯片电极(未示出)与凸点9电连接。用诸如环氧树脂之类的密封树脂8密封整个半导体芯片1。
图8是沿图7中的线Ⅷ-Ⅷ截取的局部且放大的剖面图。
在图8中，TAB带2由作为基底的聚酰亚胺带2b和形成在聚酰亚胺带2b上的铜箔布线2a构成，聚酰亚胺带2b用作薄膜载体(布线基片)，在其上将支撑半导体芯片1。
通过在聚酰亚胺带2b的通孔中汽相淀积铜，按预定的布线图形预先在聚酰亚胺带2b上形成布线2a。通过镀敷，在各凸点6的暴露表面上形成另一个镍(Ni)或金(Au)的凸点5。
芯片电极4与半导体芯片1中的布线3电连接，用芯片覆盖膜12覆盖芯片的表面，以便露出芯片电极4。
这样制造的薄膜载体用于如下的半导体封装装配：
首先，凸点5与芯片电极4按相面对的关系对准，使用键合工具在加热或超声波下使布线2a贴压在凸点6上。结果，各凸点5变形，在接触表面上形成金-铝(Au-Al)合金，从而在受热情况下凸点5与相应的芯片电极4相互贴压。然后，用粘接材料11使半导体芯片1和芯片覆盖膜12相互粘接在一起，于是完成半导体封装。同时，用于防腐蚀的焊料保护膜10涂敷在露出的布线2a表面上。
可是，按照该常规技术，当在加热下加压使凸点5与芯片电极4互连之后，因TAB带2可能的应力，这种接点有分离的趋势，结果，在半导体封装装配之后的检测过程中将发现成为失效连接的分离的接点。
鉴于上述问题，本发明的目的在于提供一种在芯片电极和凸点之间无任何失效连接的半导体器件。
按照本发明的第一方案，通过这样的半导体器件实现上述目的，该半导体器件包括：布线基片，具有在一个表面上形成的布线的预定图形；半导体芯片，设置于布线基片的另一个表面上，并具有在公共布线层中的两个或更多个芯片电极；布线基片带有多个通孔：和以与芯片电极相面对的关系分别形成于通孔中的多个凸点，凸点与布线和芯片电极电连接。
按照本发明的第二方案，通过另一种半导体器件实现上述目的，该半导体器件包括：布线基片，具有在一个表面上形成的布线的预定图形；半导体芯片，设置于布线基片的上述表面上，并具有在公共布线层中的两个或更多个芯片电极；和分别以与芯片电极相面对的关系设置于布线上的多个凸点，凸点与布线和芯片电极电连接。
按照本发明的第三方案，通过再一种半导体器件实现上述目的，该半导体器件包括：TAB(载带自动键合)带，具有在一个表面上形成的布线的预定图形；半导体芯片，设置于TAB带的另一个表面上，并具有在公共布线层中的两个或更多个芯片电极；TAB带带有多个通孔；和分别以与芯片电极相面对的关系形成于通孔中的多个凸点，凸点与布线和芯片电极电连接。
按照本发明的第四方案，通过又一种半导体器件实现上述目的，该半导体器件包括：TAB带，具有在一个表面上形成的布线的预定图形；半导体芯片，设置于TAB带的上述表面上，并具有在公共布线层中的两个或更多个芯片电极；和分别以与芯片电极相面对的关系设置于通孔中的多个凸点，凸点与布线和芯片电极电连接。
在本发明第一至第四方案的任一个的半导体器件中，作为优选特征，从半导体芯片的边缘朝向其内侧排列芯片电极。
作为另一个优选特征，芯片电极与半导体芯片的边缘平行地排列，并且布线在至少一个位置弯折。
作为另一个优选特征，芯片电极与半导体芯片的边缘平行地排列，并且布线具有其宽度大于芯片电极之间的内电极距离的端部。
作为另一个优选特征，芯片电极包括选自半导体芯片的接地端、电源接线端和信号接线端中的至少一种接线端。
在本发明的半导体器件的结构中，器件具有至少两组芯片接线端和用于公共布线层的凸点，因而，如果在一个位置的接点发生分离，那其余的接点仍可保持不被分离。因此该半导体封装无任何连接失效。
通过下面参照附图所作的说明，将更加明了本发明的上述和其它目的、优点和特征，其中：
图1是本发明第一实施例的半导体器件的局部平面图；
图2(a)和2(b)是沿图1中线Ⅱ-Ⅱ截取的局部剖面图，表示图1的半导体器件的制造工艺；
图3是表示应用图1中结构的半导体封装的局部剖面图；
图4是本发明第二实施例的半导体器件的局部平面图；
图5是本发明第三实施例的半导体器件的局部平面图；
图6是本发明第四实施例的半导体器件的局部平面图；
图7是常规的普通型CSP(芯片尺寸封装)的透视图；和
图8是沿图7中线Ⅷ-Ⅷ截取的局部且放大的剖面图。
本发明的原理在用于半导体器件上时特别有用，下面参照附图说明本发明的各种优选实施例。
图1是本发明第一实施例的半导体器件的局部平面图。
图1中，与图8中的部件或元件相似的部分被标以相同的参考标号。半导体芯片1设置于作为薄膜载体(布线基片)的TAB(载带自动键合)带2上，芯片1的尺寸大体与TAB带2的尺寸相等。两个为铝(Al)的芯片电极4连接于半导体芯片1的公用布线层3上。
半导体芯片1的各芯片电极4与TAB带2上的公用布线2a电连接，在布线2a的一端形成焊盘2c，在焊盘2c上要粘附凸点。在TAB带2上按预定图形形成铜布线2a。
下面参照图2(a)和2(b)说明第一实施例的半导体器件的制造工艺方法。
图2(a)和2(b)是沿图1的线Ⅱ-Ⅱ截取的剖面图，表示制造图1的半导体器件的工艺方法。
首先，在图2(a)中，用作薄膜载体的TAB带2由将要作为基底的聚酰亚胺带2b和形成在聚酰亚胺带2b上的铜箔布线2a构成。接着，凸点5与芯片电极4对准，用两个键合工具7通过加热或施加超声波使布线2a贴压在凸点6上。这样，将半导体芯片1装配于TAB带2上。
如图2(b)所示，键合工具7的压力使各凸点5变形，在接触表面上形成金-铝(Au·Al)合金，从而在受热情况下凸点5与芯片电极4相互贴压在一起。
为了更牢固的接点强度，在相应于凸点5和6的每一组上可设置三个或更多个芯片电极4。
图3是表示半导体封装的局部剖面图，图1的结构已装入其中。
在图3中，通过凸点5,6的各组，布线2a在两个位置进行连接，其一个与芯片电极4的每一个连接。在布线2a的一端形成焊盘2c，在其上安装用于与封装基片连接的大凸点9。
图4和5是展示本发明第二和第三实施例的局部平面图。
在图4和5中，与图3中的部件或元件相似的部分被标以相同的参考标号。在第二和第三实施例中，两个芯片电极4与一根布线连接，并且相同的布线层3与半导体芯片1的边缘平行。
在图4的第二实施例中，在另一端部弯折(成直角)的布线2a与两个芯片电极4连接。在图5的第三实施例中，布线2a具有其宽度大于两个芯片电极4之间距离的端部。当然，在这两种情况下，通过凸点(未示出)布线2a与芯片电极4互连。
本发明可用于任何接线端，例如半导体芯片1的电源接线端(VCC)，接地端(GND)和信号接线端。如果用于接地端，可获得下列结果。
即，通常，半导体芯片配有多个电源接线端和多个接地端，因此，如果在一个接点发生连接失效，那么另一个接点保持闭合，可充分地执行其原定功能。可是，如果在用户进行的产品检验期间发现即使一个接点连接失效，他或她就可能会怀疑其技术水平和制造者的技术水平。将本发明用于至少电源接线端和接地端，就可避免这样的危险。尽管，其不足是由芯片电极占据的区域会增加，但是，只要本发明仅用于电源接线端和接地端，那么其可能的影响便小得可忽略不计。此外，由于可实现可靠的连接，即使有增加芯片电极占据面积的某些冒险，将本发明应用于电源接线端和接地端也是值得的。
在图示的实施例中，凸点5设置于半导体芯片1的背面。另一方面，也可如图6所示那样，可以按相互面对的关系设置布线2a与凸点5。
按照本发明的半导体器件，在布线基片上的布线与连接到半导体芯片的公共布线层上的两个或多个芯片电极连接，因此，即使发生单个接点的断开，另外的接点仍维持闭合。因而作为整体半导体器件无任何连接失效。
显然，本发明并不限于上述实施例，可以进行改变和修改，而不会脱离本发明的范围和实质。

Claims (20)

1．半导体器件，包括：
布线基片，具有在一个表面上形成的布线的预定图形；
半导体芯片，设置于所述布线基片的另一个表面上，并具有在公共布线层中的两个或更多个芯片电极；
所述布线基片带有多个通孔：和
以与所述芯片电极相面对的关系分别形成于所述通孔中的多个凸点，所述凸点与所述布线和所述芯片电极电连接。
2．如权利要求1所述的半导体器件，其特征在于，从所述半导体芯片的边缘朝向其内侧排列所述芯片电极。
3．如权利要求1所述的半导体器件，其特征在于，所述芯片电极与所述半导体芯片的边缘平行地排列，并且所述布线在至少一个位置弯折。
4．如权利要求1所述的半导体器件，其特征在于，所述芯片电极与所述半导体芯片的边缘平行地排列，并且所述布线具有其宽度大于所述芯片电极之间的内电极距离的端部。
5．如权利要求1所述的半导体器件，其特征在于，所述芯片电极包括选自所述半导体芯片的接地端、电源接线端和信号接线端中的至少一种接线端。
6．半导体器件，包括：
布线基片，具有在一个表面上形成的布线的预定图形；
半导体芯片，设置于所述布线基片的上述表面上，并具有在公共布线层中的两个或更多个芯片电极；和
分别以与所述芯片电极相面对的关系设置于所述布线上的多个凸点，所述凸点与所述布线和所述芯片电极电连接。
7．如权利要求6所述的半导体器件，其特征在于，从所述半导体芯片的边缘朝向其内侧排列所述芯片电极。
8．如权利要求6所述的半导体器件，其特征在于，所述芯片电极与所述半导体芯片的边缘平行地排列，并且所述布线在至少一个位置弯折。
9．如权利要求6所述的半导体器件，其特征在于，所述芯片电极与所述半导体芯片的边缘平行地排列，并且所述布线具有其宽度大于所述芯片电极之间的内电极距离的端部。
10．如权利要求6所述的半导体器件，其特征在于，所述芯片电极包括选自所述半导体芯片的接地端、电源接线端和信号接线端中的至少一种接线端。
11．半导体器件，包括：
TAB(载带自动键合)带，具有在一个表面上形成的布线的预定图形；
半导体芯片，设置于所述TAB带的另一个表面上，并具有在公共布线层中的两个或更多个芯片电极；
所述TAB带带有多个通孔；和
分别以与所述芯片电极相面对的关系设置于所述通孔中的多个凸点，所述凸点与所述布线和所述芯片电极电连接。
12．如权利要求11所述的半导体器件，其特征在于，从所述半导体芯片的边缘朝向其内侧排列所述芯片电极。
13．如权利要求11所述的半导体器件，其特征在于，所述芯片电极与所述半导体芯片的边缘平行地排列，并且所述布线在至少一个位置弯折。
14．如权利要求11所述的半导体器件，其特征在于，所述芯片电极与所述半导体芯片的边缘平行地排列，并且所述布线具有其宽度大于所述芯片电极之间的内电极距离的端部。
15．如权利要求11所述的半导体器件，其特征在于，所述芯片电极包括选自所述半导体芯片的接地端、电源接线端和信号接线端中的至少一种接线端。
16．半导体器件，包括：
TAB带，具有在一个表面上形成的布线的预定图形；
半导体芯片，设置于所述TAB带的上述表面上，并具有在公共布线层中的两个或更多个芯片电极；和
分别以与所述芯片电极相面对的关系设置于所述通孔中的多个凸点，所述凸点与所述布线和所述芯片电极电连接。
17．如权利要求16所述的半导体器件，其特征在于，从所述半导体芯片的边缘朝向其内侧排列所述芯片电极。
18．如权利要求16所述的半导体器件，其特征在于，所述芯片电极与所述半导体芯片的边缘平行地排列，并且所述布线在至少一个位置弯折。
19．如权利要求16所述的半导体器件，其特征在于，所述芯片电极与所述半导体芯片的边缘平行地排列，并且所述布线具有其宽度大于所述芯片电极之间的内电极距离的端部。
20．如权利要求16所述的半导体器件，其特征在于，所述芯片电极包括选自所述半导体芯片的接地端、电源接线端和信号接线端中的至少一种接线端。
CN98126502A 1997-12-26 1998-12-28 半导体器件 Pending CN1225509A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP359478/97 1997-12-26
JP9359478A JP3065010B2 (ja) 1997-12-26 1997-12-26 半導体装置

Publications (1)

Publication Number Publication Date
CN1225509A true CN1225509A (zh) 1999-08-11

Family

ID=18464710

Family Applications (1)

Application Number Title Priority Date Filing Date
CN98126502A Pending CN1225509A (zh) 1997-12-26 1998-12-28 半导体器件

Country Status (6)

Country Link
US (1) US6794750B2 (zh)
EP (1) EP0928028A3 (zh)
JP (1) JP3065010B2 (zh)
KR (1) KR100349957B1 (zh)
CN (1) CN1225509A (zh)
TW (1) TW396467B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6077766A (en) * 1999-06-25 2000-06-20 International Business Machines Corporation Variable thickness pads on a substrate surface
JP3597754B2 (ja) 2000-04-24 2004-12-08 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
US7253510B2 (en) 2003-01-16 2007-08-07 International Business Machines Corporation Ball grid array package construction with raised solder ball pads
KR100510518B1 (ko) * 2003-01-30 2005-08-26 삼성전자주식회사 반도체 장치 및 반도체 장치의 패키지 방법
KR100541649B1 (ko) * 2003-09-03 2006-01-11 삼성전자주식회사 테이프 배선 기판과 그를 이용한 반도체 칩 패키지
KR100608364B1 (ko) * 2004-04-29 2006-08-08 주식회사 하이닉스반도체 반도체 칩 패키지
KR100805289B1 (ko) * 2005-08-22 2008-02-20 세이코 엡슨 가부시키가이샤 전기 영동 장치 및 전자 기기
TWM524553U (zh) * 2016-03-21 2016-06-21 Team Expert Man Consulting Service Ltd 半導體封裝結構

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5399898A (en) * 1992-07-17 1995-03-21 Lsi Logic Corporation Multi-chip semiconductor arrangements using flip chip dies
JPH0563029A (ja) * 1991-09-02 1993-03-12 Fujitsu Ltd 半導体素子
US5548091A (en) * 1993-10-26 1996-08-20 Tessera, Inc. Semiconductor chip connection components with adhesives and methods for bonding to the chip
JP2833996B2 (ja) * 1994-05-25 1998-12-09 日本電気株式会社 フレキシブルフィルム及びこれを有する半導体装置
US5635761A (en) * 1994-12-14 1997-06-03 International Business Machines, Inc. Internal resistor termination in multi-chip module environments
JPH08236586A (ja) * 1994-12-29 1996-09-13 Nitto Denko Corp 半導体装置及びその製造方法
US5707894A (en) * 1995-10-27 1998-01-13 United Microelectronics Corporation Bonding pad structure and method thereof
US5844317A (en) * 1995-12-21 1998-12-01 International Business Machines Corporation Consolidated chip design for wire bond and flip-chip package technologies
KR0182510B1 (ko) * 1996-02-17 1999-04-15 김광호 탭 테이프를 적용한 칩 스케일 패키지
US5686764A (en) * 1996-03-20 1997-11-11 Lsi Logic Corporation Flip chip package with reduced number of package layers
US5925930A (en) * 1996-05-21 1999-07-20 Micron Technology, Inc. IC contacts with palladium layer and flexible conductive epoxy bumps
US5952726A (en) * 1996-11-12 1999-09-14 Lsi Logic Corporation Flip chip bump distribution on die
US6441487B2 (en) * 1997-10-20 2002-08-27 Flip Chip Technologies, L.L.C. Chip scale package using large ductile solder balls
US6064114A (en) * 1997-12-01 2000-05-16 Motorola, Inc. Semiconductor device having a sub-chip-scale package structure and method for forming same

Also Published As

Publication number Publication date
US20020000654A1 (en) 2002-01-03
US6794750B2 (en) 2004-09-21
EP0928028A3 (en) 2000-06-28
KR19990063444A (ko) 1999-07-26
KR100349957B1 (ko) 2002-11-18
EP0928028A2 (en) 1999-07-07
JP3065010B2 (ja) 2000-07-12
TW396467B (en) 2000-07-01
JPH11191574A (ja) 1999-07-13

Similar Documents

Publication Publication Date Title
US7883993B2 (en) Semiconductor device with semiconductor chip and rewiring layer and method for producing the same
US6635960B2 (en) Angled edge connections for multichip structures
JP3011233B2 (ja) 半導体パッケージ及びその半導体実装構造
KR100537972B1 (ko) 집적 회로 패키지용 칩 스케일 볼 그리드 어레이
US6501157B1 (en) Substrate for accepting wire bonded or flip-chip components
US7229850B2 (en) Method of making assemblies having stacked semiconductor chips
US6984885B1 (en) Semiconductor device having densely stacked semiconductor chips
US7372131B2 (en) Routing element for use in semiconductor device assemblies
CA1078071A (en) Integrated circuit package
US20080042249A1 (en) Microelectronic package
US20040135243A1 (en) Semiconductor device, its manufacturing method and electronic device
KR20030029743A (ko) 플랙서블한 이중 배선기판을 이용한 적층 패키지
CN1239588A (zh) 带有通孔从焊球键合位置侧向偏移的tab带球栅阵列封装
US6992395B2 (en) Semiconductor device and semiconductor module having external electrodes on an outer periphery
US6090633A (en) Multiple-plane pair thin-film structure and process of manufacture
CN1225509A (zh) 半导体器件
CN1211000C (zh) 刚性挠性基板及使用该基板的照相机
US6285562B1 (en) Method of contacting a chip
CN1193186A (zh) 载体薄片和使用了载体薄片的集成电路装置
US20060278962A1 (en) Microelectronic loop packages
WO2002023592A2 (en) Method and apparatus for reducing ic die mass and thickness while improving strength characteristics
CN1076873C (zh) 集成芯片的封装及其所使用的连接部件
US20040232566A1 (en) Semiconductor device and method of manufacturing the same
US20050118791A1 (en) Method of manufacturing semiconductor device and system of manufacturing semiconductor device
JPS6329566A (ja) 半導体装置

Legal Events

Date Code Title Description
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
ASS Succession or assignment of patent right

Owner name: NEC ELECTRONICS TAIWAN LTD.

Free format text: FORMER OWNER: NIPPON ELECTRIC CO., LTD.

Effective date: 20030410

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20030410

Address after: Kanagawa, Japan

Applicant after: NEC Corp.

Address before: Tokyo, Japan

Applicant before: NEC Corp.

AD01 Patent right deemed abandoned
C20 Patent right or utility model deemed to be abandoned or is abandoned