CN1223249C - 低侧面的互联结构 - Google Patents

低侧面的互联结构 Download PDF

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CN1223249C
CN1223249C CNB00134286XA CN00134286A CN1223249C CN 1223249 C CN1223249 C CN 1223249C CN B00134286X A CNB00134286X A CN B00134286XA CN 00134286 A CN00134286 A CN 00134286A CN 1223249 C CN1223249 C CN 1223249C
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CN1299230A (zh
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黄荣丰
付嘉宇(音译)
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NXP USA Inc
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    • H05K3/3457Solder materials or compositions; Methods of application thereof
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Abstract

低侧面互联结构包括一个电子电路模块,这个电子电路模块具有多个安装区域和多个电气接触区域。多个安装区域与一个安装与互联表面隔开一第一距离,并且这个安装与互联表面与这个安装表面平行并且相互之间有一距离,这多个电气接触区域与这个安装与互联表面隔开一第二距离,第二距离比第一距离小。在安装区域和这个安装与互联表面之间使用了大的焊锡球,以形成一个固定的安装,并且小的焊锡部件被用于电气互联。

Description

低侧面的互联结构
技术领域
本发明涉及用于以一低侧面安装和互联电子电路模块的结构和方法。
背景技术
在当前的电子领域内,经常需要或者希望将电子电路固定地安装在支持和互联表面例如印刷电路板上,等等。但是,  在很多应用中,被安装模块的整体厚度是一个必须保持较低的关键参数。
用于在一个印刷电路板上实现这样一个模块安装的一个突出的方法和装置是称作一个球栅阵列(BGA)。BGA包括一个焊锡球阵列,这个焊锡球阵列均具有相同的相对大小直径。BGA是已知能够为具有大的输入/输出(I/O)数目的器件提供可靠的互联的方法。但是,其高度范围从15到35毫英寸,从而使器件的整体高度太大。
对I/O焊接使用金属焊盘可以将互联厚度减少到少于5毫英寸,这大大降低了被安装在一个印刷电路板上时这个器件的整体高度。金属焊盘的缺点是I/O的可靠性不是很好。因为低的焊锡高度,就没有足够的焊锡来释放因为这个模块和这个印刷电路板之间的热不匹配而引起的应力。
发明内容
本发明提供一种低侧面互联结构,其特征在于包括:一个电子电路模块,其具有一个安装表面,这个安装表面上具有多个相互隔开的安装区域和多个在该安装表面上形成的电气接触区域;一个支撑和互联表面,其与所述安装表面平行且隔开设置,该支撑和互联表面包括多个隔开的匹配支撑区域,每个所述匹配支撑区域位于在所述支撑和互联表面中形成的一个凹陷内;所述多个安装区域与所述支撑和互联表面的匹配支撑区域的隔开第一距离;和所述多个电气接触区域与所述支撑和互联表面隔开第二距离,该第二距离比第一距离小;多个电气连接件,其中的每一个位于所述电气接触区域中之一与所述支撑和互联表面之间。
所以,特别希望能够提供用于将模块安装在一个支撑和互联表面并且也能够实现一个侧面较低的最终结构的结构和一个方法。
附图说明
图1是使用一个众所周知的球栅阵列被安装在一个印刷电路板上的一个模块的一个侧面图;
图2是根据本发明,被安装在一个安装和互联电路上的一个模块的一个侧面图;和
图3是图2的这个模块的底视图。
具体实施方式
现在参考图,并且特别地参考图1,图1显示了使用众所周知的球栅阵列装置和方法被安装在一个印刷电路板11上的一个模块10的一个侧面图。这个球栅阵列(BGA)包括多个焊锡球12,所有的焊锡球均具有基本上相同的、大的直径。焊锡球12是由焊锡形成的,并且被用于将模块10上的触点与印刷电路板11上的触点互联。在某些情形下,附加的焊锡球12可以仅被用作物理安装结构来完成这个阵列。
一般,模块10的材料与形成印刷电路板11的材料是不同的,并且这两个材料具有不同的热扩散系数。在球栅阵列的正常的、众所周知的使用中,焊锡球12的直径足够地大,以能够吸收被两个不同热扩散系数所产生的任何应力。形成焊锡球12的焊锡是足够地软,以能够吸收这个应力,而不会产生裂缝或者将应力传送到电触点上。但是,如果所形成的焊锡球12太小了,某些应力将被传送到电触点,从而导致在焊锡连接和/或者电触点中有裂缝或者断裂,这反过来又导致不希望出现的电触点。
这个问题在于,在今天的很多应用中,最终结构的高度或者侧面是关键的并且必须被保持在一个很低的水平上,这一般比可以可靠地实现球栅阵列类型的安装和互联所需要的值还低。
现在,参考图2和3,根据本发明的一个低侧面的互联结构20被显示了。互联结构20包括一个电子电路模块21,这个电子电路模块21可以是任何众所周知的模块,例如一个被封装的半导体芯片,一个陶瓷的混合封装,等等。电子电路模块21具有被专门设计成用于将电子电路模块21安装在一个支撑和互联表面23上的一个低安装表面22。安装表面22包括被放置在与封装技术和所涉及的电子电路类型相称的任何方便位置的多个输入/输出端子。一般,电气连接区域24包括外部可以接近、并且可以在内部连接到所有均与标准多层互联技术一致的嵌入式电子电路的金属焊盘。
另外,包括在安装表面22中的是被特殊提供的、并且被巧妙地放置来物理地将电子电路模块21安装在支撑和互联表面23上的安装区域25。除了物理安装结构外,安装区域25可以包括电气连接,如果需要的话或者方便的话。在某些应用中,安装区域25仅被包括以用于物理安装。一般,安装区域25将被沿安装表面22分隔开,以被放置在巧妙选择以为电子电路模块21提供最大支撑的点上。例如,在电子电路模块21一般是矩形时,如图3所显示的,一个安装区域25被形成为与在4个角中每一个的边缘相邻。
支撑和互联表面23包括多个匹配支撑区域30和多个匹配电气互联区域31。如可以从图2中看出的,当将电子电路模块21放置在叠加在支撑和互联表面23上的一个安装位置中,电子电路模块21的电气连接区域24被与匹配电气互联区域31对准,并且电子电路模块21的安装区域25被与多个匹配支撑区域30对准。在这个位置中,电子电路模块21的安装表面22一般与支撑和互联表面23并行,并且相互之间被隔开。
这里,应注意,电子电路模块21的安装区域25被与匹配支撑区域30隔开一第一距离,并且电子电路模块21的电气连接区域24被与匹配电气互联区域31隔开一第二距离,第二距离比第一距离小。这个在隔开距离上的差异可以被使用一些不同的安排结构来实现。例如,在这个优选的实施方式中,通过被形成在电子电路模块21的安装表面22中的凹陷35来定义安装区域25。当然,应理解,这些凹陷可以被形成在支撑和互联表面23中,以定义匹配支撑区域30,或者在某些特定的应用中,可以同时在安装表面22和支撑和互联表面23中形成更小的凹陷。
为了将电子电路模块21安装在支撑与互联表面23上,提供了多个安装结构36,例如球,方型,等等和多个电气连接件37,安装结构36具有基本上与第一距离相等的一第一厚度或者直径,电气连接件37具有比第一厚度小的一第二厚度。在这个优选实施方式中,安装结构36和电气连接件37是由不同的焊锡材料形成的,以使安装结构36可以基本上保持它们的形状来提供焊接特征,而电气连接件37进行流动来提供电气连接特性。在一个特定的示例中,安装结构36是一个熔化温度大约为310℃的焊锡球,而电气连接件37是一个熔化温度大约是220℃的焊锡剂的一部分。然后,一个简单的重新流动过程(reflow process)可以被用于电气连接件37,而安装结构36提供机械安装,应理解,如果希望的话,可以使用具体适合于各种功能的相同材料。
安装结构36被物理地、一个一个地连接到每一个安装区域25,并且被连接到匹配支撑区域30,以物理地将电子电路模块21安装在支撑与互联表面23上。同时,电气连接件37被放置成将每一个电气连接区域24连接到匹配电气互联区域31。放置和固定在安装结构36和电气连接件37中的过程被根据标准的和众所周知的技术执行,这不需要在这里进行详细描述。
通过使用被巧妙地放置在电子电路模块21上的虚设或者活动安装结构36,安装结构36将吸收因为电子电路模块21和支撑与互联表面23之间的热扩散系数等差异,而引起的大部分应力,并且将保护使用更细的电气连接部件37而形成的或者焊接而成的电气连接。进一步,通过使用这个方法,最后封装的高度hL基本上比一个BGA安装模块的高度hL小(见图1)。如图1所显示的,为了将BGA安装模块降低到高hL,模块的很多部分将丢失。在这个优选的实施方式中,虽然一小部分电子电路模块21会因为凹陷35而丢失,但是主要部分将被保留以给电路所使用。如果凹陷被形成在支撑与互联表面中,就不会额外丢失任何体积,但是可能会缺少某些标准性。
这样,公开了一个低侧面的互联结构,并且具有可靠的安装。这个结构可以被轻易地调节成适合许多应用中的高度限制,而仍然能够提供可靠的接触,并且不会牺牲很多电气连接体积,或者根据不牺牲电气连接体积。
虽然我们已经显示并且描述了本发明的特定实施方式,但是,该领域内的技术人员可以进行进一步的修改和改善。所以我们希望应理解,本发明不局限于所显示的特定形式,并且我们认为后附权利要求书覆盖了所有不偏离本发明的精神和范围的修改。

Claims (5)

1.一种低侧面互联结构(20),其特征在于包括:
一个电子电路模块(21),其具有一个安装表面(22),这个安装表面(22)上具有多个相互隔开的安装区域(25)和多个在该安装表面(22)上形成的电气接触区域(24);
一个支撑和互联表面(23),其与所述安装表面(22)平行且隔开设置,该支撑和互联表面(23)包括多个隔开的匹配支撑区域(30),每个所述匹配支撑区域位于在所述支撑和互联表面(23)中形成的一个凹陷内;
所述多个安装区域(25)与所述支撑和互联表面(23)的匹配支撑区域(30)隔开第一距离;和
所述多个电气接触区域(24)与所述支撑和互联表面(23)隔开第二距离,该第二距离比第一距离小;
多个电气连接件(37),其中的每一个位于所述电气接触区域(24)中之一与所述支撑和互联表面(23)之间。
2.如权利要求1的低侧面互联结构,其中,所述多个电气接触区域比所述多个隔开的安装区域大得多。
3.如权利要求1的低侧面互联结构,其中,所述多个隔开的安装区域位于所述电子电路模块的边缘附近。
4.如权利要求3的低侧面互联结构,其中,所述电子电路模块的形状是具有4个角的矩形,所述多个隔开的安装区域被在所述电子电路模块的4个角中每一个角中放置一个。
5.如权利要求1的低侧面互联结构,其中,所述多个隔开的安装区域中的每一个安装区域(25)位于在所述安装表面(22)中形成的一个凹陷(35)内。
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Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3093800U (ja) * 2002-11-01 2003-05-16 アルプス電気株式会社 電子ユニット
US20040245624A1 (en) * 2003-06-03 2004-12-09 Swanson Leland S. Using solder balls of multiple sizes to couple one or more semiconductor structures to an electrical device
US7084500B2 (en) * 2003-10-29 2006-08-01 Texas Instruments Incorporated Semiconductor circuit with multiple contact sizes
US7005742B2 (en) * 2004-02-05 2006-02-28 Texas Instruments Incorporated Socket grid array
US7364945B2 (en) 2005-03-31 2008-04-29 Stats Chippac Ltd. Method of mounting an integrated circuit package in an encapsulant cavity
US7354800B2 (en) * 2005-04-29 2008-04-08 Stats Chippac Ltd. Method of fabricating a stacked integrated circuit package system
US7768125B2 (en) * 2006-01-04 2010-08-03 Stats Chippac Ltd. Multi-chip package system
US7456088B2 (en) 2006-01-04 2008-11-25 Stats Chippac Ltd. Integrated circuit package system including stacked die
US7750482B2 (en) 2006-02-09 2010-07-06 Stats Chippac Ltd. Integrated circuit package system including zero fillet resin
US8704349B2 (en) 2006-02-14 2014-04-22 Stats Chippac Ltd. Integrated circuit package system with exposed interconnects
US7385299B2 (en) * 2006-02-25 2008-06-10 Stats Chippac Ltd. Stackable integrated circuit package system with multiple interconnect interface
JP5350604B2 (ja) * 2007-05-16 2013-11-27 スパンション エルエルシー 半導体装置及びその製造方法
US8487428B2 (en) * 2007-11-20 2013-07-16 Fujitsu Limited Method and system for providing a reliable semiconductor assembly
US9773724B2 (en) 2013-01-29 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices, methods of manufacture thereof, and semiconductor device packages
US8952532B2 (en) 2013-05-13 2015-02-10 Intel Corporation Integrated circuit package with spatially varied solder resist opening dimension
JP6508217B2 (ja) * 2015-01-16 2019-05-08 株式会社村田製作所 基板、基板の製造方法及び弾性波装置
KR20200095253A (ko) 2019-01-31 2020-08-10 에스케이하이닉스 주식회사 앵커(anchor) 구조물을 포함하는 반도체 패키지
CN112437979A (zh) * 2019-07-24 2021-03-02 深圳市大疆创新科技有限公司 电子封装组件、相机、可移动平台及其制备方法
CN110602363A (zh) * 2019-09-23 2019-12-20 Oppo广东移动通信有限公司 一种摄像头模组以及电子设备
CN114664747B (zh) * 2020-12-31 2023-02-03 华为技术有限公司 板级结构及通信设备
US20230068329A1 (en) * 2021-08-30 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4545610A (en) * 1983-11-25 1985-10-08 International Business Machines Corporation Method for forming elongated solder connections between a semiconductor device and a supporting substrate
US4581680A (en) * 1984-12-31 1986-04-08 Gte Communication Systems Corporation Chip carrier mounting arrangement
US5191404A (en) * 1989-12-20 1993-03-02 Digital Equipment Corporation High density memory array packaging
DE4020048A1 (de) * 1990-06-23 1992-01-02 Ant Nachrichtentech Anordnung aus substrat und bauelement und verfahren zur herstellung
JP2555811B2 (ja) * 1991-09-10 1996-11-20 富士通株式会社 半導体チップのフリップチップ接合方法
US5370541A (en) * 1993-01-25 1994-12-06 Minnesota Mining And Manufacturing Company Repositionable termination module
JPH09283564A (ja) * 1996-04-16 1997-10-31 Hitachi Ltd 半導体接合構造
JP2817715B2 (ja) * 1996-07-05 1998-10-30 日本電気株式会社 ボールグリッドアレイ型回路基板
JP2986413B2 (ja) * 1996-08-01 1999-12-06 富士機工電子株式会社 エアリア・グリッド・アレイ・パッケージ
US6075711A (en) * 1996-10-21 2000-06-13 Alpine Microsystems, Inc. System and method for routing connections of integrated circuits
JP3178401B2 (ja) * 1998-01-08 2001-06-18 住友金属工業株式会社 パッケージのbga型電極の形成および接続方法
US6973225B2 (en) * 2001-09-24 2005-12-06 National Semiconductor Corporation Techniques for attaching rotated photonic devices to an optical sub-assembly in an optoelectronic package

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