CN1192048A - 芯片上引线及标准常规引线的组合结构的半导体芯片封装 - Google Patents

芯片上引线及标准常规引线的组合结构的半导体芯片封装 Download PDF

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CN1192048A
CN1192048A CN97121615A CN97121615A CN1192048A CN 1192048 A CN1192048 A CN 1192048A CN 97121615 A CN97121615 A CN 97121615A CN 97121615 A CN97121615 A CN 97121615A CN 1192048 A CN1192048 A CN 1192048A
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lead
semiconductor chip
die package
electrode pad
semiconductor die
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CN97121615A
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CN1114948C (zh
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郑道秀
权五植
宋泳僖
任旻彬
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

一种半导体芯片封装,包括位于集成电路(IC)的有源表面上的中央电极焊盘和周边电极焊盘。该封装还包括引线框,引线框具有:第一内引线,其直接贴装至有源表面并且连接至中央电极焊盘;第二内引线,它远离该芯片并连接至周边电极焊盘;第一外引线,连接至第一内引线;以及第二外引线,连接至第二内引线。沿着芯片的长边或是沿着IC的短边,通过布置第二外引线可形成双列类型的或者是四边形的封装。

Description

芯片上引线及标准常规引线的组合 结构的半导体芯片封装
本发明一般地涉及半导体芯片封装，尤其是涉及在高密度的半导体芯片中布置接触引线的方法。
一般地，半导体芯片在其有源表面具有多个电极焊盘以便于集成电路元件和外部之间连接电信号。依赖于电极焊盘的排列，半导体芯片可以被分为中央焊盘型器件及周边焊盘型器件，其中在中央焊盘型器件中电极焊盘分布在芯片有源表面的中央区域，在周边焊盘型器件中电极焊盘则沿着芯片有源表面的边缘而布置。中央焊盘器件显示出小的信号偏差，因为缩短的总线线路而有很高的信号传输速度，以及在电极焊盘的设计方面较为简单且相对容易。进而，按照中央焊盘设计生产的半导体存储器芯片的尺寸比周边存储器芯片的尺寸小大约4％至7％，其结果使得单个晶片上放置的净焊盘的数目增加并因此提高了生产量。由于这些以及其它的优点，目前存储器器件的制造商们广泛采用中央焊盘型芯片。
为了封装中央焊盘型器件，无论是芯片上引线(LOC)的设计方案，或是长引线键合方案都可以采用，其中芯片上引线是引线直接贴装至芯片的有源表面，长引线键合是引线离芯片边缘很远并且是通过长键合线与电极焊盘相连接。但是，由于有这样长的键合线，后者有一些问题比如较差的可靠性。另一方面，尽管LOC引线比标准常规引线需要更多的制造成本，但键合线能够制作的更短些并因此能提高封装的可靠性，进而，LOC封装能提高芯片的尺寸对总的封装的比率。
尽管如此，由于存储器芯片的密度不断地增大，封装工程师面临着一些技术问题，那就是，因为引线框的制造技术跟不上芯片的缩小率，将所有的LOC引线布置在下一代存储器芯片的缩小的有源表面上是不可能的。一般地，引线框引线或者用冲压或者用光腐蚀的方式来构图。在这两种方法中，仅仅当引线的宽度或者相邻引线之间的距离等于或大于该引线框的厚度的80％的时候，才能制作成理想的引线图形。为了克服这种局限性，可以考虑减小引线框的厚度，但是，这种设计方案并不理想，因为在装配过程中，薄的引线框极易损坏并且这种构图的引线很容易被损坏，甚至是由于一次小小的冲击。
因此，有必要在并不丢失中央焊盘结构和LOC引线结构的优点的条件下来封装高密度半导体芯片。
本发明的目的是提供一种半导体芯片封装，它能通过使用中央焊盘结构及LOC引线结构来装配高密度半导体芯片。
本发明的另一目的是提供一种半导体芯片封装，它能够克服引线框的生产的局限并能有效地封装高密度半导体芯片。
在依据本发明的半导体芯片封装中，半导体芯片具有中央焊盘的组合型结合，引线框提供有多个第一内引线，它们直接贴装至芯片的有源表面并且电连接至中央电极焊盘；以及多个第二内引线，它们远离芯片的边缘而分布并且电连接至周边电极焊盘。
一般地，半导体芯片呈矩形，具有一长边和一短边，当引线框的外引线与内引线制作成一体，并且既沿着长边又沿着短边而分布时，就可得到一个四边形的封装器件，而且如果外引线沿着芯片的长边而分布时，即得到双列类型的封装器件。
应用于本发明的封装的引线框包括连杆，它连接于角部引线和引线框的侧轨之间，以便在装配过程中单个封装能够保持成条形直至它们成为单一体，并且最长的角部引线能够被支持和保护以免损坏。引线框可能还包括对准键以便当芯片贴装至引线框的引线且当引线与电极焊盘电连接的时候，来提高引线框与半导体芯片的可识别性和精确的布置。
LOC结构的第一内引线具有倾斜区域(up-set，regions)，该倾斜区域的大小由芯片的厚度及用来将芯片贴装至第一引线的粘合剂的厚度来确定，通过控制该倾斜区域的大小，即有可能获得该封装器件的最佳的垂直结构。
上面已经叙述了本发明的一些目的和优点，通过下文的详细说明，并且参照附图，将能更加充分地理解其它的目的和优点，其中：
图1是本发明的优选的引线框条的局部平面图；
图2是根据本发明的一个实施例的半导体芯片封装的平面图；
图3是根据本发明的半导体芯片封装的局部平面图；
图4A是沿图2中线IV-A所取的截面图；
图4B是沿图2中线IV-B所取的截面图；
图5是根据本发明的另一实施例的半导体芯片封装的截面图；
图6是本发明的示例性半导体芯片封装的透视图；
图7是根据本发明的再一个实施例的半导体芯片封装的局部平面图；及
图8是根据本发明的再一个实施例的半导体芯片封装的透视图。
现在，参照附图，详细地阐述本发明的实施例。
图1是本发明的优选引线框条的局部平面图，引线框条100具有若干个相同的引线框图形，因而能使管芯键合，导线键合，以及模塑工艺应用至多个芯片。在装配过程中，通过使用输送孔16，引线框条100被输送，这些重复的单个引线框图形由槽22隔开，为简单起见，图1中仅仅示出了一个单个引线框图形。
每个单个图形都有多个内引线10和12，它们电连接至半导体芯片(未示出)的电极焊盘，以及多个外引线14a和14b，用于电连接芯片，内引线与外引线通过阻拦条28相耦连，当塑料模制树脂满了模塑区域34以形成一封装保护体时，阻拦条28将会防止模塑树脂的溢出。在模塑过程之后，阻拦条28和连杆18被切掉，这样内引线和外引线即成独立状态。
借助于侧轨24，各单个引线框图形被制作成为条带形，通过连杆18位于模塑区域34的四个角部的角部引线15连接至侧轨24上，当阻拦条28被切掉可是单个引线框并未最后成为单一体时，连接角部引线15和侧轨24的连杆18用于支撑单个引线框，而且，连杆18能够防止角部引线15的任何可能的变形，角部引线15具有最长的长度因而在装配过程中容易损坏变形。
引线20这样称呼并不是连接引线，它们并不连接到芯片上，电源引线26是施加至芯片上的正电源电压VDD和负电源电压VSS的通道，电源引线26被分成两个部分以便能减少引线的电感。
对于引线框引线，第一内引线10是LOC引线，而第二内引线是标准常规引线。通过一粘合材料32第一内引线10直接贴装至芯片的有源表面，并且它有一弯曲区域(倾斜区域)30，这种组合引线结构适合于封装具有中央分布的电极焊盘及周边分布的电极焊盘的半导体芯片。
图2是根据本发明的一个实施例的半导体芯片封装的平面图，在图2中，半导体芯片封装200具有总共一百个输入/输出管脚，其中的每一个发送和接收不同的信号。
半导体芯片40具有一长边42和一短边44，在半导体储器芯片中这种矩形结构是很普遍的。在半导体芯片40的有源表面46上面，许多内部电路元件比如存储器单元，控制栅极，金属线，和多个电极焊盘48和49被形成，电极焊盘包括中央电极焊盘48和周边电极焊盘49，其中电极焊盘48位于芯片有源表面46的中央区域上面按两行并且平行于长边42而排列着，电极焊盘49则在芯片有源表面46的边缘附近沿着短边44而分布。
第一LOC内引线10沿着芯片的长边42排列着并且通过粘合剂32直接贴装至芯片的有源表面46，由键合线52该第一内引线10电连接至中央电极焊盘48，且电连接至第一外引线14a，外引线14a同样也是沿着长边42分布。
粘合剂32是电绝缘的，并且可以是由聚酰亚胺制成的双面粘合剂，或者是使用胶带或者是淀积部分固化的粘合剂，半导体芯片能粘结到第一内引线上。前一种情况，胶带粘合到第一内引线上，然后该第一内引线与芯片的有源表面相对准并布置在其上。在高温下通过对第一内引线与芯片加压，二者便键合在一起。同时，在芯片的有源表面上通过淀积部分固化的液体粘合材料，然后在高温下通过对第一内引线和芯片加压，即可进行管芯键合操作。
第二内引线12沿着半导体芯片的短边44排列并且具有标准常规结构，也就是，它们远离芯片的边缘。通过键合线52第二内引线12电连接至周边电极焊盘49，并且与第二外引线14b相连接，引线14b沿着芯片的短边44而分布。
对于这种LOC引线和标准引线的组合结构，有可能克服引线框的加工过程的局限性，因而能有效地封装高密度存储器件，另外，由于半导体芯片除了周边电极焊盘之外还具有中央电极焊盘，因而同样能获得中央类型的优点，比如小信号偏差，很高的信号传输速率以及在电极焊盘的设计方面较为简单且相对容易。
如图2所示，周边电极焊盘49与粘合剂32必须相隔一距离D，距离D是考虑了若干个参数后确定的，这些参数比如是引线框的加工公差，封装过程中的加工公差，以及该第一内引线与用于线键合的毛细管之间的接触情况，较为可取的是，将距离D保持在等于或者大于20密耳的状态。
脚号为36-45和86-96的虚设引线20并不是连接引线，它们是由于比如是按照JEDEC所定义的外引线的数目规格与为了某一存储器件的功能的外引线的真实数目之间差异而产生的。
第一内引线10可能包括对准键50，在管芯键合过程以及线键合过程中它用来帮助识别引线框引线和存储器芯片40的位置。或者是经过蚀刻或者是通过冲压的方法，对准键50能够与引线框图形同时制作成，而且很自然地由和引线框条相同的材料构成。
电源引线26为存储器芯片40提供电源电压比如VDD和VSS，并且使其端部分成两个部分，这两个平行的电源通道使得引线框引线之间的电感减少，因而能够提供相对较稳定的电源。
对于这种稳定的电源，可以采用如图3所示的总线结构。参照图3，总线汇流条56连接着一些内引线并形成一个单通道，恒定的电源电压通过这些内引线被施加上。因此，电源电压的恒定电平能够被施加到不同的电路元件上，并且电源的噪声效果能被减少，图3中，具有管脚号5，11和19的内引线由总线汇流条56a连接以便用于接收负的VSS电源电压信号，而管脚号为59，67，73和79的内引线由总线汇流条56b来连接，其中正的VDD电源电压信号施加至总线汇流条56b上。
如图2所示，当第一内引线10贴装至芯片的有源表面46上时，第一内引线必须分布成不置于保险盒54之上。保险盒54一般提供用来以多余的单元来替换有故障的存储器件的存储单元，并且具有外露金属线，例如是铝线，它能被激光切断。如果保险盒54被第一内引线所覆盖，则修复故障的存储器单元将变得不可能。
如图4A所示，第一内引线10具有倾斜区域30，图4A是沿图2中线IVA所取的截面图。倾斜区域30将半导体芯片40放置在保护性的封装体60的中央部位。例如，如果半导体芯片具有197密耳×340密耳的尺寸和0.3密耳的厚度，并且粘合剂的厚度t是0.1密耳，则该倾斜区域30的尺寸可以是大约0.2密耳以便使从半导体芯片到封装体的顶面的距离d1是1.05密耳，基本上等于从半导体芯片至封装体的底面的距离d2。保护性的封体是经过模塑过程而形成的，其中液态模制树脂以高压力注入至凹腔中，引线框条放置在该凹腔中，此时，如果距离d1和d2不一样，则该模制树脂的注射力在该封装体的上部和下部是不均衡的，并且因而可能发生半导体芯片的倾斜，这种芯片倾斜在随后的装配过程中会引起封装体的曲翘，但是，在本发明中，由于封装体的上部以及下部的平衡能够通过控制倾斜区域30的大小来调节，倾斜区域30形成于第一内引线10中，这样即能获得最佳的封装体的垂直结构，尽管倾斜区域30的大小被描述为大约0.2密耳，本领域的那些普通的技术人员会懂得，根据半导体芯片的厚度以及粘合剂的厚度该尺寸是可以变化的。
图4B是沿图2中线IVB所取的截面图，如前面所说明的，周边电极焊盘49沿着半导体芯片40的短边排列，并且通过键合线52电连接至第二内引线12。该第二内引线12是标准常规引线，它们离开半导体芯片40而排列。
如图2和4B所示，半导体芯片封装200具有内引线10和12，通过键合线52它们电连接至电极焊盘48和49，但是，该直接贴装至芯片有源表面46上的第一内引线10通过使用金属凸点而不是键合线亦能电连接至中央电极焊盘48。
图5是根据本发明的一实施例的半导体芯片封装的截面图，参照图5，半导体芯片封装210的第一内引线10贴装至半导体芯片40的有源表面，并且通过金属凸点70电连接至中央电极焊盘48，该金属凸点70形成于电极焊盘48的上面，金属凸点70可以是金凸点，铜凸点或者是锡-铅凸点，金属凸点70与第一内引线10通过热-压方法键合，此时，必须注意该引线与电极焊盘的精确对准度。尽管图5中未示出，为了提高第一内引线10与半导体芯片40之间的键合力，会使用粘合剂。
图6是根据本发明的另一实施例的半导体芯片封装的透视图。半导体芯片封装300是一个四边形封装，其中外引线14沿着封装体60的四个边伸出，外引线14形状为一鸥翼状或是一J型引线以便封装300能够表面安装至电路板(未示出)上面。四边形封装适合于具有许多输入/输出管脚的芯片，并且比起管脚-插入类型的封装它代表着一种提高的封装密度。
通过沿着半导体芯片40的长边42排列该第一外引线14a以及沿着芯片40的短边44设置该第二外引线14b，即能获得这种四边形的封装器件，如图1和2所示。
图7是根据本发明的再一实施例的半导体芯片封装的平面图，类似于图2中所示的实施例，图7中所示的半导体芯片封装40包括LOC结构的第一内引线110，它们直接贴装至芯片的有源表面146上并且电连接至中央电极焊盘149，该封装还包括标准第二内引线112，它们离开半导体芯片140的短边144分布，并且电连接至周边电极焊盘149。
封装400的第一内引线110具有倾斜区域用于建立封装的最佳垂直结构，并且通过粘合剂132键合到芯片的有源表面146上。粘合剂132距离周边电极焊盘149必须是至少200密耳。电源引线126被分成两部分，尽管电源引线126分布在如图7中的第二内引线中，但是将电源引线形成于第一内引线中是可以的。
连杆180亦被保护性封装体所密封，并且连接至引线框条的侧轨上以便在形成单一体之前用来将各单个引线框图形保持为条形，通过键合线152该第一和第二内引线110和112电连接至电极焊盘，如图7中所示。尽管如此，通过使用金属凸点，还可将第一内引线110电连接至中央电极焊盘148上，其类似于以上参照图5中所说明的实施例。
无论是与第一内引线110相连的第一外引线114a，还是与第二内引线112相连的第二外引线114b，它们都沿着保护性封装体的长边分布着，利用这种结构的外引线，能够获得如图8中所示的双列封装400，其中外引线从该封装的两个长边伸出，外引线114具有鸥翼形状的末端，如图8中所示，或者是具有J-引线末端，用于封装400的表面-安装。
尽管已经参考说明性质的实施例描述了本发明，但该说明并未打算将此作为限定性的。通过参考本说明该领域的技术人员会明白各种修改所说明的各实例的组合以及本发明的其他实施例。因此正如所期的，所附权利要求包含任何这样的修改或者是实施例。

Claims (21)

1.一种半导体芯片封装，包括：
一半导体芯片，它具有长边和短边以及集成电路元件形成于其上的有源表面，所述半导体芯片具有多个中央电极焊盘和多个周边电极焊盘，其中中央电极焊盘位于所述有源表面的中央区域上沿着所述长边分布，周边电极焊盘则位于所述有源表面的周边区域上沿着所述短边分布；
引线框，它具有多个内引线和多个外引线，以便使所述半导体芯片电连接至外部器件，所述内引线包括第一内引线和第二内引线，其中第一内引线直接贴装至所述半导休芯片的所述有源表面上并且沿着所述长边排列，第二内引线沿着并且远离所述短边排列，所述外引线包括第一外引线和第二外引线，其中第一外引线与所述第一内引线相连接并且沿着所述短边排列，第二外引线与所述第二内引线相连接并且沿着所述长边排列；
电连接器件，用于将所述第一内引线连接至所述中央电极焊盘和将所述第二内引线连接至所述周边电极焊盘；以及
保护性封装体，用于密封所述半导体芯片，所述第一和所述第二内引线，以及所述电连接器件。
2.如权利要求1所述的半导体芯片封装，其特征在于，所述引线框还包括角部引线，位于所述半导体芯片的所述有源表面的角部，而且所述角部引线由连杆支撑，该连杆连接至引线框条的侧轨上，该引线框条包括所述引线框。
3.如权利要求1所述的半导体芯片封装，其特征在于，所述多个第一内引线包括对准键，当所述半导体芯片贴装至所述第一内引线并且当所述第一和所述第二内引线通过所述电连接器件与所述电极焊盘相连接的时候，该对准键用于将所述引线框与所述半导体芯片对准。
4.如权利要求1所述的半导体芯片封装，其特征在于，所述电连接器件是键合线。
5.如权利要求1所述的半导体芯片封装，其特征在于，所述电连接器件包括金属凸点，用于连接所述多个内引线与所述中央电极焊盘，以及键合线，用于连接所述多个第二内引线与所述周边电极焊盘。
6.如权利要求1所述的半导体芯片封装，其特征在于，所述中央电极焊盘是按照两条平行线分布的，该两条平行线基本上平行于所述半导体芯片的所述长边。
7.如权利要求1所述的半导体芯片封装，其特征在于，所述的多个第一内引线具有倾斜区域。
8.如权利要求1所述的半导体芯片封装，其特征在于，所述内引线包括电源内引线，该电源内引线被分成两部分。
9.如权利要求1所述的半导体芯片封装，其特征在于，所述第一内引线通过电绝缘胶带贴装至所述有源表面。
10.如权利要求9所述的半导体芯片封装，其特征在于，所述胶带是由聚酰亚胺制作成的双面胶带。
11.如权利要求9所述的半导体芯片封装，其特征在于，所述第一内引线具有倾斜区域，并且所述倾斜区域的尺寸由所述胶带的厚度以及所述半导体芯片的厚度来确定，以便使得所述半导体芯片位于所述保护性封装体的中央。
12.如权利要求9所述的半导体芯片封装，其特征在于，所述周边电极焊盘距离所述胶带的距离大于20密耳。
13.如权利要求1所述的半导体芯片封装，其特征在于，所述第一内引线包括用于连接电源引线的总线汇流条，通过该电源引线恒定电源电压信号被提供至所述半导体芯片中。
14.如权利要求1所述的半导体芯片封装，其特征在于，所述半导体芯片具有多个保险盒，它们形成于所述有源表面之上，所述具有可由激光束切断的外露的金属线的保险盒是用来以好的单元来替换所述半导体芯片的故障单元，而且其中所述第一内引线直接贴装至所述有源表面上却并不覆盖所述保险盒。
15.一种半导体芯片封装，包括：
半导体芯片，具有长边和短边以及内部电路单元形成于其上的有源表面，所述半导体芯片具有多个中央电极焊盘和多个周边电极焊盘，其中中央电极焊盘位于所述有源表面的中央区域上沿着所述长边分布，周边电极焊盘位于所述有源表面的周边区域上沿着所述短边分布；
引线框，具有多个内引线和多个外引线，所述外引线与所述内引线形成为一个整体，并且用于使所述半导体芯片电连接至外部器件，所述内引线包括第一内引线和第二内引线，其中第一内引线直接贴装至所述半导体芯片的所述有源表面上，并且沿着所述长边排列，第二内引线沿着并且远离所述短边排列，所述外引线包括第一外引线和第二外引线，其中第一外引线与所述第一内引线相连接并且沿着所述长边排列，第二外引线与所述第二内引线相连接并且沿着所述长边排列；
电连接器件，用于将所述第一内引线连接至所述中央电极焊盘和将所述第二内引线连接至所述周边电极焊盘；以及
保护性封装体，用于密封所述半导体芯片，所述第一和所述第二内引线，以及所述电连接器件。
16.如权利要求15所述的半导体芯片，其特征在于，所述引线框包括连杆，该连杆连接至引线框条的侧轨上，并且由所述封装体进行密封，该引线框条包括所述引线框。
17.如权利要求15所述的半导体芯片封装，其特征在于，所述第一内引线具有倾斜区域。
18.如权利要求15所述的半导体芯片封装，其特征在于，通过一电绝缘粘合剂所述第一内引线贴装至所述半导体芯片的所述有源表面上。
19.如权利要求18所述的半导体芯片封装，其特征在于，所述第一内引线具有倾斜区域并且所述倾斜区域的尺寸由所述半导体芯片的厚度以及所述粘合剂的厚度来确定。
20.如权利要求15所述的半导体芯片封装，其特征在于，所述第一内引线包括用于连接电源引线的总线汇流条，通过该电源引线恒定电源电压信号被提供至所述半导体芯片中。
21.如权利要求15所述的半导体芯片封装，其特征在于，所述半导体芯片具有多个保险盒，它们形成于所述有源表面之上，所述具有可由激光切断外露的金属线的保险盒用于以好的单元替换所述半导体芯片的故障单元，而且其中，所述第一内引线直接贴装至所述有源表面上却并不覆盖所述保险盒。
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CN100459115C (zh) * 2003-10-04 2009-02-04 三星电子株式会社 带式电路衬底及使用该衬底的半导体芯片封装

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FR2760289A1 (fr) 1998-09-04
DE19749539B4 (de) 2006-04-13
JP2981194B2 (ja) 1999-11-22
KR19980069880A (ko) 1998-10-26
FR2760289B1 (fr) 2002-08-30
DE19749539A1 (de) 1998-09-10
JPH10242373A (ja) 1998-09-11
TW354856B (en) 1999-03-21
KR100227120B1 (ko) 1999-10-15

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