CN1191390A - 塑封半导体器件及其制造方法 - Google Patents

塑封半导体器件及其制造方法 Download PDF

Info

Publication number
CN1191390A
CN1191390A CN97123188A CN97123188A CN1191390A CN 1191390 A CN1191390 A CN 1191390A CN 97123188 A CN97123188 A CN 97123188A CN 97123188 A CN97123188 A CN 97123188A CN 1191390 A CN1191390 A CN 1191390A
Authority
CN
China
Prior art keywords
semiconductor device
device chip
wire
lead
mold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN97123188A
Other languages
English (en)
Other versions
CN1121720C (zh
Inventor
大内伸仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Publication of CN1191390A publication Critical patent/CN1191390A/zh
Application granted granted Critical
Publication of CN1121720C publication Critical patent/CN1121720C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一种塑封半导体器件,该器件具有半导体器件芯片,还具有沿半导体器件芯片上表面设置的多根引线,和覆盖半导体器件芯片的塑模,其中塑模限制在半导体器件芯片的上表面上,引线的形状为J形或U形,从而可以加强引线和印刷电路板间的连接,提高半导体器件的电气和机械性能的可靠性。

Description

塑封半导体器件及其制造方法
本发明涉及一种适用于塑封半导体器件及制造塑封半导体器件的方法的改进。特别是，本发明涉及一种适用塑封半导体器件的改进及其制造方法，研究该改进的目的是通过降低连接引线和印刷板印迹的焊料层龟裂从而导致引线和印刷电路板之间不完全的机械和电气连接的可能性，来提高半导体器件的可靠性。
随着IC技术领域的快速发展，越来越需要将存储卡等做得更薄和尺寸更小。所以对适用于IC和/或存储卡的半导体器件也有类似需求。
参见图1，该图展示出现有技术的塑封半导体器件的剖面，其中，通过使用例如聚酰亚胺树脂型的胶带602，多根引线603(引线603彼此平行地排列于半导体器件芯片上)附着在半导体器件芯片601的上表面601a上(该表面下制造有单片电子元件，在图1中实际为下表面)。每根引线603借助Au丝604与形成在半导体器件芯片601上表面的每个键合焊盘104a键合。将设置了引线603的半导体器件芯片601模制于塑模中，如聚酰亚胺树脂605中，但引线603的端部603a的上表面及半导体器件芯片601的下表面601b未被模制。尽管塑模605垂直方向的厚度在0.3-0.4mm范围内，但对半导体器件芯片601的侧面来说，这已到了极限。这是为了满足使完成的塑封半导体器件的厚度薄且横向面积小的目的。
把完成的塑封半导体器件上下倒转过来后，引线603的端部603a与设置于印刷电路板610a上的印迹610焊接在一起。以此方式，借助焊料块611保证引线603的端部603a与印迹610间的电连接。
由于半导体器件芯片601倒转过来安装于印刷电路板上，且由于现有技术中其下表面未被塑模例如聚酰亚胺树脂605覆盖，所以可以一定程度上减小完成的塑封半导体器件的厚度。
然而，上述现有技术的塑封半导体器件存在以下缺点，即连接引线603的端部603a和设置于印刷电路板610a上的印迹610的焊料块611存在龟裂的可能性，导致端部603a和印迹610间的机械和电气连接不能令人满意。从电气和机械性能角度看，这显然是降低塑封半导体器件的可靠性的一个因素。
据推测这种不良现象是由半导体器件芯片和印刷电路板间热膨胀系数不同及引线603和印迹610间较弱的连接造成的。换句话说，为了减小塑封半导体器件的横向面积，可以将引线603的长度设计得较短。因此，引线603很难吸收因半导体器件芯片和印刷电路板间的热膨胀系数不同产生的应力。此外，把引线603的长度设计得较短而造成的引线603的端部603a的面积较小，这会使引线603的端部603a与印迹610间的连接强度变弱。
因此，在以上的情况下，从电气和机械的角度来看非常需要改进塑封半导体器件，加强引线与印刷电路板间的连接，从而使塑封半导体器件的电气和机械性能可靠。
因此，本发明的目的是提供一种塑封半导体器件，加强引线与印刷电路板间的连接，从而使塑封半导体器件的电气和机械性能可靠。
本发明的另一目的是提供一种制造上述塑封半导体器件的方法。
为了实现上述第一个目的，根据本发明第一实施例的塑封半导体器件包括：
半导体器件芯片，
沿半导体器件芯片上表面从半导体器件芯片中间部分向半导体器件芯片边缘彼此平行排列的多根引线，
覆盖半导体器件芯片上表面和侧面的塑模，
其中每根引线在靠近半导体器件芯片边缘的部位弯折或在离半导体器件芯片边缘不太远的部位弯折，以使引线的形状成J形，并使引线的端部覆盖塑模的上表面。
为了实现上述第一个目的，根据本发明的第二实施例的塑封半导体器件包括：
半导体器件芯片，
沿半导体器件芯片上表面从半导体器件芯片中间部分向半导体器件芯片边缘彼此平行排列的多根引线，
覆盖半导体器件芯片上表面和侧面的塑模，
其中形成于半导体器件芯片上表面上的塑模限制在半导体器件芯片的中间部分，每根引线在形成于半导体器件芯片上表面中间部分的塑模的边缘弯折，使引线的形状成U形，并使引线的端部覆盖塑模的上表面。
为了实现上述第一个目的，根据本发明的第三实施例的塑封半导体器件包括：
半导体器件芯片，
沿半导体器件芯片上表面从半导体器件芯片中间部分向半导体器件芯片边缘彼此平行排列的多根引线，
覆盖半导体器件芯片上表面和侧面的塑模，
其中形成于半导体器件芯片上表面上的塑模限制在半导体器件芯片的中间部分，每根引线在靠近半导体器件芯片边缘的部位弯折或在离边缘稍远一些的部位向半导体器件芯片的中间部分弯折，不覆盖塑模的上表面。
在根据本发明第一至第三实施例的任一个塑封半导体器件中，实际上用环氧树脂作塑模。
在根据本发明第一至第三实施例的任一个塑封半导体器件中，实际上利用胶带例如聚酰亚胺树脂带把引线粘接于半导体器件芯片上。
为了实现本发明的上述目的，根据本发明的第一实施例，制造塑封半导体器件的方法包括以下步骤：
把每根直引线粘结于半导体器件芯片的上表面上，
用键合金属丝键合每根直引线，
用塑模覆盖半导体器件芯片，及
把直引线弯成J形或U形。
在根据本发明第一实施例的制造塑封半导体器件的方法中，塑模可以由环氧树脂制成。
在根据本发明第一实施例的制造塑封半导体器件的方法中，可以利用胶带如聚酰亚胺树脂带把引线粘结于半导体器件芯片上。
在根据本发明第一和第二实施例的制造塑封半导体器件的方法中，用塑模覆盖半导体器件芯片的步骤后可以是烘焙工艺，弯折直引线的步骤可以在靠近半导体器件芯片边缘的部位进行。
在根据本发明第一和第二实施例的制造塑封半导体器件的方法中，弯折直引线的步骤还包括从塑模上剥离直引线的步骤和在离边缘较远的部位向半导体器件芯片中间部分弯折直引线的步骤，还可以包括烘焙塑模的步骤，烘焙步骤在弯折直引线步骤完成后进行。
而且，本发明可以描述成一种半导体器件，该器件包括：具有多个电极的半导体器件芯片；具有第一和第二端的多根引线，第一端设置于半导体器件芯片的上表面上，第二端向与第一端相反的方向弯折；连接电极和引线的多个导电部件；及覆盖电极和引线的第一端的塑模。
在上述半导体器件中，引线的第二端可以设置于塑模上。
在上述半导体器件中，引线的第二端也可以设置于引线的第一端之上。
结合以下更详细的说明及各附图可以容易理解本发明及其各种特征和优点，其中：
图1是现有技术的塑封半导体器件的剖面图，所述半导体器件安装于印刷板上；
图2是根据本发明第一实施例制造过程中的塑封半导体器件的剖面图；
图3是根据本发明第一实施例制造过程中的塑封半导体器件的剖面图；
图4是根据本发明第一实施例制造过程中的塑封半导体器件的剖面图；
图5是根据本发明第一实施例的完成的塑封半导体器件的剖面图；
图6是根据本发明第一实施例的完成的塑封半导体器件的剖面图，所述半导体器件安装于印刷电路板上；
图7是根据本发明第二实施例制造过程中的塑封半导体器件的剖面图；
图8是根据本发明第二实施例制造过程中的塑封半导体器件的剖面图；
图9是根据本发明第二实施例的完成的塑封半导体器件的剖面图；
图10是根据本发明第二实施例的完成的塑封半导体器件的剖面图，所述半导体器件安装在印刷电路板上；
图11是根据本发明第三实施例制造过程中的塑封半导体器件的剖面图；
图12是根据本发明第三实施例制造过程中的塑封半导体器件的剖面图；
图13是根据本发明第三实施例的完成的塑封半导体器件的剖面图；
图14是根据本发明第三实施例的完成的塑封半导体器件的剖面图，所述半导体器件安装在印刷电路板上。
参见各附图，下面按照本发明三个独立的实施例详细说明三个塑封半导体器件及其制造方法。
在以下的实施例中，设半导体器件芯片的尺寸为长15mm、宽6mm、厚0.3mm。各实施例中塑模的厚度设为0.3-0.4mm。线性膨胀系数设为硅衬底是3×10-4/℃，由含42％Ni和58％Fe的合金成的引线是4×10-6/℃，由环氧树脂制成的塑模是10×10-6/℃。
第一实施例
有J形引线的塑封半导体器件。
参见图2，利用胶带例如聚酰亚胺带102，把由含42％Ni和58％Fe的合金制成且线性膨胀系数为4×10-6/℃的每根引线103粘结于长15mm、宽6mm、厚0.3mm的半导体器件芯片101上表面(从图面看为反面)上。引线103彼此平行排列。引线103的长度足以允许进行弯折。半导体器件芯片101的Si衬底和环氧树脂的线性膨胀系数分别为3×10-6/℃和10×10-6/℃。
参见图3，每根引线103借助Au丝104与形成于半导体器件芯片101上表面的每个键合焊盘104a键合。
参见图4，进行模制工艺，覆盖半导体器件芯片101的上表面和侧面。为了使完成的塑封半导体器件的横向尺寸和厚度小，塑模105的厚度较薄，在0.3-0.4mm范围内。其结果是，从图面上看，引线103的端部103a从塑模105向右和左突出来。
参见图5，每根引线103的端部103a弯折成覆盖塑模105的上表面。但引线103的端部103a并未固定在塑模105的上表面上。以此方式，完成根据本发明第一实施例的具有J形引线103的塑封半导体器件。
参见图6，按以下方式将完成的具有J形引线的塑封半导体器件安装于印刷电路板110a上。把完成的具有J形引线的塑封半导体器件上下倒转过来，然后把引线103的端部103a的上表面焊接在形成于印刷电路板110a上的印迹110上。
如图6所示，引线103比现有技术的引线长，且在引线103的端部103a和主体103c之间有弧形部分或弯折部分103b。此形状使引线103有较大的柔韧性。结果，因半导体器件芯片和印刷电路板间热膨胀系数不同造成的焊料111中产生和存储的潜在应力容易被引线103吸收，所以可以减小焊料111发生龟裂引起引线103和印迹110之间无法实现令人满意的机械和电气连接的可能性。应注意的是，半导体器件芯片101的硅衬底、由含42％Ni和58％Fe的合金制成的引线103、由环氧树脂制成的塑模105的线性膨胀系数分别为3×10-6/℃、4×10-6/℃、和10×10-6/℃。要强调的是，引线103的上述形状对于减小封装于塑料管壳中且具有J形引线的半导体器件的横向尺寸来说也是有效的。由含42％Ni和58％Fe的合金制成的引线103及由环氧树脂制成的塑模105的线性膨胀系数分别为4×10-6/℃和10×10-6/℃。
第二实施例
具有U形引线的塑封半导体器件中，设置的U形引线远离半导体器件的边缘。
参见图7，利用胶带例如聚酰亚胺带302，把多根引线303中的每根粘结于半导体器件芯片301的上表面(从图面上看为下表面)上。引线303的长度远小于第一实施例中引线的长度。利用Au丝304，键合每根引线303与形成在半导体器件芯片301上表面的键合焊盘304a。
参见图8，进行模制工艺，覆盖半导体器件芯片301上表面的中间区域和侧面。使用环氧树脂作塑模。应注意，使沿半导体器件芯片301侧面形成的塑模305的厚度较薄，例如为0.3-0.4mm，以使半导体器件的横向尺寸较小。在此模制工艺中，半导体器件芯片301上表面与引线303之间的间隙填满了塑料或此实施例中的环氧树脂。
参见图9，未被胶带例如聚酰亚胺带302粘结到半导体器件芯片301上的那部分引线303从沿半导体器件芯片301上表面形成的薄塑模305上剥离下来，并向塑模305的上表面折叠，结果形成U形引线303。引线303的端部并未固定于塑模305的上表面上。以此方式，完成具有U形引线303的塑封半导体器件。
参见图10，按以下方式，把完成的具有U形引线的塑封半导体器件安装于印刷电路板310a上。把完成的具有U形引线的塑封半导体器件上下倒转过来，然后把引线303的折叠端部303a的上表面焊接于形成于印刷电路板310a上的印迹310上。
参见图10，由于引线303由折叠端部303a、弯折部分303b和主体303c构成，所以引线303有相当好的柔韧性。结果，因半导体器件芯片301和印刷电路板310a之间热膨胀系数不同造成的焊料块311中产生和存储的潜在应力容易被引线303吸收，所以可以减小焊料311发生龟裂并引起引线303和印迹310之间无法实现令人满意的机械和电气连接的可能性。应注意的是，半导体器件芯片301的硅衬底、由含42％Ni和58％Fe的合金制成的引线303、由环氧树脂制成的塑模305的线性膨胀系数分别为3×10-6/℃、4×10-6/℃、和10×10-6/℃。此外，由于引线303设置于半导体器件芯片301中间部分之外，所以显著地减小了具有U形引线的塑封半导体器件的横向尺寸。
第三实施例
塑封半导体器件中，管壳的部位并不限于半导体器件芯片上表面的中间部分，半导体器件具有其上表面不高于管壳上表面的J形引线。
参见图11，利用胶带例如聚酰亚胺带502，把多根引线503中的每根粘结在半导体器件芯片501的上表面(从图面上看为反面)上。引线503的长度较长。换句话说，引线503的长度几乎与第一实施例的引线长度相同。利用Au丝504，键合每根引线503与形成在半导体器件芯片501上表面的键合焊盘504a。
参见图12，进行模制工艺，覆盖半导体器件芯片501上表面的中间区域和侧面。在半导体器件芯片501侧面上形成的塑模505的厚度较薄，例如为0.3-0.4mm，以使完成的半导体器件的横向尺寸较小。
参见图13，端部503a在靠近塑模505侧面505a的部位开始弯折180°或向后折叠。应注意的是，引线503的端部503a未覆盖塑模505的上表面，为的是使折叠端部503a的高度小于树脂模505的上表面505b的高度。以此方式制造根据本发明的第三实施例的塑封半导体器件，管壳的位置限制在半导体器件芯片上表面中间部分，该半导体器件具有J形引线，J形引线的上表面不高于管壳的上表面。
参见图14，按以下方式，把根据本发明第三实施例的完成的塑封半导体器件安装于印刷电路板510a上。把塑封半导体器件上下倒转过来，然后把引线503的折叠端部503a的上表面焊接在形成于印刷电路板510a上的印迹510上。
参见图14，由于引线503由折叠端部503a、弯折部分503b和主体503c构成，所以引线503具有相当好的柔韧性。结果，因半导体器件芯片和印刷电路板间热膨胀系数不同造成的焊料511中产生和存储的潜在应力容易被引线303吸收，所以可以减小焊料511发生龟裂引起引线503和印迹510间无法实现令人满意的机械和电连接的可能性。应注意的是，半导体器件芯片501的硅衬底、由含42％Ni和58％Fe的合金制成的引线503、由环氧树脂制成的塑模505的线性膨胀系数分别为3×10-6/℃、4×10-6/℃、和10×10-6/℃。此外，由于折叠端503a的高度小于树脂模505的上表面505b的高度，所以塑封半导体器件的整个高度明显小于第一和第二实施例半导体器件的高度。
上述说明表明，由本发明成功地提供了塑封半导体器件，其引线与印刷电路板间的连接加强，由此使得塑封半导体器件的电气和机械性能更可靠。
尽管以上结合特定的实施例说明了本发明，但此说明并不构成对发明的限制。对于本领域的普通技术人员来说，很显然，参考本发明的说明书可以得出对所公开实施例的各种变形及其它实施例。因此，所附加的权利要求书将覆盖所有落在本发明真正范围内的所有变形或实施例。

Claims (13)

1.一种塑封半导体器件，包括：
半导体器件芯片，
沿所述半导体器件芯片上表面从所述半导体器件芯片中间部分向所述半导体器件芯片边缘排列的多根引线，
覆盖所述半导体器件芯片上表面和侧面的塑模，
其中每根所述引线在靠近所述半导体器件芯片边缘的部位弯折或在离所述半导体器件芯片边缘不太远的部位弯折，以使所述引线的形状成J形，并使所述引线的端部覆盖所述塑模的上表面。
2.一种塑封半导体器件，包括：
半导体器件芯片，
沿所述半导体器件芯片上表面从所述半导体器件芯片中间部分向所述半导体器件芯片边缘排列的多根引线，
覆盖所述半导体器件芯片上表面和侧面的塑模，
其中形成于所述半导体器件芯片上表面上的所述塑模限制在所述半导体器件芯片的中间部分，每根所述引线在形成于所述半导体器件芯片上表面中间部分的所述塑模的边缘弯折，使所述引线的形状成U形，并使所述引线的端部覆盖所述塑模的上表面。
3.一种塑封半导体器件，包括：
半导体器件芯片，
沿所述半导体器件芯片上表面从所述半导体器件芯片中间部分向所述半导体器件芯片边缘排列的多根引线，
覆盖所述半导体器件芯片上表面的塑模，
其中形成于所述半导体器件芯片上表面上的所述塑模限制在所述半导体器件芯片的中间部分，每根所述引线在靠近所述半导体器件芯片边缘的部位弯折或在离边缘稍远一些的部位向所述半导体器件芯片中间部分弯折，不覆盖塑模的上表面。
4.根据权利要求1、2或3的塑封半导体器件，其中所述塑模是环氧树脂模。
5.根据权利要求1、2或3的塑封半导体器件，其中利用胶带将所述引线的每根粘结于所述半导体器件芯片上。
6.根据权利要求5的塑封半导体器件，其中胶带是聚酰亚胺树脂带。
7.一种制造塑封半导体器件的方法，其中所述半导体器件包括：半导体器件芯片，设置于所述半导体器件芯片上的多根引线，所述引线弯折成J形或U形，及覆盖所述半导体器件芯片上表面和侧面的塑模，该方法包括以下步骤：
把每根直引线粘结于所述半导体器件芯片的上表面上，
用键合金属丝键合每根所述直引线，
用塑模覆盖所述半导体器件芯片，及
把所述直引线弯成J形或U形。
8.根据权利要求7的制造塑封半导体器件的方法，其中利用胶带把所述直引线粘结于所述半导体器件芯片上。
9.根据权利要求7或8的制造塑封半导体器件的方法，其中用塑模覆盖所述半导体器件芯片的所述步骤之后是烘焙工艺，弯折所述直引线的所述步骤在靠近所述半导体器件芯片的边缘进行。
10.根据权利要求7或8的制造塑封半导体器件的方法，其中，弯折所述直引线的所述步骤还包括从所述塑模上剥离所述直引线的步骤，及在离边缘较远的部位向所述半导体器件芯片中间部分弯折所述直引线的步骤，还包括烘焙所述塑模的步骤，所述烘焙步骤在弯折所述直引线的步骤完成后进行。
11.一种半导体器件，包括：
具有多个电极的半导体器件芯片；
具有第一和第二端的多根引线，所述第一端设置于所述半导体器件芯片的上表面上，所述第二端向与所述第一端相反的方向弯折；
连接所述电极和所述引线的多个导电部件；及
覆盖所述电极和所述引线的所述第一端的塑模。
12.根据权利要求11的半导体器件，其中所述引线的所述第二端设置在所述塑模中。
13.根据权利要求11的半导体器件，其中所述引线的所述第二端设置在所述引线的所述第一端上方。
CN97123188A 1997-02-21 1997-11-21 塑封半导体器件及其制造方法 Expired - Fee Related CN1121720C (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP03819597A JP3737233B2 (ja) 1997-02-21 1997-02-21 樹脂封止型半導体装置およびその製造方法
JP038195/1997 1997-02-21
JP038195/97 1997-02-21

Publications (2)

Publication Number Publication Date
CN1191390A true CN1191390A (zh) 1998-08-26
CN1121720C CN1121720C (zh) 2003-09-17

Family

ID=12518587

Family Applications (1)

Application Number Title Priority Date Filing Date
CN97123188A Expired - Fee Related CN1121720C (zh) 1997-02-21 1997-11-21 塑封半导体器件及其制造方法

Country Status (5)

Country Link
US (1) US6181003B1 (zh)
JP (1) JP3737233B2 (zh)
KR (1) KR100336147B1 (zh)
CN (1) CN1121720C (zh)
TW (1) TW351840B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110696275A (zh) * 2019-10-31 2020-01-17 奇点新源国际技术开发(北京)有限公司 一种线缆节点的塑封方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3180800B2 (ja) * 1999-04-08 2001-06-25 カシオ計算機株式会社 半導体装置及びその製造方法
US6798078B2 (en) * 2000-12-14 2004-09-28 Yamaha Hatsudoki Kabushiki Kaisha Power control device with semiconductor chips mounted on a substrate
US11444227B2 (en) 2019-10-01 2022-09-13 Dominant Opto Technologies Sdn Bhd Light emitting diode package with substrate configuration having enhanced structural integrity
US11444225B2 (en) 2020-09-08 2022-09-13 Dominant Opto Technologies Sdn Bhd Light emitting diode package having a protective coating
US11329206B2 (en) 2020-09-28 2022-05-10 Dominant Opto Technologies Sdn Bhd Lead frame and housing sub-assembly for use in a light emitting diode package and method for manufacturing the same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200364A (en) * 1990-01-26 1993-04-06 Texas Instruments Incorporated Packaged integrated circuit with encapsulated electronic devices
US5053852A (en) * 1990-07-05 1991-10-01 At&T Bell Laboratories Molded hybrid IC package and lead frame therefore
US5291038A (en) * 1990-12-19 1994-03-01 Sharp Kabushiki Kaisha Reflective type photointerrupter
US5548087A (en) * 1993-05-07 1996-08-20 At&T Corp. Molded plastic packaging of electronic devices
US5600179A (en) * 1994-09-27 1997-02-04 Nec Corporation Package for packaging a semiconductor device suitable for being connected to a connection object by soldering
JP2917868B2 (ja) * 1995-07-31 1999-07-12 日本電気株式会社 半導体装置およびその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110696275A (zh) * 2019-10-31 2020-01-17 奇点新源国际技术开发(北京)有限公司 一种线缆节点的塑封方法
CN110696275B (zh) * 2019-10-31 2022-06-21 奇点新源国际技术开发(北京)有限公司 一种线缆节点的塑封方法

Also Published As

Publication number Publication date
CN1121720C (zh) 2003-09-17
JPH10242337A (ja) 1998-09-11
KR100336147B1 (ko) 2002-06-20
TW351840B (en) 1999-02-01
US6181003B1 (en) 2001-01-30
KR19980070092A (ko) 1998-10-26
JP3737233B2 (ja) 2006-01-18

Similar Documents

Publication Publication Date Title
CN1151554C (zh) 半导体器件、其制造方法以及组合型半导体器件
CN1065662C (zh) 半导体芯片封装及其制造方法
CN1246899C (zh) 半导体装置
CN1052340C (zh) 塑料模制的具有小平直度偏差引线的集成电路组件
KR100299949B1 (ko) 박형반도체장치,그것을이용한모듈구조체및그반도체장치의기판실장방법
CN1041254C (zh) 三维结构的半导体器件
CN1124652C (zh) 半导体器件装配构造和半导体器件装配方法
CN1047470C (zh) 半导体器件
CN1109217A (zh) 半导体装置及其制造方法
US20100193922A1 (en) Semiconductor chip package
CN1043828A (zh) 半导体器件的制造方法
CN1638120A (zh) 半导体组装体及其制造方法
CN1213173A (zh) 半导体集成电路装置
JP2907801B2 (ja) ボトムリード半導体パッケージ及びその製造方法
CN1197290A (zh) 半导体器件
CN1121720C (zh) 塑封半导体器件及其制造方法
CN1193186A (zh) 载体薄片和使用了载体薄片的集成电路装置
CN1505146A (zh) 多芯片模块
US20080265432A1 (en) Multi-chip package and method of manufacturing the multi-chip package
CN1206729C (zh) 半导体装置及其制造方法、电路板和电子仪器
TWI571995B (zh) 具有多連接導線之設備、具有多連接導線之晶片封裝以及用於保留導線框次結構之外部針腳的方法
CN1441495A (zh) 半导体装置及其制造方法、电路板和电子仪器
CN1606160A (zh) 半导体装置及其制造方法、电路基板以及电子设备
CN110808242B (zh) 一种led灯串及其制造方法
CN1023675C (zh) 半导体器件的制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee