CN1183643A - 半导体器件及其所用的引线架 - Google Patents

半导体器件及其所用的引线架 Download PDF

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CN1183643A
CN1183643A CN97122148A CN97122148A CN1183643A CN 1183643 A CN1183643 A CN 1183643A CN 97122148 A CN97122148 A CN 97122148A CN 97122148 A CN97122148 A CN 97122148A CN 1183643 A CN1183643 A CN 1183643A
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lead
pressing position
wire
semiconductor chip
semiconductor device
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奥秋胜己
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NEC Corp
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Abstract

本发明公开了一种引线在芯片上的结构的半导体器件,它有一块在其上设有多个焊接点的半导体芯片和在半导体芯片上配置的多条引线,每条引线包含外引线与内引线,并有形成在内引线尖端用焊线与一个焊接点相连的压合部位;其中有至少一条内引线和至少一条内引线的压合部位被配置成围绕着除至少一条内引线和至少一条内引线的压合部位之外的一条内引线及其相关的一个压合部位。

Description

半导体器件及其所用的引线架
本发明涉及一种半导体器件以及用于半导体器件具有LOC(引线在芯片上面)结构随半导体芯片封入封装的引线架。
对超大规模集成电路(VLSI)的市场需求日益转向提高速度和容量以及朝着多样化的方向。例如，即使就用于一般目的的16MDRAM(16兆位动态随机存取存贮器)产品的输入/输出结构而论，市场需×4的产品(×4位输入/输出RAM产品)、×8的产品(×8位输入/输出RAM产品)、×16的品(×16位输入/输出RAM产品)等等。这些产品的半导体芯片是按各自的封装状态配在引线腿的数目和引线腿的排列互不相同的封装之中的。具体地说，构成这些产品所用装配半导体芯片的封装状态是按照，×4的产品封装在26条腿的封装内，×8的产品封装在28条腿的封装内，或是×16的产品封装在50条腿的封装内。还有产品中半导体芯片自身的面积则按照×4的产品、×8的产品、及×16的产品的顺序增大。
另一方面，利用半导体器的微小型化减少笔记本电脑、便携式话机等的尺寸是主流趋向。因而，为了提高半导体器件的包装密度就要求半导体器件自身的封装微小型化。适应这种需求的一种半导体器件结构是在标准宽度和厚度的封装中封入半导体芯片的LOC半导体结构。为了在这样的情况下以有限的开发费用、工艺数目和工作期限开发适应这些市场需求的产品，VLSI的开发人员进行了能将同一类型的半导体芯片封装在引线腿的数目和引线腿排列不相同的各种封装之中的设计。
例如，为了将同类的半导体芯片封入不同类型的封装中，在此以前如图6和7中所示，在半导体芯片Pa上设置了专用于各类封装的焊接点6a、7a；6b、7b；6、7c；6d、7d。换句话说，如在图6中所示的32条腿DIP(双列直插式封装)中，32条腿DIP的焊接点6a、6b、6c、6d是为实现32条腿的DIP半导体器件供在半导体芯片Pa上选择焊接寻址腿A0、A1、A11和A10而专设的。同样，如在图7中所示的50条腿的DIP中，50条腿DIP的焊接点7a、7b、7c、7d是为实现50条腿的DIP半导体器供在半导体芯片Pa上选择焊接寻址腿A0、A1、A10和A11而专设的。
类似的情况，如图8中所示在日本专利公报昭60-98652号所公开的技术中，为实现DIP的半导体器件，DIP专设了为在半导体芯片Pb选择焊接Vcc(电源)腿和GND(接地)腿而专设了焊接点8a和8b，同时，使用了与图8中所示的同一类半导体芯片Pb，为了实现ZIP(之字形直插式封装)的半导体器件，如图9中所示，ZIP专设了为在半导体芯片Pb上选择焊接Vcc腿和GND腿的焊接点9a和9b。
然而，这样的半导体器件有如下的两个问题。第一个问题就是半导体芯片由于要为各类封装设置专用的焊接点6a-6d、7a-7d、8a、8b、9a、9b而增加了面积。实际上，当用如图中所示的前述DIP装配DRAM之类的半导体器件时，只要人们考虑到半导体芯片的面积，由于只需使用DIP专用的焊点8a和8b，不用的焊点9a和9b就完全成为多占的面积。与此相同，当用如图9中所示的前述ZIP装配半导体器件时，只要人们考虑到半导体芯片的面积，可以用ZIP专用的焊点9a和9b，而焊点8a和8b就完全成为多占的面积。
同样，当用图6中所示的前述32条腿的DIP装配DRAM之类的半导体器件时，只需用32条腿DIP专用的焊点6a-6d；因而，只要人们考虑到半导体芯片的面积，不用的50条腿  的DIP专用焊点7a-7d就完全成为多占的面积。与其类似，当用如图7中所示的前述的50条腿DIP装配半导体器件时，可用50条腿DIP的专用焊点7a-7b；因而，只要人们考虑到半体芯片的面积，32条腿DIP的专用焊点6a-6d就完全成为多占的面积。
第二个问题就是通过一条外引线与一输入/输出焊接点连接的信号导体的端点电容是随为各类封装设置的专用焊点6a-6d、7a-7d、8a、8b、9a、9b成正比地增加，从而就导致半导体器件的电学特性下降。
事实上，图8和图9中示出了为使同类半导体芯片Pb不论是在DIP还是在ZIP封装中都能装配的半导体器件结构。对于用DIP装配的情形，半导体芯片Pb的信号导体是用铝线等与输入/输出端的DIP专用焊点8a电连接的，对于ZIP的专用焊点9a，与DIP的专用焊点8a的情况相同。因此，对于作为输入/输出端的DIP专用焊接点8a的半导体芯片Pb的信号导体就有了一个ZIP专用焊点9a的冗余电容。这样一个ZIP专用焊点9a的冗余电容在以往一般用途的16兆位RAM工艺中高达400fF(毫微微法)。这-400fF的冗余电容使如象一同步DRAM之类的高速半导体器件全部输入信号导体的端点电容提高多达15％。
这造成半导体芯片Pb的信号导体电学特性下降，影响着经外引线连接的自DIP专用焊接点8a的输入和输出。
考虑到半导体芯片Pb的信号导体，影响着经外引线连接的自DIP专用焊点8b的输入的输出，作为输入/输出端的DIP专用焊点的信号导体是用铝线等作连接的，它同样适用于ZIP的专用焊点9b。因此，作为输入/输出端的DIP专用焊点8b的半导体芯片Pb的信号导体具有一个ZIP的专用焊点9b的冗余电容。从而，这就带来了以上所讨论的与DIP专用焊接点8b连接的信号导体的端点电容增加，导致这一信号的电学特性下降。
此外，用图9中所示的ZIP装配半导体器件与用图6中所示的32条腿的DIP或图7中所示的50条腿的DIP装配半导体器件的情形具有相同的问题。
在一段时间里，为避免与特定封装的专用焊点连接的信号导体端点电容的增加影响到经外引线的输入和输出，从而避免电学特性下降，考虑到采用以下测量方法。这种方法是通过为各类封装制备由封装专用的铝工艺交叉线并用铝线转换多余的焊接点以分隔开不为封装所需的多余焊接点。然而，在此情况下，与各类封装对应的专用铝工艺交叉线必需为每一类封装制备。问题是大量的工艺步骤和包括在产品开发费用中的整个耗费，这些如为制备对应于每一类封装的专用铝工艺交叉线有关的设计费用以及为制备对应于每一类封装的专用铝工艺交叉线所用铝扩散新工艺的扩散工艺费用。
按照以上考虑，本发明的目的是要提供一种半导体器件和引线架，它使半导体器件的结构能够避免增加信号导体与焊点连接的端点电容影响经外引线的输入和输出从而避免电学特性下降，特别是借助于适宜的结构，无需增加半导体芯片的面积将同一类半导体芯片封入引线腿数和引线腿排列不相同的不同类型封装中以获得一组半导体器件。
为了解决上述问题，按照本发明的第一种方式，提供了一种引线在芯片上的结构的半导体器件，它包括：一个在其上设有多个焊接点的半导体芯片；以及多个配置在半导体芯片上的引线，每一引线包含一外引线和一在其尖端形成一压合部位并与焊接点之一焊线连接的内引线；其中至少有一条内引线和至少一条内引线的压合部位是被配置成围绕着除至少一条内引线和至少一条内引线的压合部位之外的一条内引线及一相关联的压合部位。
在上述第一种方式的半导体器件中，前述弯曲结构造成形成在至少一条前述内引线尖端的前述压合部位和形成在至少一条前述其它内引线尖端的压合部位的顺序不同于与至少一条其它内引线相连的前述外引线和与至少一条内引线相连的外引线的顺序。
由于在结构中前述半导体芯片的前述焊接点正好有一个与引线的一条外引线连接，从而使同一类半导体芯片能够装配在引线腿数和引线腿排列不相同的不同类型的封装中。因而，通过一外引线输入/输出的与一焊接点连接的信号导体的端点电容就能避免增加，也从而避免了电学特性的下降。
在上述第一种方式中，半导体芯片最好是用树脂密封的。
同样，当有至少两组引线与至少一条内引线和至少一条其它的内引线有关时就更为有效。
同样，按照本发明的第二种方式，提供了一种引线在芯片上结构的半导体器件，它包括：一个在其上设有多个焊接点的半导体芯片；以及在半导体芯片上配置的多个引线，每一引线包含一条外引线和一条在其尖端形成有一压合部位且用焊线与一焊接点连接的内引线，内引线和压合部位被置于半导体芯片上；其中至少有一条外引线定为电源腿，而除至少一条外引线之外的至少一条外引线则定为接地腿；并且其中的至少一条内引线与定为电源腿或接地腿的外引线相连，而将至少一条内引线的压合部位设置成绕着除至少一条内引线和至少一条内引线的压合部位以外的一条内引线及其关联的压合部位。
同样，按照本发明的第三种方式，提供了一种用于在其上设有多个焊接点的半导体芯片的引线架，引线架包括：设置在半导体芯片上的多个引线，每一引线包含一条外引线和一条在其尖端形成有一压合部位并用焊线与一个焊接点连接的内引线，其中至少一条内引线以及至少一条内引线的压合部位被设置成绕着除至少一条内引线和至少一条内引线的压合部位以外的一条内引线及其关联的压合部位。
因此本发明能够实现一种半导体器件，其结构可以防止影响到通过外引线的输入和输出的与焊接点相连的信号导体的端点电容增加从而防止电学特性的下降，特别是借助于适宜的结构，无需增加半导体芯片面积，将同类的半导体芯片封装在引线腿数目和引线腿排列不相同的不同类型封装中以获得一组半导体器件。
此外，就结构来说，已经公开的图10中所示日本专利公报昭62-283653号和图11及12中所示日本专利公报昭63-208235号，其中的内引线压合部位的顺序和外引线的顺序不同。然而，这些技术对以上讨论的现有技术存在的问题没有实质性改进，这是由于这两项技术将引线腿数目或是引线腿排列不相同的不同类型封装用于相同类型的半导体芯片。而且，由于两种技术没有LOC的结构，多条内引线和压合部位建立在半导体芯片的周边上。内引线压合部位的顺序与外引线的不同。因而，当被封入一封装内时，压合部位与内引线中的多个形成在半导体芯片的周边上，必须全部封入封装之中。其结果是，当以封装尺寸为基础进行比较时，前述两项报告与用LOC结构的半导体器件比较时就有半导体器件变大的问题，而LOC的结构是本发明的前提。
从以下结合附图所作的说明中，将明显可见本发明的上述及其它目的、优点和特性。
图1为本发明第一实施例32条腿双列直插模塑封装型半导体器件的焊接示意图。
图2为本发明第二实施例50条腿双列直插模塑封装型半导体器件的焊接示意图。
图3为本发明第三实施例32条腿双列直插模塑封装型半导体器件的焊接示意图。
图4为本发明第四实施例50条腿双列直插模塑封装型半导体器件的焊接示意图。
图5为本发明第五实施例双列直插模塑封装型半导体器件部分焊接单元的示意图。
图6为用以说明相关技术的半导体器件的焊接示意图；
图7为用以说明另一项相关技术的半导体器件的焊接示意图；
图8为用以说明现有技术的半导体器件的焊接示意图；
图9为用以说明另一项现有技术的半导体器件的焊接示意图；
图10为提供参考示出的半导体器件的焊接示意图；
图11为提供参考示出的另一半导体器件的焊接示意图；以及
图12为提供参考示出的另一半导体器件的焊接示示意图；
下面，参照附图对本发明的最佳实施例进行说明。
如图1中所示，本发明第一实施例的半导体器件有一带压合部位(引线端)1c和内引线1b的LOC结构，它封在模塑封装1a中，排列在半导体芯片1d上。形成在半导体芯片1d表面上的焊接点1d上。形成在半导体芯片1d表面上的焊接点(金属薄膜部位)1e通过焊接线1f与压合部位1c相连。最后，未绘出的此半导体器体与外部系统的电路是通过外引线1g连接的。
而且，将与此半导体芯片1d具有相同尺寸和形式的半导体芯片用于其它类型引线腿数目和引线腿排列都不同的半导体器件中。在图1的15号腿(15pin)A5中，形成在半导体芯片1d表面上的一个焊接点1h通过焊接线1i与压合部位1j连接；此压合部位1j则通过一内引线1k与一外引线11相连。按照同一方式，在16号腿(16pin)Vcc中，形成在半导体芯片1d表面上的一个焊接点1m通过焊接线1n与压合部位1o连接；此压合部位1o则通过一内引线1p与一外引线1q相连。
在此图中所示的这一半导体器件，16号腿(16pin)Vcc的内引线1p和压合部位1o是绕着15号腿(15pin)A5的内引线1k和压合部位1j的，造成16号腿(16pin)Vcc的内引线的弯曲结构。
由于这种结构，从绕着15号腿(15pin)A5的压合部位1j和内引线1k的在16号腿(16pin)Vcc内引线1p尖端形成的压合部位1o起到被围绕的在15号腿(15pin)A5内引线尖端形成的压合部位部位1j止的顺序，它与从与被围绕的内引线1k相连的15号腿(15pin)A5外引线11起到与围绕的内引线1p相连的16号腿(16pin)Vcc外线1q止的顺序不同。
此外，如此图中所示的结构是使17号接地腿(17pinGND)的压合部位和内引线绕着18号腿(18pin)A6的压合部位和内引线；17号接地腿(17pinGND)的内引线被弯曲。这就使得在结构中自绕着18号腿(18pin)A6的内引线和压合部位的形成在17号接地腿(17pinGND)内引线尖端的压合部位起到在被围绕着的18号腿(18pin)A6内引线的尖端形成的压合部位止的顺序和从与被围绕的18号腿(18pin)A6相连的18号腿A6的外引线起到与包围的17号接地腿(17pinGND)内引线相连的17号接地腿的外引线止的顺序相反。
将半导体芯片1d用焊线与具有上述弯曲结构的引线架的压合部位焊接之后经树脂密封制备成具有上述结构的半导体器件。
而且，只要内引线1p不具有弯曲结构，就无法避免如图1中用虚线HL所示的增加半导体芯片1d的面积并且不能指望提高成品。然而，采用此例的结构，由于能够缩小半导体芯片的面积而提高了成品率。
而且，此例的半导体芯片1d还能包含在不同类型的半导体器件(以图2中所示为例)之中，这些半导体器件引线腿的数目或引线腿的排列不相同而没有一条内引线弯曲成其它的结构。
因而，采用比例中的结构就有可能将同一类半导体芯片装配在一引线腿数目和引线腿排列不相同的封装中而无需设置多余的焊接点。从而，由于没有增加半导体芯片的面积而提高了成品率。此外，还由于不必设置多余的焊接点，也能避免为通过外引线输入/输出而使信号导体与焊接点相连的端点电容的增加；使得电学特性的下降能获避免。
如图2中所示，本发明第二实施例的半导体器件具有带压合部位2c和内引线2b的LOC结构，它们密封在一模塑封装2a中，排列在半导体芯片2d上。而且，此半导体芯片2d与图1中所示半导体芯片1d的尺寸和形式相同。形成在半导体芯片2d表面上的焊接点2e通过焊线2f与压合部位2c相连。最后，此半导体器件与未绘出的外部系统电路径外引线2g相连。
在图2的24号腿(24pin)A5中，形成在半导体芯片2d表面上的焊接点2h经焊线2i与压合部位2j相连；此压合部位2j则经内引线2k与外引线21相连。按照同样的方式，在25号腿(25pin)Vcc中，形成在半导体芯片2d表面上的焊接点2m经焊线2n与压合部位2o相连；此压合部位2o则经内引线2p与外引线2q相连。
在该图所示的半导体器件中，25号腿(25pin)Vcc的内引线2p和压合部位2o绕着24号腿(24pin)A5的内引线2k和压合部位2j，造成25号腿Vcc的内引线2p的弯曲结构。
由于这种结构，自围绕着24号腿(24pin)A5压合部位2j和丙引线2k的25号腿(25pin)Vcc内引线路2p尖端处形成的压合部位2o起到被围绕的24号腿(24pin)A5内引线2k的尖端处形成的压合部位2j的顺序不同于自与被围的与内引线2k相连的24号腿(24pin)A5外引线起到与包围的内引线2p相连的25号腿(25pin)Vcc的外引线2q的顺序。
此外，如此图中所示的结构是使26号接地腿(24pin GND)的压合部位和内引线围绕着27号腿(27pin)A6的压合部位和内引线；26号接地腿的内引线被弯曲。这样产生的结构，自围绕着27号腿(27pin)A6的内引线和压合部位的26号接地腿(26pin GND)内引线尖端处形成的压合部位起到被围绕的27号腿(27pin)A6内引线尖端处形成的压合部位的顺序和自被包围的与27号腿(27pin)A6内引线相连的27号腿A6的外引线起到与包围的26号接地腿(26pinGND)内引线相连的26号接地腿的外引线的顺序相反。
用此第二实施例可以同样得到第一实施例所讨论过的同类效果。具体地说，由于能够缩小半导体芯片的面积而提高了成品率。
如在图3中所示，本发明第三实施例的半导体器件具有带压合部位3c和内引线3b的LOC结构，它们密封在模塑的封装3a中，排列在半导体芯片3d上。形成在半导体芯片3d表面上的焊接点3e通过焊接线3f与压合部位3c相连。最后，此半导体器件与一未绘出的外部系统电路经外引线3g相连。
在图3的11号腿(11pin)A1中，形成在半导体芯片3d表面上的焊接点3h通过焊接线3i与压合部位3j相连；此压合部位3j则经内引线3k与外引线31相连。按照相同的方式，在10号腿(10pin)A0中，形成在半导体芯片3d表面上的焊接点3m通过焊接线3n与压合部位3o相连；此压合部位3o则经内引线3p与外引线3q相连。
如图中所示，在此半导体器件的结构中，由于10号腿(10pin)A0的压合部位3o和内引线3p围绕着11号腿(11pin)A1的压合部位3j和内引线3k，10号腿(10pin)A0的内引线3p是弯曲的。
由于这种结构，自围绕着11号腿(11pin)A1压合部位3j和内引线3k的10号腿(10pin)A0内引线3p尖端处形成的压合部位3o起到被围绕的11号腿(11pin)A1内引线3k尖端处形成的压合部位3j的顺序，不同于自与被围绕的内引线3k相连的11号腿(11pin)A1的外引线起到与包围的内引线3p相连的10号腿(10pin)A0的外引线3q的顺序。
此外，如图中所示的结构是使23号腿(23pin)A11的压合部位和内引线围绕着22号腿(22pin)A10的压合部位和内引线；23号腿(23pin)A11的内引线是弯曲的。这样产生的结构，自围绕着22号腿(22pin)A10内引线和压合部位的23号腿(23pin)A11内引线尖端处形成的压合部位起至被围绕的22号腿(22pin)A10内引线尖端处形成的压合部位的顺序，和自与被围绕的22号腿(22pin)A10内引线相连的22号腿A10的外引线起到与围绕的23号腿(23pin)A11内引线相连的23号腿A11的外引线的顺序相反。
在将半导体芯片3d用焊线焊接到具有上述弯曲结构引线架的压合部位之后经用树脂密封制备成具有上述结构的半导体器件。
如图4中所示，本发明第四实施例的半导体器件具有带压合部位4c和内引线4b的LOC结构，它们密封在一模塑的封装4a中，排列在半导体芯片4d上。而且，此半导体芯片4d与图3中所示半导体芯片3d的尺寸和形式相同。形成在半导体芯片4d表面上的焊接点4e通过焊接线4f与压合部位4c相连。最后，此半导体器件与一未绘出的外部系统电路经由外引线4g相连。
在图4的19号腿(19pin)A0中，形成在半导体芯片4d表面上的焊接点4h经焊接线4i与压合部位4j相连；此压合部位4j经内引线4k与外引线41相连。按照同样的方式，在20号腿(20pin)A1中，形成在半导体芯片4d表面上的焊接点4m经焊接线4n与压合部位4o相连；此压合部位4o经内引线4p与外引线4q相连。
如图中所示，在此半导体器件的结构中，由于20号腿(20pin)A1的压合部位4o和内引线4p围绕着19号腿(19pin)A0的压合部位4j和内引线4k，20号腿(20pin)A1的内引线4p是弯曲的。由于这种结构，自围绕着19号腿(19pin)A0压合部位4j和内引线4k的20号腿(20pin)A1内引线4p尖端处形成的压合部位4o起到被围绕的19号腿(19pin)A0内引线尖端处形成的压合部位4j的顺序，不同于自与被围绕的内引线4k相连的19号腿(19pin)A0的外引线41起到与围绕的内引线4p相连的20号腿(20pin)A1的外引线4q的顺序。
此外，如此图中所示的结构是使31号腿(31pin)A10的压合部位和内引线围绕着32号腿(32pin)A11的压合部位和内引线；31号腿A10的内引线是弯曲的。这样产生的结构，使自围绕32号腿(32pin)A11内引线和压合部位的31号腿(31pin)A10内引线尖端处形成的压合部位起到被围绕的32号腿(32pin)A11内引线尖端处形成的压合部位的顺序，和自与被围绕的32号腿(32pin)A11的内引线相连的32号腿A11外引线起到与围绕的31号腿(31pin)A10的内引线相连31号腿的外引线的顺序相反。
将半导体器芯片4d用焊线与上述具有弯曲结构引线架的压合部位焊接之后经树脂密封就制备成上述结构的半导体器件。
采用上述的第三和第四实施例的结构，就有可能将同类的半导体芯片装配在引线腿数目和引线腿排列不相同的封装中而无需装设多余的焊接点。从而，由于未增加半导体芯片的面积而提高了成品率。此外，由于不必装设多余的焊接点而能避免为通过外线引线输入/输出而与焊接点相连的信号导体的端点电容增加；结果能够避免电学特性的下降。
图5为成为本发明第五实施例的双列直插模塑封装型半导体器件的焊接单元的部分示意图。
在图5中所示，这种半导体器件具有带压合部位5c和内引线5b的LOC结构，它们密封在一模塑封装5a中，排列在半导体芯片5d上。形成在半导体芯片5d表面上的焊接点5e通过焊接线5f与压合部位5c相连。最后，这一半导体器件和一未绘出的外部系统电路经外引线5g相连。
5B引线腿的压合部位和内引线围绕着5A引线腿的压合部位和内引线，形成一弯曲结构；此外，为形成弯曲结构，5c引线腿的压合部位和内引线还包围着围绕5A引线腿压合部位和内引线5B引线腿的压合部位和内引线。其结果产生的结构是使，自主要包围5B引线腿压合部位和内引线及5A引线腿压合部位和内引线的5C引线腿内引线尖端处形成的压合部位起到包围着的5A引线腿内引线尖端处形成的压合部位的顺序(实际上的顺序为，5C线腿的压合部位、5B引线腿的压合部位和5A引线腿的压合部位)，不同于自与被包围的5A引线腿内引线相连的5A引线腿外引线起到与包围的5C引线腿内引线相连的5C引线腿的外引线的顺序(实际上的顺序为，5A引线腿的外引线、5B引线腿的外引线、和5C引线腿的外引线)。
采用此第五实施例同样能得到第三和第四实施例所描述的同一类效果。具体地说就是能将同一类半导体芯片装配在引线腿数目和引线腿排列不相同的封装中而又无需装设多余的焊接点。
非常明显，本发明不受上述实施例所限，它可以在未偏离本发明的范围与精神的情况下进行变动和改进。

Claims (12)

1、一种属于引线在芯片上的结构的半导体器件，它包括：
在其上设有多个焊接点的一块半导体芯片；以及
配置在所述半导体芯片上的多条引线，每条所述引线包含一外引线和一内引线，所述内引线有一形成在其尖端并用焊线与一个所述的焊接点相连的压合部位；
其特征在于，其中至少有一条所述的内引线和所述至少一条内引线的压合部位被配置成围绕着除所述至少一条内引线和所述至少一条内引线的压合部位之外的一条内引线和所关联的一个压合部位。
2、按照权利要求1所述的半导体器件，其特征在于，所述至少一条内引线的压合部位与所述至少一条其它内引线的压合部位所配置的顺序不同于从所述至少一条内引线伸出的外引线与从所述至少一条其它内引线伸出的外引线所配置的顺序。
3、按照权利要求1所述的半导体器件，其特征在于，它限定一种将所述半导体芯片用树脂密封在其中的模塑封装类型。
4、按照权利要求1所述的半导体器件，其特征在于，它限定其中的若干所述外引线排成两行的双列直插式的封装类型。
5、按照权利要求1所述的半导体器件，其特征在于，它限定为随机存取存贮器(RAM)。
6、按照权利要求1所述的半导体器件，其特征在于，所述半导体芯片与具有不同的引线腿数目或引线腿排列的另一类半导体器件中所用的另一种半导体芯片具有相同的外形和尺寸。
7、按照权利要求1所述的半导体器件，其特征在于，它包括至少两组包含所述至少一条内引线和所述至少另一条内引线的引线组。
8、按照权利要求7所述的半导体器件，其特征在于，所述的至少两组引线组被配置在所述半导体芯片的两侧。
9、一种属于引线在芯片上的结构的半导体器件，它包括：
在其上设有多个焊接点的一块半导体芯片；以及
配置在所述半导体芯片上的多条引线，每条所述引线包含一外引线和一内引线，所述内引线有一形成在其尖端并用焊线与一个所述的焊接点相连的压合部位，所述内引线和所述压合部位置于所述的半导体芯片上；
其特征在于，其中至少有一条所述的外引线确定为一电源引线腿而除所述至少一条外引线之外的至少一条外引线则确定为一接地引线腿；以及
其中至少有一条内引线与确定为电源引线腿或所述接地腿的外引线相连而且所述至少一条内引线的压合部位被配置成围绕着除所述至少一条内引线和所述至少一条内引线的压合部位之外的一条内引线和相关联的一压合部位。
10、一种用于在其上设有多个焊接点的半导体芯片的引线架，所述引线架包括：
配置在所述半导体芯片上的多条引线，每条所述引线包含一外引线和一内引线，所述内引线有一形成在其尖端并用焊线与一个所述的焊接点相连的压合部位；
其特征在于，其中至少有一条所述内引线和所述至少一条内引线的压合部位被配置成围绕着除所述至少一条内引线和所述至少一条内引线的压合部位之外的一条内引线和相关联的-压合部位。
11、按照权利要求10所述的引线架，其特征在于，其中所述至少一条内引线的压合部位和所述至少一条其它内引线的压合部位所配置的顺序不同于从所述至少一条内引线伸出的外引线和从所述至少一条其它内引线伸出的外引线所配置的顺序。
12、按照权利要求10所述的引线架，其特征在于，它包括至少两组包含所述至少一条内引线和所述至少一条其它内引线的引线组。
CN97122148A 1996-11-25 1997-11-25 半导体器件及其所用的引线架 Withdrawn CN1183643A (zh)

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Publication number Priority date Publication date Assignee Title
CN102569242A (zh) * 2012-02-07 2012-07-11 日月光半导体制造股份有限公司 整合屏蔽膜的半导体封装件及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102569242A (zh) * 2012-02-07 2012-07-11 日月光半导体制造股份有限公司 整合屏蔽膜的半导体封装件及其制造方法

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