CN1181843A - 射频功率晶体管的发射极镇流旁路 - Google Patents

射频功率晶体管的发射极镇流旁路 Download PDF

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CN1181843A
CN1181843A CN96193307A CN96193307A CN1181843A CN 1181843 A CN1181843 A CN 1181843A CN 96193307 A CN96193307 A CN 96193307A CN 96193307 A CN96193307 A CN 96193307A CN 1181843 A CN1181843 A CN 1181843A
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T·约翰森
L·莱顿
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Telefonaktiebolaget LM Ericsson AB
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
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    • H01L29/73Bipolar junction transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73Bipolar junction transistors
    • H01L29/7302Bipolar junction transistors structurally associated with other devices
    • H01L29/7304Bipolar junction transistors structurally associated with other devices the device being a resistive element, e.g. ballasting resistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/0652Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H01L27/0658Vertical bipolar transistor in combination with resistors or capacitors

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Abstract

提供了一种设备和方法来对功率晶体管的发射极镇流电阻器进行旁路,从而提高晶体管的增益。在一个叉指型的功率晶体管中,对发射极镇流电阻器的旁路要求用一个并联电容器对每一个分立的镇流电阻器进行旁路。因此,在硅芯片上完成旁路。更确切地说,根据本发明的一个实施例,RF功率晶体管包括一个硅芯片、一个制作在硅芯片上的发射极镇流电阻器(13)以及一个制作在硅芯片上且与发射极镇流电阻器(13)并联连接的旁路电容器(40)。此电阻器可以是一个扩散电阻器,而电容器可以是一个多晶硅上金属电容器。根据本发明的另一实施例,提供了一种提高RF晶体管增益的方法,此RF晶体管制作在硅芯片上且带有一个制作在硅芯片上的发射极镇流电阻器,其中一个电容器制作在硅芯片上且与镇流电阻器并联连接。

Description

射频功率晶体管的发射极镇流旁路
发明领域
本发明涉及到功率晶体管,更确切地说是涉及到硅双极型射频(RF)功率晶体管。这种晶体管通常用于无线基站放大器的放大级中,但也广泛地用于其它与RF有关的应用中。
背景技术
大多数现代RF双极功率晶体管都含有大量并联的晶体管区段,以便借助于分配大量电流、减小寄生参量并提供散热而达到高的功率容量。最普通的布局方式即叉指式布局,是由硅顶面上金属化条连接的平行的基区和发射区的交替指条组成。
有源双极晶体管具有正的温度系数。这就是说,当温度上升时,静态收集极电流也上升。由于特定电流时的基极到发射极的电压Vbe以大约0.002V/℃的速率下降,从而出现了这种情况。若晶体管的偏置电源保持恒定而温度升高,则Vbe下降而收集极电流上升。收集极电流的这一上升导致功率耗散的进一步增大,它反过来又引起晶体管的结温更进一步升高。若不施加其它影响,则这种情况将使晶体管因热而失去控制,其电流将达到使晶体管失效的程度。
有许多从外部来控制这种情况的不同的方法。最普通的方法是这样一种电路,它探测收集极电流并提供负反馈以便在温度改变时保持收集极电流恒定。另一种方法是在偏置网络中采用温度特性与Vbe相反的温度敏感元件。第三种方法是采用发射极电阻器来接地。随着收集极电流的上升,Vbe下降,因而基极电流被降低。
晶体管外部的任何电流本身都增加复杂性并增加电路的成本。成本效益最大的施加温度补偿的方法是发射极接地电阻器。虽然此方法对于补偿环境温度的变化是非常有效的,但很难在物理上将这一电阻器放置在离晶体管足够近的地方以尽量减小发射极引线电感。
半导体制造厂家已知放置发射极电阻器的最佳地点是将其与有源晶体管一起设置在硅芯片上。用这种方法可将发射极电阻器的串联电感保持在最小值。在半导体工业中,发射极电阻器常常被称为发射极镇流电阻器,或简称为镇流电阻器。通常,较高的功率密度要求较大的发射极镇流电阻值。
发射极镇流电阻re对功率增益有不利的影响。较高的功率增益是更为可取的,因为对于同样大小的功率输出所要求的输入功率更小。
通常,双极晶体管的本征发射极电阻比之发射极镇流电阻是可以忽略的,以至对于实际的目的可将发射极电阻认为只等于发射极镇流电阻。利用简化的晶体管模型,双极晶体管的功率增益由下式给出: Gain ( dB ) = 10 log β [ R L r e ]
其中β是收集极电流对基极电流之比,RL是收集极负载电阻,re是发射极电阻。上述模型不包括发射极引线电感之类的较高频率效应,并且不包括收集极反馈电容对功率增益的可能的不利影响。即使如此,也已经验证确定,较低的re通常导致较高的增益。具体地说,在上述模型下,每当re降低1/2时,增益就增大3dB。
在电路设计中所用的消除re对增益的影响的普通方法是用电容器来旁路re。若电容器的容抗等于re,则re与电容器并联的总阻抗被降低1/2。此时,双极晶体管可更准确地模型如下: Gain ( dB ) = 10 log β [ R L ( ( r e + X c ) / ( r e · X c ) ) ]
如上述结果所示,通过使发射极镇流电阻器旁路,可克服发射极镇流电阻器对增益的不利影响。所要求的则是一种使所述类型功率晶体管中的发射极镇流电阻器旁路的技术。
发明概要
一般说来,本发明提供了一种用于使功率晶体管的发射极镇流电阻器旁路从而提高晶体管增益的设备和方法。在叉指型功率晶体管中,旁路发射极镇流电阻器要求对每一个分立的镇流电阻器用一个电容器与之并联旁路。因此,旁路是在硅芯片上完成的。更确切地说,根据本发明的一个实施例,RF功率晶体管包括一个硅管心、一个制作在硅管心上的发射极镇流电阻器、以及一个制作在硅管心上且与发射极镇流电阻器并联连接的旁路电容器。根据本发明的另一实施例,RF功率晶体管包括一个硅管心以及一个制作在硅管心上的带有多个平行的电极指条的叉指式电极。扩散区形成在电极指条的下方。电阻器制作在硅管心上且在第一节点处与电极指条串联连接。包括连接焊点区的金属化区制作在硅管心上且在第二节点处用金属线路连接于电阻器。导电层处于金属化区下方且在第一节点处连接于电极指条。隔离层将金属化区同导电层分隔开。根据本发明的又一实施例,提供了一种提高RF晶体管的增益的方法,这种晶体管制作在硅芯片上且带有一个制作在硅芯片上的发射极镇流电阻器,其中在硅芯片上制作了一个电容器且与镇流电阻器并联连接。
附图简述
结合附图从下面的描述中将进一步理解本发明。在这些附图中:
图1是双极功率晶体管中常规发射极镇流电阻器的剖面图;
图2是包括MOS旁路电容器结构的发射极镇流电阻器的剖面图;
图3是图2的MOS电容器结构的等效电路图;
图4是集成于典型RF功率晶体管结构中的多晶硅/氧化物/金属MOS电容器结构的剖面图;
图5是根据本发明一个实施例的RF功率晶体管中旁路电容器布局的详细平面图;以及
图6是图5的MOS电容器结构的等效电路图。
优选实施例的详细描述
为了对功率晶体管的发射极镇流电阻器作容性旁路,需要有一种方法来实现电容量足够大的电容器。由于MOS电容器的线性极好、具有高的击穿电压和低的温度系数且各晶体管的电容量能够以良好的一致性加以制造,故在双极工艺中被最普遍地采用。反向偏置的PN结只要一直保持在反向偏置情况,也可采用。但大的电容量要求高的掺杂水平,这会导致得到的结构具有无法接受的击穿电压。
参照图1,发射极镇流电阻器的制作方法(如在常规双极功率晶体管中那样)如下:在N型衬底11中提供一个P型扩散区13,其一端用金属引线15连接到一个发射极指条对,并在另一端用金属引线17连接到发射极连接焊点(未示出)。制作在同一金属化层上的金属引线15和金属引线17用部分氧化层(分别为19和21)与衬底11隔离。
参照图2的双极工艺中的最简单方法,为了额外提供MOS电容器,在工艺中加入了一个额外的掩蔽步骤以便在扩散区13之上确定一个生长薄层二氧化硅23的区域。然后将金属化层25置于薄的氧化层上,从而得到电容量大而击穿电压高的电容器。
但如图3所示,在扩散区13和衬底区11(晶体管 收集极)之间出现由结的耗尽电容造成的很大的寄生电容。换言之,扩散区13变成寄生电容器的一个平板,而衬底11变成另一个平板。此电容占据着位于扩散区与衬底之间交界面处的PN结的耗尽区。这一寄生电容由于会提高收集极一发射极电容并降低采用此晶体管的放大器的带宽,因而是不利的。
降低这一寄生电容的一个方法是采用多晶硅/氧化物/金属电容器。参照图4,其中N型衬底11、形成P+镇流电阻器的P型扩散区13、以及氧化区域19和21都与图1的常规安排相同。同时示出的是RF晶体管的一个有源发射极区27。与图2的MOS电容器相反,一层高掺杂的多晶硅29被用来形成电容器的下电极,且通过可制成为数μm厚的氧化区21将其与衬底隔离。结果,对衬底的电容被大为降低。在多晶硅层29之上生长了一个薄的氧化层37并在电容器的二平板(多晶硅层29和发射极焊点金属化31)之间形成一个介电层。金属化33将一对发射极指条连接到镇流电阻器13,并将镇流电阻器13连接到多晶硅层29。
得到的图4的多晶硅-金属电容器40是一个性质与图2的电容器相似的MOS电容器。为了将图4所示的电容器加入到典型的高频晶体管工艺中,只需要包括一个或二个附加的掩蔽步骤的标准的硅工艺步骤。多晶硅层29应当重掺杂以便尽量减小电容器电极中的耗尽效应。亦即,若多晶硅没有被重掺杂,则多晶硅在某些偏压下可能载流子耗尽,造成与氧化物电容串联的电容。这一耗尽导致总电容降低,而且电容值依赖于电压,线性很差。
图5示出了旁路电容器40的典型布局的简化细节,此处所示的只有4个连接于一个焊点41的发射极(33,34,36和38)。一个实际晶体管可以包含几百个连接于一个焊点的发射极。线IV-IV表示图4所示的剖面。比之常规布局,此布局已增加了制作MOS电容器40的多晶硅上金属区29。电容器40通常有高达1fF/μm2的电容值。
图5中多晶硅上金属电容器40的宽度依赖于所需的电容。例如,若对于一个1560个发射极指条布局要求50pF以便在2GHz时获得1.6Q的阻抗,则如果在多晶硅顶部使用300的二氧化硅,图5所示的多晶硅上金属电容器的宽度只需37μm。增大了的布局尺寸应与40-60μm的典型发射极指条尺度及高达100×100μm的典型连接焊点的尺寸来进行比较。
图6示出了布局的等效电路,其中一个RF功率晶体管50连接到一个被一个旁路电容器40′旁路的镇流电阻器13′。
本技术领域的普通熟练人员将会理解,本发明可用其它的特定形式来体现而不超越其构思与主要特点。因而此处公开的实施例无论从哪方面来看都是示例性的而非限制性的。本发明的范围由所附权利要求而不是由前面的描述来阐明,而且符合其等效意义和范围的所有改变都被认为包括在其中。

Claims (8)

1.一种RF功率晶体管,它包含:
一个硅管心;
一个制作在硅管心上的带有多个平行的电极指条的叉指式电极;
制作在上述电极指条下方的扩散区;
一个制作在硅管心上且在第一节点处与上述电极指条串联连接的电阻器;
一个制作在硅管心上的包括一个连接焊点区的金属化区;
一个连接于上述金属化区且在第二节点处连接于上述电阻器的金属通路;
一个位于上述金属化区下方且在上述第一节点处连接于上述电极指条的导电层;以及
一个将上述金属化区与上述导电层分隔开的隔离层。
2.权利要求1的设备,其中所述的导电层是掺杂的多晶硅。
3.权利要求2的设备,其中所述的隔离层是一个氧化物层。
4.一种RF功率晶体管,它包含:
一个硅管心;
一个制作在上述硅管心上的发射极镇流电阻器;以及
一个制作在上述硅管心上且与上述发射极镇流电阻器并联连接的旁路电容器。
5.权利要求4的设备,其中所述的发射极镇流电阻器是一个扩散电阻器。
6.权利要求5的设备,其中所述的电容器是一个多晶硅上金属的电容器。
7.一种提高RF晶体管的增益的方法,此RF晶体管制作在硅芯片上,且带有一个制作在硅芯片上的发射极镇流电阻器,包含下列步骤:
在硅芯片上制作一个电容器;以及
将电容器与镇流电阻器并联连接。
8.一种提高RF晶体管的增益的方法,此RF晶体管制作在硅芯片上,且带有多个制作在硅芯片上的发射极镇流电阻器,包含下列步骤:
在硅芯片上制作一个电容器;以及
将电容器与每个镇流电阻器单独地并联连接。
CN96193307A 1995-02-24 1996-02-16 一种制作在半导体管芯上的功率晶体管 Expired - Fee Related CN1077333C (zh)

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US08/393,683 1995-02-24
US08/393,683 US5684326A (en) 1995-02-24 1995-02-24 Emitter ballast bypass for radio frequency power transistors

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EP (1) EP0811249B1 (zh)
JP (1) JPH11500868A (zh)
KR (1) KR100359978B1 (zh)
CN (1) CN1077333C (zh)
AU (1) AU4852596A (zh)
CA (1) CA2213611A1 (zh)
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FI (1) FI973463A (zh)
HK (1) HK1018121A1 (zh)
WO (1) WO1996026548A1 (zh)

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CN101785109B (zh) * 2007-06-22 2012-02-08 克里公司 具有内部稳定性网络的rf晶体管封装以及形成具有内部稳定性网络的rf晶体管封装的方法

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US5684326A (en) 1997-11-04
FI973463A (fi) 1997-10-23
CN1077333C (zh) 2002-01-02
JPH11500868A (ja) 1999-01-19
KR100359978B1 (ko) 2003-05-16
WO1996026548A1 (en) 1996-08-29
HK1018121A1 (en) 1999-12-10
EP0811249B1 (en) 2002-08-28
DE69623265D1 (de) 2002-10-02
DE69623265T2 (de) 2003-11-27
AU4852596A (en) 1996-09-11
CA2213611A1 (en) 1996-08-29
EP0811249A1 (en) 1997-12-10
FI973463A0 (fi) 1997-08-22
KR19980702471A (ko) 1998-07-15

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