CN118099028A

CN118099028A - Grain processing

Info

Publication number: CN118099028A
Application number: CN202410088838.4A
Authority: CN
Inventors: 赛普里恩·艾米卡·乌佐
Original assignee: Edya Semiconductor Bonding Technology Co ltd
Current assignee: Edya Semiconductor Bonding Technology Co ltd
Priority date: 2017-04-21
Filing date: 2018-04-02
Publication date: 2024-05-28
Also published as: US20240021572A1; TWI748080B; WO2018194827A1; EP4418314A2; TWI847438B; TWI790817B; US20180308819A1; US20210233888A1; US20190189588A1; US10985133B2; KR102391159B1; JP7106575B2; US11742315B2; US10714449B2; KR20190133256A; TW201842634A; US20190371761A1; CN110546754A; TW202209590A; TW202322304A

Abstract

Representative embodiments provide techniques and systems for processing Integrated Circuit (IC) dies. The dies prepared for intimate surface bonding (to other dies, to the substrate, to another surface, etc.) can be treated with minimal handling to prevent contamination of the surfaces or edges of the dies. These techniques include treating the die while they are on a dicing sheet or other device treatment film or surface. The system includes an integrated cleaning assembly configured to simultaneously execute a plurality of cleaning procedures.

Description

Grain processing

The application is a divisional application of patent application number 201880025616.0 filed on 4 months and 2 days in 2018.

Cross-reference to priority claims and related applications

U.S. patent application Ser. No. 15/936,075 and U.S. provisional application Ser. No. 62/488,340 to 2017, month 4, and U.S. provisional application Ser. No. 62/563,847 to 2017, month 9, month 27, claims 35U.S. 119 (e) (1), which are hereby incorporated by reference.

Technical Field

The following description relates to the processing of integrated circuits ("ICs"). More particularly, the following description relates to apparatus and techniques for processing IC dies.

Background

The need for more compact physical configurations of microelectronic components such as integrated chips and dies has become increasingly stronger with the rapid development of portable electronic devices, expansion of the internet of things, nanoscale integration, sub-wavelength optical integration, and the like. By way of example only, devices are commonly referred to as "smartphones" that integrate the functionality of cellular telephones having a high-power data processor, memory and auxiliary devices such as global positioning system receivers, electronic cameras and local area network connections, as well as high-resolution displays and associated image processing chips. Such devices may provide functions such as: complete internet connectivity, including entertainment, navigation, electronic banking, sensors, memory, microprocessors, health electronics, automation electronics, etc., of full resolution video, are all implemented in pocket devices. Complex portable devices require numerous chips and dies to be packaged into a small space.

Microelectronic assemblies often contain thin flat sheets of semiconductor material such as silicon arsenide or gallium arsenide or other semiconductor materials. The chips and dies are typically provided as individual pre-packaged units. In some unit designs, the die is mounted to a substrate or chip carrier, which is then mounted on a circuit panel, such as a printed circuit board (printed circuit board; PCB). The die may be provided in a package that facilitates handling of the die during fabrication and during mounting of the die on an external substrate. For example, many dies are provided in packages suitable for surface mount. Numerous packages of this general type are proposed for various applications. Most commonly, such packages include dielectric components, commonly referred to as "chip carriers" having terminals formed as plated or etched metal structures on a dielectric. Terminals are typically connected to contacts (e.g., bond pads or metal posts) of the die by conductive features such as thin traces extending along the die carrier and by fine leads or wires extending between the contacts and terminals or traces of the die. In a surface mount operation, the package may be placed onto a circuit board such that each terminal on the package is aligned with a corresponding contact pad on the circuit board. Solder or other bonding material is typically disposed between the terminals and the contact pads. The package may be permanently bonded in place by heating the assembly to melt or "reflow" the solder or otherwise activate the bonding material.

Many packages include solder solids in the form of solder balls, typically between about 0.025mm and about 0.8mm (1 mil and 30 mil) in diameter, attached to terminals of the package. Packages having an array of solder balls protruding from their bottom surface (e.g., the surface opposite the front face of the die) are commonly referred to as ball grid arrays or "BGA" packages. Other packages known as land grid arrays or "LGA" packages are secured to the substrate by means of thinner layers or pads formed from solder. This type of packaging can be very compact. Some packages, commonly referred to as "chip scale packages," occupy an area of the circuit board that is equal to or only slightly larger than the area of the devices incorporated in the package. This ratio is advantageous because it reduces the overall size of the assembly and permits the use of short interconnects between the various devices on the substrate, which in turn limits signal propagation time between the devices and thus facilitates operation of the assembly at high speeds.

The semiconductor die may also be arranged in a "stacked" configuration, where, for example, one die is disposed on a carrier and another die is mounted on top of the first die. Such configurations may allow multiple different dies to be mounted within a single footprint on a circuit board, and may further facilitate high speed operation by providing short interconnects between the dies. Typically, this interconnect distance may be only slightly greater than the thickness of the die itself. For interconnects to be achieved within a stack of die packages, interconnect structures for mechanical and electrical connections may be provided on both sides (e.g., faces) of each die package (except for the highest package). For example, it is achieved by providing contact pads or bonding pads on both sides of the substrate on which the die is mounted, the pads being connected by conductive vias or the like via the substrate. Examples of stacked chip configurations and interconnect structures are provided in U.S. patent application publication No. 2010/023269, the disclosure of which is incorporated herein by reference.

The die or wafer may also be stacked in other three-dimensional configurations as part of various microelectronic packaging schemes. This may include stacking layers of one or more dies or wafers on a larger base die or wafer, stacking multiple dies or wafers in a vertical or horizontal configuration, or stacking similar or different substrates, wherein one or more of the substrates may contain electrical or non-electrical components, optical or mechanical components, and/or various combinations of such components. The dies or wafers can be bonded in a stacked configuration using a variety of bonding techniques, including direct dielectric bonding, adhesive-free techniques (such as) Or hybrid bonding techniques (such as/>) Both are available from Infan Sasbond technologies Inc. (Invensas Bonding technologies, inc.), previously Ziptronix, xperi (see, e.g., U.S. Pat. Nos. 6,864,585 and 7,485,968, which are incorporated herein in their entirety). When bonding stacked dies using direct bonding techniques, it is often desirable that the surface of the die to be bonded be extremely flat and smooth. For example, typically, the surface topology of the surfaces should have minimal variation so that the surfaces can mate tightly to form a continuous bond. For example, it is generally preferred that the roughness of the bonding surface varies less than 3nm and preferably less than 1.0nm.

Some stacked die configurations are sensitive to the presence of particles or contamination on one or both surfaces of the stacked die. For example, particles remaining from the processing step or contamination from die processing or tools may create poorly bonded regions between stacked dies or the like. Additional handling steps during die processing can further exacerbate the problem, leaving undesirable residues.

Drawings

The detailed description is set forth with reference to the drawings. In the figures, the leftmost digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different figures indicates similar or identical items.

For this discussion, the devices and systems illustrated in the figures are shown as having a large number of components. As described herein, various implementations of devices and/or systems may include fewer components and remain within the scope of the invention. Alternatively, other implementations of the device and/or system may include additional components or various combinations of the described components and remain within the scope of the invention.

FIG. 1 is a text flow diagram illustrating an example grain process column using a rotating plate.

FIG. 2 is a text flow diagram illustrating an example grain progression column performed on a dicing tape or device handling film or surface according to a specific example.

FIG. 3 is a graphical flow diagram of an example grain process column of FIG. 2 according to an embodiment.

Fig. 4A-4E illustrate example steps for transferring dice from a dicing sheet to a wafer or surface according to an example embodiment.

Fig. 5A-5C illustrate an example dicing sheet with die removed according to one embodiment.

Fig. 6 is a text flow diagram illustrating an example grain process column performed on a dicing tape or device handling film or surface according to a second embodiment.

Fig. 7 is a text flow diagram illustrating an example grain process column performed on a dicing tape or device handling film or surface according to a third embodiment.

FIG. 8 is a graphical flow diagram of an example grain process column of FIG. 7 according to an embodiment.

Fig. 9A and 9B illustrate an example die cleaning system according to various embodiments.

Fig. 10A and 10B illustrate an example die cleaning system according to other embodiments.

Detailed Description

Various embodiments of techniques and systems for processing Integrated Circuits (ICs) are disclosed. The die prepared for intimate surface bonding (to other die, to the substrate, to another surface, etc.) may be treated with minimal handling to prevent contamination of the surface or edges of the die.

According to various embodiments, the techniques include treating the die while the die is on a dicing sheet or other device treatment film or surface. For example, when the die is on a dicing sheet, the die may be cleaned, ashed, and activated (thereby removing several processing steps and opportunities for contamination during processing). For example, the process may prepare dies to be bonded in a stacked configuration. After processing, the die may be picked directly from the dicing sheet and placed on a prepared die receiving surface (another die, substrate, etc.) for bonding to the surface.

In various embodiments, using the disclosed techniques may reduce die manufacturing and processing costs and may reduce the complexity of manufacturing electronic packages including dies. To be used"Direct bond interconnect/>)"Technically stacked and bonded dies may be particularly beneficial, which may be susceptible to particulates and contaminants. Whether or not the fabrication process involves the use of low temperature covalent bonds between two corresponding semiconductor and/or insulating layers to bond the two surfaces (the process is referred to as) Or whether the fabrication process also includes forming interconnections and bonding techniques (the process is referred to as) A high degree of flatness and cleanliness across the bonding surface is typically required.

The disclosed techniques may also be beneficial for other applications where, for example, the bonding region of the device may comprise a flowable bulk material, such as any form of solderable material for bonding. Minimizing or removing particles or stains between the bonded surfaces can significantly improve yield and reliability. In one implementation, large batches of dice may be processed at a time where a larger die or wafer carrier is used, such as a larger dicing sheet, where multiple dice or wafer carriers are used, and so forth.

In some embodiments, several process steps may be removed, thereby reducing manufacturing complexity and cost, while improving overall cleanliness of the die (e.g., reducing the occurrence of particles, contaminants, residues, etc.). The reduced die handling also minimizes particle generation.

A flow chart is shown at fig. 1 illustrating an example die or device process row 100 for holding a die using a rotating plate during processing. At blocks 1 to 4, the process begins by preparing a substrate, such as a silicon wafer, by: applying a protective coating to one or both sides of the wafer; singulating the wafer into dice (i.e., a first set of dice) on a dicing sheet or the like; exposing the die and cut pieces to Ultraviolet (UV) radiation and stretching the cut pieces; and transferring the die to the rotating plate with the die facing upward. At blocks 5 to 9, the procedure comprises the steps of: cleaning the organic layer from the die; plasma ashing the top surface of the die to remove any remaining organic residues on the die; and further cleaning the die with deionized water (DI), such as plasma activating the top surface of the die and re-cleaning the die.

At block 10, the die is transferred to the flipper to position the die to face downward (i.e., the active surface (e.g., first surface) of the die faces downward or toward the flipper). At block 11, the die are transferred to a pick-and-place station. In this configuration, the die is picked from its back surface (e.g., the show or active surface opposite the face, front surface, or first surface) and placed face down on the prepared receiving surface for bonding. To pick up the die, a pick-up vacuum tool, for example, contacts the back or second surface of the die opposite the bonded surface.

The receiving surface may comprise a prepared surface such as a substrate, another die, a dielectric surface, a polymeric layer, a conductive layer, a surface of an interposer, another package, a surface of a flat panel, or even a surface of another circuit or silicon wafer or non-silicon wafer. The material of the die may be similar to or different from the material of the receiving substrate. Further, the surface of the die may be different from the surface of the accommodating substrate.

At block 13, the die placed on the substrate is heat treated to enhance bonding between the surface of the die and the receiving surface of the substrate. In some embodiments, additional dies may be attached to the back (e.g., second) or available surface of the bonded dies. The back surface may additionally have active devices therein.

At blocks 14-18, the receiving surfaces of the bonded dies, such as the substrate, and the exposed back surface are cleaned, plasma ashed, re-cleaned, plasma activated, and re-cleaned. At block 19, a second set of dies (with the top surface previously prepared as described at blocks 1-11) may be attached to the first set of dies (which form a stacked die configuration). In an example, a prepared front surface (e.g., a first surface) of the second die is attached to an exposed back surface (e.g., a second surface) of the first die. At block 20, the assembly with the first and second dies is heat treated to enhance bonding of the stack. For additional dies to be added to the stacked die configuration (e.g., third or more dies), the process loops back to block 14 and continues until the desired number of dies has been added to each stack.

In various examples, a manufacturing process as described may use at least or about 13+7 (n-1); n >0 steps (where n = the desired number of dies in the stack).

In some cases, the die may leave some contaminants or particles on one or more surfaces of the die, although many cleaning steps will be included in the procedure. For example, the top or front surface of the die may be cleaned from contaminants, while the bottom or back surface of the die may be left with particles or contaminants. In addition, handling the grains during multiple processing steps may add particles or contaminants to the grains. For example, tools used during handling may deliver contaminants to the die. The location of the particle or defect on the die may determine whether the particle or defect may be potentially problematic for a stacked configuration. For example, some particles and defects may cause poor bonding between stacked dies, and so on. In another example, the device flipping step may be a source of contaminants or defects because the cleaned top surface of the device is in contact with another surface after the flipping operation.

Example implementation

Fig. 2 is a flow chart illustrating an example die progress column 200 in which dies are processed on a carrier such as a dicing tape ("dicing sheet") or other processing sheet, according to a specific example. FIG. 3 shows a graphical flow diagram representation of a process 200 implemented according to an example. Procedure 200 is discussed with reference to fig. 2 and 3, however, unless otherwise specified, reference to "blocks" in this discussion refers to the numbered blocks at fig. 2.

At block 1, the wafer 302 is processed, including adding one or more protective layers or coatings 304 to one or both surfaces of the wafer 302 (block 2). The protective layer 304 may include a photoresist or similar protective agent. The wafer 302 is transferred to the dicing sheet 306 and temporarily secured to the dicing sheet 306 with an adhesive 308. At block 3, wafer 302 is singulated into dice 310 while on dicing sheet 306.

At block 4, when die 310 is attached to dicing sheet 306, the clean die 310 includes edges of die 310 to remove particles. Cleaning may be performed mechanically and/or chemically. For example, the die 310 may be bombarded with fine CO2 particles and/or exposed to a brush cleaning step, which may be ultrasonic or ultra-high frequency sonic enhancement. The brush 312 (as shown in fig. 3) may rotate or otherwise move in any direction relative to the surface of the die 310. The die 310 may additionally or alternatively be exposed to wet etching, water jets, and the like. At block 5, the dicing sheet 306 may be stretched slightly to create spaces between the dies 310, accommodating cleaning of the edges of the dies 310. The die 310 on the dicing sheet 306 may be exposed to Ultraviolet (UV) radiation to decompose the resist 304 and/or adhesive 308 layers. If it is desired to prepare the die 310 for removal from the dicing sheet 306, the dicing sheet 306 may be further stretched.

At block 6, when the die 310 is on the dicing sheet 306, the remaining residue of the resist layer 304 is cleaned from the exposed surface (e.g., first surface) of the die 310. Cleaning solutions may be used, as well as other chemical and/or mechanical cleaning techniques such as those described herein. In addition, while the die 310 remains on the dicing sheet 306, a first (e.g., exposed) surface of the die 310 is plasma ashed (e.g., oxygen ashed) to remove any undesirable organic residues.

At block 7, the first surface of die 310 is again cleaned using wet cleaning techniques (e.g., deionized water, cleaning solution, etc.), which may include ultra-high frequency sonic washing, mechanical brush scrubbing or agitation, or other suitable cleaning techniques. For example, in some cases, additional cleaning may be performed after the ashing step by wet cleaning and/or by CO2 particle flow, or by a rotating brush, water jet, or ultra high frequency sonic assisted wet cleaning technique, or a combination thereof.

At block 8, a first surface of die 310 is plasma activated (e.g., nitrogen plasma, etc.) to create or enhance a bond for stacking die 310. At block 9, the activated die 310 is cleaned using a wet cleaning technique (e.g., deionized water, hot deionized water, steam, or a high pH cleaning solution, etc.), which may be enhanced with ultra-high frequency sonic waves or a combination of the cleaning techniques described above, or the like.

At block 10, dice 310 (e.g., known good dice) 310 are transferred from dicing sheet 306 to receiving surface 314 (prepared dice, substrate, etc.) for bonding to receiving surface 314. In some cases, various cleaning and surface activation procedures discussed above may be performed on the exposed surfaces of the die 310 and/or the receiving surface 314.

In various embodiments, the die 310 is transferred from the dicing sheet 306 using a "stamping" technique (as illustrated in fig. 4 and 5). Stamping techniques allow the die 310 to be transported (e.g., known to be good die) without contaminating the surface or edges of the die 310. Also, the stamping technique allows the die 310 (e.g., known good die) to be bonded to a "down-facing" bonding surface 314 using DBI hybrid bonding techniques, solder bumps, or the like, the bonding surface 314 being along with a first surface of the die 310 that faces the receiving surface 314.

In one example, as shown in fig. 4 (a), 5 (a), and 5 (B), the stretched cut piece 306 is held by a clamp ring 402 or frame or the like. The die 310 on the dicing sheet 306 are separated by gaps 404 (about 2um to 200um wide) that may be at least partially due to stretching. As shown at fig. 4 (B) and 4 (C), the dicing sheet 306 may be perforated along the gaps 404 between the dies 310 using one or more of a variety of tools 406, such as a dicing blade, a hot knife, an optical knife (laser ablation), and the like. In one embodiment, the perforations allow the dies 310 to be punched individually (e.g., known to be good dies) from the dicing sheet 306, leaving other dies 310 in place on the dicing sheet 306. A vacuum tool 408 or the like (i.e., a "pick-up head") may be used, for example, to punch individual dies 310 from the perforated dicing sheet 306 (as shown in fig. 4 (B)), from the back of the dicing sheet 306. The vacuum tool 408 is capable of transporting the die 310 (e.g., known to be a good die) from a surface of the dicing tape 306 opposite the die 310, with a portion of the dicing tape 306 (or processing piece) in place between the tool 408 and the die 310. Thus, the die 310 (e.g., known good die) reaches the bonding surface 314, and the vacuum tool 408 does not contaminate the surface or edge of the die 310 to be bonded. The portion of tape 306 that remains attached to the back surface of die 310 (e.g., known good die) in turn protects die 310 from contamination by contact with tool 408.

Fig. 4 (D) shows a cross-sectional view of the dicing sheet 306 with the die 310 removed. Holes 410 are present in the dicing sheet 306 because a portion of the dicing sheet 306 and the die 310 are removed. Fig. 4 (E), which is further shown at fig. 5 (a) through 5 (C), shows a number of dies 310 placed on a substrate 314 for bonding.

In another embodiment, the device pick-up head 408 (e.g., a vacuum tool) picks up the die 310 (e.g., a known good die) from the backside of the die 310 (e.g., a known good die) by the dicing blade 306 while the corresponding tool uses a laser source (or the like) to ablate the dicing blade 306 around the perimeter of the die 310. In some applications, during pick-up of die 310 from the backside by vacuum tool 408, the heated knife 406 edge may be used to melt dicing sheet 306 around die 310 to completely separate die 310 from dicing sheet 306. An inert gas may be applied to the surface of the die 310 to prevent fumes or other contaminants from the device separation step from contaminating the cleaned surface of the die 310. In other embodiments, a vacuum may be used in place of the inert gas, while in other embodiments, both the inert gas and the vacuum are used to protect the surface of the die 310 during the device separation procedure.

In various implementations, the cleaned exposed surface of die 310 is not touched by any other surface or material other than the surface of receiving substrate 314. This is in contrast to some prior art techniques, where the cleaned surface of die 310 (e.g., a known good die) typically contacts some portion of the receiving flap. In other common techniques, the vacuum pickup device 408 may pick up the cleaned die 310 (e.g., known to be good die) by touching a portion of the surface of the cleaned die 310, for example, which may cause contamination of the touched surface.

Referring back to fig. 2 and 3, at block 11, the wafer or substrate 314 with the latest stacked die 310 is heat treated (e.g., to 50 to 150°f) to enhance bonding of the die 310 to the substrate 314. At block 12, the currently exposed surface of die 310 ("back surface" or "second surface") and substrate 314 are prepared by chemical and/or mechanical cleaning techniques (e.g., surfactants, non-PVA rotating brushes, ultra-high frequency sonic waves, etc.). This removes any remaining adhesive 308, dicing sheet 306, protective layer 304, or other residue from the back surface of die 310. At block 13, the back surface of die 310 is plasma activated in preparation for further bonding.

At block 14, additional prepared dies 316 are separated by the techniques disclosed herein and disposed with the first surface "face down" (e.g., active side down, prepared side down, etc.) on a prepared back (e.g., second) surface of die 310 previously disposed, for example, on substrate 314. The newly added die 316 is heat treated (e.g., block 11) to strengthen the bond to the die 310. For additional dies 316 (e.g., third or more dies) to be added to the stacked die configuration, the process loops back to block 12 and continues until the desired number of dies 310, 316 has been added to each stack.

In various examples, a manufacturing process as described may use approximately 11+2 (n-1); n >0 steps (where n = the desired number of dies 310, 316 in the stack). When compared to the procedure described with respect to fig. 1: (13+7 (n-1)) this represents a significant reduction in manufacturing steps. The reduced process steps not only reduce the manufacturing cost and complexity, but also reduce the chance of contaminating the die 310, resulting in better quality and higher yield at lower cost. The reduced processing steps translate into cost savings per die 310 and the removal of the rotating plate (or similar processing element) translates into additional manufacturing cost savings. For example, about 50 to 100 dies 310 may be processed at a time using a rotating plate, and about 200 to 10,000 dies 310 or more may be processed at a time using a dicing sheet 306 procedure as described.

A second example embodiment 600 for processing the die 310 on the dicing sheet 306 is shown at fig. 6. Example embodiment 600 illustrates that some of the process steps may be performed in a different order, including a reduced process step. For example, as previously described, at blocks 1-3, wafer 302 is treated with protective coating 304, singulated into dies 310 on dicing sheet 306, and cleaned on dicing sheet 306. Optionally, the dicing sheet 306 may be stretched to accommodate cleaning between the dies 310, and/or the dies 310 may be exposed to UV light to decompose the resist 304 and the adhesive 308. At block 4, while the die 310 remains on the dicing sheet 306, the first surface of the die 310 is plasma ashed (e.g., oxygen ashed) to remove any undesirable organic residues (or other contaminants) from the first surface.

At block 5, the ashed surfaces of the dies 310 are cleaned using wet cleaning techniques (e.g., deionized water, cleaning solution, etc.) as described above, which may include ultra-high frequency sonic waves or the like. At block 6, a first surface of die 310 is plasma activated (e.g., nitrogen plasma, etc.) to create or enhance a bond for stacking die 310. At block 7, the activated die 310 is exposed to UV light and the dicing sheet 306 is partially stretched. At block 8, activated die 310 is cleaned using a wet cleaning technique (e.g., deionized water, hot deionized water, steam, or a high pH cleaning solution, etc.), which may be enhanced with ultra-high frequency sonic waves or a combination of the cleaning techniques described above, or the like.

At block 9, die 310 is transferred from dicing sheet 306 to bonding surface 314 and bonded to the "down" facing first surface using, for example, DBI hybrid bonding techniques, solder bumps, or the like. In various embodiments, the die 310 is transferred from the dicing sheet 306 using the "stamping" technique described above (including perforating the dicing sheet 306 and transferring the die 310 using the vacuum tool 408 or the like, while a portion of the dicing sheet 306 remains on the die 310 to protect the die 310 from contamination by the vacuum tool 408). At block 10, die 310 and substrate 314 are heat treated (e.g., to 50 to 150F.) to enhance bonding of die 310 to substrate 314. At block 11, the exposed surface ("back surface" or "second surface") of die 310 and substrate 314 are cleaned using chemical and/or mechanical cleaning techniques (e.g., surfactants, non-PVA rotating brushes 312, ultra-high frequency sonic waves, etc.). This removes any remaining adhesive 308 or other residue from the back surface of die 310. At block 12, the back surface of die 310 is plasma activated in preparation for further bonding.

At block 13, additional dies 316 may be stamped from the perforated cut sheet 306 (as described above) and placed "face down" on the back (e.g., exposed) surface of the dies 310 previously placed on, for example, the substrate 314. The newly added die 316 is heat treated (e.g., block 10) to enhance bonding. For additional dies 310, 316 (e.g., third or more dies) to be added to the stacked die configuration, the process loops back to block 11 and continues until the desired number of dies 310, 316 has been added to each stack.

In various examples, a manufacturing process as described may use about 10+2 (n-1); n >0 steps are completed (where n = the desired number of dies 310, 316 in the stack), resulting in further reductions in steps, complexity, and cost.

Fig. 7 is a flow chart illustrating another example die 310 process column 700 performed on dicing tape 306 according to a third embodiment. FIG. 8 is a graphical representation of an example grain process column 700 of FIG. 7 according to an example implementation. In the example embodiments of fig. 7 and 8, the plasma ashing step (i.e., block 4 of fig. 6) is removed, thereby reducing the process steps.

As previously described, at blocks 1-3, wafer 302 is treated with protective coating 304, singulated into dice 310 on dicing sheet 306, and cleaned on dicing sheet 306. Optionally, the dicing sheet 306 may be stretched to accommodate cleaning between the dies 310, and/or the dies 310 may be exposed to UV light to decompose the resist 304 and the adhesive 308. At block 4, a first surface of die 310 is plasma activated (e.g., nitrogen plasma, etc.) to create or enhance a bond for stacking die 310. At block 5, activated die 310 is cleaned using wet cleaning techniques (e.g., deionized water, high ph cleaning solutions, etc.), which may include ultra-high frequency sonic washing, agitation, or other suitable cleaning techniques. At block 6, the activated die 310 is exposed to UV light and the dicing sheet 306 is partially stretched.

At block 7, die 310 is transferred from dicing sheet 306 to bonding surface 314 and bonded to the "down" facing first surface using DBI hybrid bonding techniques, solder bumps, or the like. In various embodiments, the die 310 is transferred from the dicing sheet 306 using the "stamping" technique described above (including perforating the dicing sheet 306 and transferring the die 310 using the vacuum tool 408 or the like, while a portion of the dicing sheet 306 remains on the die 310 to protect the die 310 from contamination by the vacuum tool 408). At block 8, die 310 and substrate 314 are heat treated (e.g., to 50 to 150F.) to enhance bonding of die 310 to substrate 314. At block 9, the exposed surface ("back surface" or "second surface") of die 310 and substrate 314 are cleaned using chemical and/or mechanical cleaning techniques (e.g., surfactant, methanol, non-PVA rotating brush 312, ultra-high frequency sonic waves, etc.). This removes any remaining adhesive 308 or other residue from the back surface of die 310. At block 10, the back surface of die 310 is plasma activated in preparation for further bonding.

At block 11, additional dies 316 may be stamped from the perforated dicing sheet 306 and placed "face down" (e.g., prepared side down) on the back surface (e.g., exposed surface) of the die 310 previously placed on, for example, the substrate 314. The newly added die 316 is heat treated (e.g., block 8) to enhance bonding. For additional dies 310, 316 to be added to the stacked die configuration (e.g., third or more dies 310, 316), the process loops back to block 9 and continues until the desired number of dies 310, 316 has been added to each stack.

In various examples, a manufacturing process as described may use approximately 8+2 (n-1); n >0 steps are completed (where n = the desired number of dies 310, 316 in the stack), resulting in further reductions in steps, complexity, and cost. After the equipment stacking step, stacked die 310 and receiving surface 314 may be further processed to a subsequent higher temperature. The treatment temperature may be in the range of 80 to 370 ℃ for a period of time ranging from 15 minutes up to 5 hours or more. The lower the temperature, the longer the treatment time.

In one embodiment of process 700, the wafer 302 to be processed/diced may include interconnects, such as solder bumps or other reflowable bonding material (not shown) or the like, on the exposed or first surface. In this particular example, the reflowable interconnect joint structure is often disposed face up on the dicing sheet 306 or the handling sheet in such a way that the reflowable features do not directly contact the adhesive layer 308 of the dicing sheet 306. The wafer 302 may be processed with a protective coating 304 covering the reflowable interconnect structure. Wafer 302 is singulated into dies 310 while on dicing sheet 306 and cleaned while on dicing sheet 306 as previously described with respect to blocks 1-3 above. Optionally, the dicing sheet 306 may be stretched to accommodate cleaning between the die 310 and the edges of the die 310, and/or the die 310 may be exposed to UV light to decompose the resist 304 and the adhesive 308.

At block 4, a first surface (e.g., an exposed surface) of die 310 may be cleaned using a plasma cleaning process (e.g., oxygen ashing, etc.). At block 5, the dice 310 on the dicing sheet 306 may be further cleaned using wet cleaning techniques (e.g., deionized water, high ph cleaning solution, etc.) as described above, which may optionally include ultra-high frequency sonic waves, agitation, or the like. At block 6, the cleaned die 310 and the dicing sheet 306 may be exposed to UV light and the dicing sheet 306 may be further stretched.

At block 7, the dice 310 are transferred from the dicing sheet 306 to the receiving surface 314 and combined with a "downward facing" first surface (e.g., a downward prepared surface) using the techniques described herein. For example, in some embodiments, the receiving substrate 314 may include a polymeric layer, a non-filled primer, or portions of an adhesive sheet. In various embodiments, the dice 310 are transferred from the dicing sheet 306 using the "stamping" techniques described above (including perforating the dicing sheet 306 and transferring the dice 310 using the vacuum tool 408 or the like, while a portion of the dicing sheet 306 remains on each of the dice 310 to protect the dice 310 from contamination by the vacuum tool 408).

At block 8, the die 310 and the substrate 314 may be heat treated to electrically couple the die 310 to the receiving substrate 314. In some applications, an underfill material may be formed around bonded device 310 to further mechanically couple device 310 to the substrate 314 receiving surface. At block 9, the exposed surfaces of the transferred die 310 and the substrate 314 are cleaned using chemical and/or mechanical cleaning techniques (e.g., surfactant, methanol, non-PVA rotating brush 312, ultra-high frequency sonic waves, etc.). This removes any remaining adhesive 308 or other residue from the back surface of die 310. At block 10, the exposed surfaces of the transferred die 310 are plasma activated in preparation for further bonding. In some applications, bonded device 310 may be cleaned prior to the heat treatment used to electrically couple die 310 to receiving substrate 314.

As discussed above, at various processing steps or stages, the dies 310, 316 and/or the substrate 314 are cleaned using chemical and/or mechanical cleaning techniques (e.g., surfactants, methanol, non-PVA rotating brushes 312, ultra high frequency sonic waves, etc.). Fig. 9A and 9B illustrate an example die cleaning system that may be used for this purpose, according to various embodiments. The cleaning process and system are described with reference to the receiving surfaces of the die 310 or substrate 314, but it is understood that the process and system are applicable to the dies 310, 316 and substrate 314 as well as dielectric surfaces, polymeric layers, conductive layers, interposers, packages, panels, circuits, silicon or non-silicon wafers, and the like.

Referring to fig. 9A, in an example cleaning sequence, an object to be cleaned (e.g., a die 310 or carrier, etc.) is loaded onto a processing apparatus 902, such as a turntable or rotating plate as shown, for cleaning and/or other processing. The cleaning procedure includes applying near-ultra-high frequency sonic energy to the cleaning fluid via an ultra-high frequency sonic transducer 904 as the die 310 may rotate on the turntable 902. The transducer 904 may be scanned back and forth as the die 310 rotates to improve the uniform application of sonic energy to the die 310. The sonic energy helps loosen particles that might otherwise be difficult to remove from the surface of the die 310.

Referring to fig. 9B, the transducer 904 is then removed and the surface of the die 310 may be brushed clean using the brush 906. For example, the brush 906 may be scanned back and forth as the turntable 902 rotates. If this cleaning procedure is not successful in removing enough particles, the procedure may be repeated as necessary. When the cleaning process is completed, the die 310 is rinsed and dried. However, in some cases, this may require multiple cycles and may still be insufficient to clean all residues from die 310.

Referring to fig. 10A and 10B, the techniques and systems provide improved cleaning of die/wafer/substrate surfaces in a single process. Fig. 10A and 10B illustrate an example die 310 cleaning system 1000 according to various embodiments. An integrated ultra-high frequency sonic brush system 1000 is disclosed that includes an ultra-high frequency sonic transducer 1002 and one or more brush heads 1004.

In a first specific example, as shown at fig. 10A, an integrated ultra-high frequency sonic brush system 1000 is placed in proximity to a die 310 on a turntable 902 (or other processing surface). The integrated uhf sonic brush system 1000 is positioned such that the transducer 1002 is at an optimal distance from the die 310 surface and such that the brush 1004 has a desired contact pressure on the die 310 surface. For example, a cleaning fluid is applied to the surface of the die 310. The brush 1004 simultaneously brushes away particles from the surface of the die 310 as the transducer 1002 applies sonic energy to the surface of the die 310 via the cleaning fluid. In various implementations, the die 310 rotates on a turntable 902 and/or the integrated ultra-high frequency sonic brush system 1000 is scanned back and forth for uniform cleaning.

In implementations, for example, the fluid level sensor 1006 assists in controlling the amount of cleaning fluid applied to the surface of the die 310 if a signal is sent to the cleaning fluid reservoir. In implementations, a fluid level sensor 1006 is positioned above the die 310 and is configured to detect a level of fluid above the die 310. The fluid level sensor 1006 is configured to send at least a first signal to the fluid source when the level of the fluid is less than a first predetermined amount and a second signal to the fluid source when the level of the fluid is greater than a second predetermined amount. The combination of ultra high frequency sonic and brushing in a single system and procedure allows for more thorough cleaning in a single procedure, thereby eliminating repeated cleaning iterations.

In a second specific example, as shown at fig. 10B, one or more brushes 1004 may be rotated via a rotation unit 1008 as the surface of the die 310 is brushed. For example, the brush 1004 may be rotated (e.g., the rotation unit 1008 may rotate the brush 1004) using hydraulics delivered via a catheter 1010, cable, or the like, or any other suitable means (pneumatic, electric, mechanical, etc.). Additional rotation of the brush 1004 may assist in removing refractory particles from the surface of the die 310 in a single cleaning system and procedure.

The techniques and systems may provide cleaner bonding surfaces with fewer process steps to prepare dies 310 to be bonded in a stacked configuration. After processing and cleaning, the die 310 may be picked up and placed on a die receiving surface 314 (another die, substrate, etc.) for bonding to the receiving surface 314, as described above. To be used"Direct bond interconnect/>)The "technically stacked and bonded die 310 may be particularly beneficial, which may be susceptible to particulates and contaminants. The disclosed techniques may also be beneficial for other applications where, for example, the bonding region of die 310 may comprise a flowable bulk material, such as any form of solderable material for bonding. Minimizing or removing particles or stains between the bonded surfaces can significantly improve yield and reliability. Additional benefits include improved efficiency of cleaning processes and cleaning equipment, simpler process steps and processing equipment, significant reductions in cleaning cycle time, and the like.

Examples of cleaning cycles in which the disclosed techniques and systems may be employed include: cleaning the die 310 after the CMP process, after etching, etc.; cleaning the organic (or inorganic) fabrication and processing layers from the die 310; cleaning the dies 310 with deionized water (DI), alkaline or acidic solutions or weakly alkaline or weakly acidic formulations, solvents, or various combinations thereof after plasma ashing the surfaces of the dies 310; the die 310 is re-cleaned after plasma activating the surface of the die 310, and so on. For example, in various embodiments, the ashing step may be omitted and the die 310 may be cleaned in the apparatus described in fig. 10A and 10B. In one embodiment, for example, the protective layer 304 may be cleaned using the apparatus described in fig. 10A and 10B using applied sonic energy and mechanical action of the brush 1004, thereby removing the protective layer 304 using a suitable solvent. To prevent cross-contamination of tools and devices, in a subsequent step, the cleaned die 310 may be transferred to another cleaning station of the type described with reference to fig. 10A and 10B for additional cleaning, e.g., to remove an ashing step, or after activation of the die 310.

The singulated die 310 may be processed on a carrier 306 as described in various previous paragraphs. In some embodiments, the known good die 310 is removed from the carrier 306, wherein at least a portion of the carrier 306 is attached to a second surface of the known good die 310. The first known good die 310 is attached to the prepared surface of the substrate 314 at a first surface of the first known good die 310. Similarly, the second surface of the first known good die 310 may be cleaned (including cleaning away portions of the carrier 306) and prepared for bonding to another known good die 316. In practice, the backside (e.g., the second side) of either of the bonded dies 310, 316 may be prepared, and additional dies 310, 316 may be bonded thereto. Any additional dies 310, 316 may be bonded to the previously bonded dies 310, 316 as desired. In various embodiments, the stacked bonded die (310, 316, etc.) may range from 1 to 200 dies 310, 316, and preferably between 1 to 100 dies 310, 316 and still preferably between 1 to 20 known good dies 310, 316.

The described techniques may be directed to/>The devices and the like fabricated result in better device and package reliability, higher performance, and improved margin of profit. Other advantages of the disclosed technology will also be apparent to those skilled in the art.

Summary

Although implementations of the invention have been described in language specific to structural features and/or methodological acts, it is to be understood that implementations are not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as representative forms of implementing the example devices and techniques.

Each of the technical solutions herein constitutes a separate embodiment and the embodiments of the different technical solutions and/or the different embodiments are combined within the scope of the present invention and will be apparent to one of ordinary skill in the art upon review of the present invention.

Claims

1. A system, comprising:

An ultra-high frequency sonic transducer configured to be disposed a predetermined proximity from a surface to be cleaned, the ultra-high frequency sonic transducer configured to apply sonic energy to the surface to be cleaned; and

One or more brushes coupled to or integral with the transducer, the one or more brushes configured to contact the surface to be cleaned at a predetermined contact pressure and configured to brush the surface to be cleaned when the ultra-high frequency sonic transducer applies the sonic energy to the surface to be cleaned.

2. The system of claim 1, further comprising a rotation unit coupled to one or more of the brushes, the rotation unit configured to rotate the one or more brushes relative to the surface to be cleaned when the ultra-high frequency sonic transducer applies the sonic energy to the surface to be cleaned.

3. The system of claim 2, wherein the rotation unit includes a hydraulic rotation unit configured to rotate the one or more brushes using hydraulic fluid.

4. The system of claim 1, further comprising a rotating turntable configured to receive the surface to be cleaned, the turntable configured to rotate the surface to be cleaned when the ultra-high frequency sonic transducer applies the sonic energy to the surface to be cleaned and the one or more brushes scrub the surface to be cleaned.

5. The system of claim 1, further comprising a transverse conveyor belt configured to move the transducer and the one or more brushes back and forth transversely across the surface to be cleaned as the uhf sonic transducer applies the sonic energy to the surface to be cleaned and the one or more brushes brush against the surface to be cleaned.

6. The system of claim 1, further comprising a cleaning solution disposed over the surface to be cleaned, the transducer configured to apply the sonic energy to the surface to be cleaned via the cleaning solution.

7. The system of claim 1, further comprising a fluid level sensor disposed above the surface to be cleaned and configured to detect a level of fluid above the surface to be cleaned, the fluid level sensor configured to send at least a first signal to a fluid source when the level of the fluid is less than a first predetermined amount and a second signal to the fluid source when the level of the fluid is greater than a second predetermined amount.

8. The system of claim 1, wherein the system is configured to clean one or more surfaces of one or more substrates, wafers, and/or semiconductor dies.

9. The system of claim 1, wherein the one or more brushes are configured to brush one or more edges of one or more components corresponding to the surface to be cleaned.

10. A method, comprising:

loading one or more microelectronic components onto a processing surface;

Positioning an integrated uhf sonic brush system proximate to the microelectronic assembly, the integrated uhf sonic brush system comprising an uhf sonic transducer and one or more brushes coupled to or integral with the uhf sonic transducer;

Applying sonic energy to the one or more microelectronic components via the uhf sonic transducer; and

Simultaneously brushing one or more surfaces of the one or more microelectronic components via the one or more brushes when the ultra-high frequency sonic transducer applies the sonic energy to the one or more microelectronic components.

11. The method of claim 10, further comprising rotating the treatment surface while simultaneously applying the sonic energy via the transducer and brushing the one or more surfaces of the one or more microelectronic components via the one or more brushes.

12. The method of claim 10, further comprising scanning the integrated ultra-high frequency sonic brush system laterally while simultaneously applying the sonic energy via the transducer and brushing the one or more surfaces of the one or more microelectronic components via the one or more brushes.

13. The method of claim 10, further comprising applying a predetermined amount of cleaning fluid to the one or more surfaces of the one or more microelectronic components, and controlling the predetermined amount of cleaning fluid with a fluid level sensor in communication with a fluid source.

14. The method of claim 13, further comprising applying the sonic energy to the one or more microelectronic components via the ultra-high frequency sonic transducer with the cleaning solution.

15. A method of forming a microelectronic assembly, comprising:

Dicing the singulated and cleaned first known good die from the carrier;

the cleaned surface of the first known good die is attached to the surface of the prepared substrate.

16. The method of claim 15, further comprising:

Preparing a second surface of the first known good grains when a first surface of the first known good grains is bonded to the surface of the prepared substrate;

A first surface of a second known good die is attached to the second surface of the first known good die to form a stacked die configuration.

17. The method of claim 16, further comprising thermally treating the stacked die configuration while the stacked die configuration is bonded to the prepared substrate.

18. The method of claim 15, wherein the cleaned surface of the first known-good grains comprises a flowable interconnect material.

19. The method of claim 15, wherein the cleaned surface of the first known-good die comprises a metal pad or a dielectric surface.

20. The method of claim 15, wherein the surface of the prepared substrate comprises a metal pad or a dielectric surface.

21. A method, comprising:

Applying a protective layer to a substrate comprising a wafer to apply the protective layer to a bonding surface of the wafer;

singulating the wafer and the protective layer into a plurality of semiconductor die assemblies;

Removing the protective layer to expose individual bonding surfaces on each of the plurality of semiconductor die components; and

The individual bonding surfaces of one or more semiconductor die components of the plurality of semiconductor die components are prepared for bonding to a surface of another substrate.

22. The method of claim 21, wherein the protective layer is a first protective layer on a first bonding surface of the wafer and the substrate comprises a second protective layer on a second bonding surface of the wafer, the second surface being different from the first surface, and the method further comprising:

and removing the second protective layer.

23. The method of claim 21, wherein preparing the individual bonding surfaces of the one or more of the plurality of semiconductor die components comprises plasma activating the individual bonding surfaces of the one or more of the plurality of semiconductor die components.

24. The method of claim 21, wherein the substrate is a first substrate and the bonding surface is a first bonding surface, the method further comprising:

The individual bonding surface of at least one semiconductor die component of the plurality of semiconductor die components is bonded to a second bonding surface of a second substrate.

25. The method of claim 24, wherein bonding the individual bonding surface of the at least one semiconductor die component of the plurality of semiconductor die components to the second bonding surface of the second substrate comprises:

the individual bonding surface of the at least one of the plurality of semiconductor die components is bonded directly to the second bonding surface of the second substrate without an adhesive or interposer.

26. The method of claim 24, wherein bonding the individual bonding surfaces of the one or more of the plurality of semiconductor die components to the second bonding surface of the second substrate comprises:

The individual bonding surface of the at least one of the plurality of semiconductor die components is hybrid bonded to the second bonding surface of the second substrate.

27. The method of claim 26, further comprising:

Activating the second bonding surface of the second substrate for the hybrid bonding.

28. The method of claim 21, further comprising:

An ultrasonic cleaning process is used to clean the plurality of semiconductor die components.

29. The method of claim 21, further comprising:

Etching edges of individual semiconductor die components of the plurality of semiconductor die components to remove particles from the edges of the individual semiconductor die components of the plurality of semiconductor die components.

30. The method of claim 29, further comprising:

A protective coating is applied to the substantially planar surface of each of the plurality of semiconductor die components prior to the etching to protect the substantially planar surface from the etchant.

31. The method of claim 21, further comprising:

The individual bonding surfaces of a first semiconductor die component of the plurality of semiconductor die components are bonded to the individual bonding surfaces of a second semiconductor die component of the plurality of semiconductor die components.

32. A method, comprising:

singulating the wafer to provide a plurality of semiconductor die assemblies;

Removing the protective layer from the bonding surface of one or more semiconductor die components of the plurality of semiconductor die components;

Preparing the bonding surfaces of the one or more of the plurality of semiconductor die components for bonding to a surface of a substrate; and

The bonding surface of the one or more of the plurality of semiconductor die components is bonded directly to the surface of the substrate.

33. The method of claim 32, wherein preparing the bonding surfaces of the one or more of the plurality of semiconductor die components comprises plasma activating individual ones of the bonding surfaces of the one or more of the plurality of semiconductor die components.

34. A method, comprising:

applying a protective layer or coating to a wafer having a substantially planar surface;

Singulating the wafer to provide a plurality of semiconductor die assemblies;

Removing the protective layer or coating from the bonding surface of one or more semiconductor die components of the plurality of semiconductor die components;

The one or more semiconductor die components of the plurality of semiconductor die components are hybrid bonded to the surface of the substrate.

35. The method of claim 34, wherein preparing the bonding surfaces of the one or more of the plurality of semiconductor die components comprises plasma activating individual ones of the bonding surfaces of the one or more of the plurality of semiconductor die components. .

36. The method of claim 34, further comprising:

37. A method, comprising:

singulating the wafer and the protective layer into a plurality of semiconductor die assemblies; and

The protective layer is removed to expose individual bonding surfaces on one or more of the plurality of semiconductor die components.

38. The method of claim 37, further comprising:

Individual bonding surfaces of the one or more of the plurality of semiconductor die components are cleaned.

39. The method of claim 38, wherein cleaning the individual bonding surfaces of the one or more of the plurality of semiconductor die components comprises mechanically cleaning the individual bonding surfaces of the one or more of the plurality of semiconductor die components.

40. The method of claim 38, wherein cleaning the individual bonding surfaces of the one or more of the plurality of semiconductor die components comprises chemically cleaning the individual bonding surfaces of the one or more of the plurality of semiconductor die components.

41. The method of claim 38, wherein cleaning the individual bonding surfaces of the one or more of the plurality of semiconductor die components comprises wet cleaning the individual bonding surfaces of the one or more of the plurality of semiconductor die components.

42. The method of claim 37, further comprising:

the plasma activates the individual bonding surfaces of the one or more of the plurality of semiconductor die components.

43. The method of claim 37, further comprising:

Stretching a carrier coupled to the substrate to form a gap between the one or more semiconductor die components of the plurality of semiconductor die components secured to the carrier; and

The carrier is perforated along one or more of the gaps.

44. The method of claim 43, wherein perforating the carrier along the one or more of the gaps comprises perforating the carrier along the one or more of the gaps using one or more of a cutting blade, a hot knife, or an optical knife.

45. The method of claim 43, further comprising:

One or more edges of the one or more of the plurality of semiconductor die components are cleaned while the one or more of the plurality of semiconductor die components are secured to the carrier, the edges exposed in the one or more of the gaps.

46. The method of claim 43, wherein the carrier comprises a cut sheet.

47. The method of claim 37, wherein the protective layer is a first protective layer on a first bonding surface of the wafer and the substrate comprises a second protective layer on a second bonding surface of the wafer, the second bonding surface being different from the first bonding surface, and the method further comprising:

The second protective layer is removed after singulating the wafer into the plurality of semiconductor die components.

48. A method, comprising:

Applying a protective layer to a substrate comprising a wafer to apply the protective layer to a bonding surface of the wafer, the substrate being coupled to a carrier;

Stretching the carrier to form gaps between one or more semiconductor die components of the plurality of semiconductor die components secured to the carrier; and

After stretching the carrier, the protective layer is removed to expose individual bonding surfaces of the one or more of the plurality of semiconductor die components.

49. The method of claim 48, further comprising:

50. The method of claim 48, further comprising:

the carrier is perforated along one or more of the gaps.

51. The method of claim 50, wherein perforating the carrier along the one or more of the gaps comprises perforating the carrier along the one or more of the gaps using one or more of a cutting blade, a hot knife, or an optical knife.

52. The method of claim 50, further comprising:

Cleaning the individual bonding surfaces of the one or more of the plurality of semiconductor die components; and

An edge of the one or more of the plurality of semiconductor die components is cleaned, the edge exposed in the gap.

53. The method of claim 52, wherein cleaning the individual bonding surfaces of the one or more of the plurality of semiconductor die components comprises (i) mechanically cleaning the individual bonding surfaces, (ii) chemically cleaning the individual bonding surfaces, or (iii) wet cleaning the individual bonding surfaces.

54. The method of claim 48, wherein the protective layer is a first protective layer on the first bonding surface of the wafer and the substrate comprises a second protective layer on a second bonding surface of the wafer, the second bonding surface being different from the first bonding surface, and the method further comprising:

55. A method of forming a microelectronic assembly, the method comprising:

providing a first known good semiconductor die assembly on a portion of a carrier;

bonding the first surface of the first known good semiconductor die assembly directly to the surface of the prepared substrate; and

The portion of the carrier is removed from the second surface of the first known good semiconductor die assembly.

56. The method of claim 55, wherein the carrier comprises one of (i) a dicing tape and an adhesive or (ii) a dicing sheet and an adhesive.

57. The method of claim 55, wherein the portion of the carrier comprises an adhesive.

58. The method of claim 55, wherein providing the first known-good semiconductor die component on the portion of the carrier comprises:

dicing the carrier around the perimeter of the first known-good semiconductor die assembly; and

The first known-good semiconductor die assembly is removed from the carrier, wherein at least one surface of the portion of the carrier is secured to the second surface of the first known-good semiconductor die assembly.

59. The method of claim 55, wherein the carrier is pre-cut from another substrate.

60. The method of claim 55, further comprising:

The first surface of the first known good semiconductor die component is cleaned prior to bonding the first surface of the first known good semiconductor die component directly to a surface of a prepared substrate.

61. The method of claim 60, wherein cleaning the first surface of the first known-good semiconductor die component comprises:

The protective layer is removed from the first surface of the first known good semiconductor die assembly.

62. The method of claim 55, further comprising:

The first known good semiconductor die assembly and the prepared substrate are heat treated.

63. The method of claim 55, further comprising:

Cleaning the second surface of the first known good semiconductor die component;

plasma activating the second surface of the first known good semiconductor die assembly;

cleaning a first surface of a second known good semiconductor die assembly;

attaching the first surface of the second known good semiconductor die component to the second surface of the first known good semiconductor die component to form a stacked die configuration; and

The stacked die configuration is heat treated.

64. The method of claim 63, wherein attaching the first surface of the second known-good semiconductor die component to the second surface of the first known-good semiconductor die component comprises hybrid bonding the first surface of the second known-good semiconductor die component to the second surface of the first known-good semiconductor die component.

65. The method of claim 55, wherein bonding the first surface of the first known-good semiconductor die component directly to the surface of the prepared substrate comprises hybrid bonding the first surface of the first known-good semiconductor component to the surface of the prepared substrate.

66. A method of forming a microelectronic assembly, the method comprising:

providing a singulated and cleaned first known good semiconductor die assembly on a portion of a carrier; and

The cleaned surface of the singulated and cleaned first known good semiconductor die assembly is bonded to the surface of the prepared substrate.

67. The method of claim 66, wherein combining the clean surface of the singulated and cleaned first known good semiconductor die components with the surface of the prepared substrate comprises:

the cleaned surface of the singulated and cleaned first known good semiconductor die assembly is directly bonded to the surface of the prepared substrate.

68. The method of claim 67, wherein the clean surface of the singulated and cleaned first known good semiconductor die components comprises a flowable conductive interconnect material.

69. The method of claim 67, wherein the clean surface of the singulated and cleaned first known good semiconductor die component comprises a metal pad or a dielectric surface.

70. The method of claim 67, wherein the surface of the prepared substrate comprises a metal pad or a dielectric surface.

71. The method of claim 67, wherein bonding the clean surface of the singulated and cleaned first known good semiconductor die components directly to the surface of the prepared substrate comprises hybrid bonding the clean surface of singulated and cleaned first known good semiconductor die components to the surface of the prepared substrate.

72. The method of claim 66, wherein providing the singulated and cleaned first known good semiconductor die components on the portion of the carrier comprises:

dicing the carrier around the perimeter of the singulated and cleaned first known good semiconductor die assembly; and

Removing the singulated and cleaned first known good semiconductor die assembly from the carrier, wherein at least one surface of the portion of the carrier is secured to another surface of the singulated and cleaned first known good semiconductor die assembly, wherein the other surface is opposite the cleaned surface,

Wherein the method further comprises removing the portion of the carrier from the other surface of the singulated and cleaned first known good semiconductor die assembly.

73. The method of claim 72, wherein the carrier comprises one of (i) a dicing tape and an adhesive or (ii) a dicing sheet and an adhesive.

74. The method of claim 72, wherein the portion of the carrier comprises an adhesive.

75. The method of claim 72, further comprising:

preparing the other surface of the singulated and cleaned first known good semiconductor die component while bonding the cleaned surface of the singulated and cleaned first known good semiconductor die component to the surface of the prepared substrate; and

A first surface of a singulated and cleaned second known good semiconductor die assembly is attached to the other surface of the singulated and cleaned first known good semiconductor die assembly to form a stacked die configuration.

76. The method of claim 75, further comprising thermally treating the stacked die configuration while bonding the stacked die configuration to the prepared substrate.

77. The method of claim 75, wherein attaching the first surface of the singulated and cleaned second known good semiconductor die component to the other surface of the singulated first known good semiconductor die component comprises hybrid bonding the first surface of the singulated second known good semiconductor die component to the other surface of the singulated first known good semiconductor die component.

78. A method of forming a microelectronic assembly, the method comprising:

Bonding the wafer to a carrier;

Applying a protective layer on the bonding surface of the wafer;

The protective layer is removed to expose individual bonding surfaces of one or more of the plurality of semiconductor die components.

79. The method of claim 78, further comprising:

the individual bonding surfaces of the one or more of the plurality of semiconductor die components are cleaned.

80. The method of claim 79, wherein cleaning the individual bonding surfaces of the one or more of the plurality of semiconductor die components comprises:

the individual bonding surfaces of the one or more of the plurality of semiconductor die components are mechanically cleaned.

81. The method of claim 79, wherein cleaning the individual bonding surfaces of the one or more of the plurality of semiconductor die components comprises:

The individual bonding surfaces of the one or more of the plurality of semiconductor die components are chemically cleaned.

82. The method of claim 79, wherein cleaning the individual bonding surfaces of the one or more of the plurality of semiconductor die components comprises:

The individual bonding surfaces of the one or more of the plurality of semiconductor die components are wet cleaned.

83. The method of claim 78, wherein the carrier comprises a dicing tape.

84. The method of claim 78, wherein the carrier comprises a cut sheet.

85. A method of forming a microelectronic assembly, the method comprising:

bonding a first wafer to a carrier;

Applying a protective layer to a surface of the first wafer;

singulating the first wafer and the protective layer into a plurality of semiconductor die assemblies;

cleaning the protective layer to expose a first bonding surface of one or more semiconductor die components of the plurality of semiconductor die components; and

One or more semiconductor die components are hybrid bonded to the second bonding surface of the prepared substrate.

86. The method of claim 85, wherein the one or more semiconductor die components comprise one or more known good dies.

87. The method of claim 85, wherein hybrid bonding the one or more semiconductor die components to the second bonding surface of the prepared substrate comprises heat treating the one or more semiconductor die components and the prepared substrate.

88. A method of forming a microelectronic assembly, the method comprising:

Providing a protective layer to a first bonding surface of the first wafer;

Singulating the first wafer into a plurality of semiconductor die assemblies such that each die has a portion of the first bonding surface;

cleaning the die, wherein cleaning the die comprises removing the protective layer from the first bonding surface of the die;

preparing a second bonding surface of a second wafer, wherein preparing the second bonding surface comprises plasma activating the second bonding surface;

Mixedly bonding at least one semiconductor die component of the plurality of semiconductor die components to the second bonding surface; and

The at least one semiconductor die assembly of the plurality of semiconductor die assemblies and the second wafer are heat treated.

89. The method of claim 88, wherein each of the at least one of the plurality of semiconductor die components comprises a known good die.

90. A method of forming a microelectronic assembly, the method comprising:

attaching a wafer to a carrier, wherein the wafer comprises a first bonding surface and a second bonding surface, and wherein attaching the wafer to the carrier comprises attaching the second bonding surface to the carrier;

singulating the wafer into a plurality of die components, wherein the plurality of die components comprises known good die, and wherein the known good die comprises a portion of the first bonding surface and a portion of the second bonding surface;

cleaning the plurality of die components while the plurality of die components are attached to the carrier;

Removing the known good grains from the carrier;

bonding the portion of the first bonding surface directly to a surface of a substrate; and

The portion of the second bonding surface is cleaned while the known good die is directly bonded to the substrate.

91. The method of claim 90, further comprising:

A protective layer is formed on the first bonding surface prior to singulating the wafer into the plurality of die assemblies.

92. The method of claim 91, further comprising:

the protective layer is removed from the portion of the first bonding surface prior to bonding the portion of the first bonding surface directly to the surface of the substrate.

93. The method of claim 90, wherein the carrier comprises a dicing tape.

94. The method of claim 90, wherein the portion of the second bonding surface comprises residue after removing the known good die from the carrier, and wherein cleaning the portion of the second bonding surface comprises cleaning the residue from the portion of the second bonding surface.

95. The method of claim 94, wherein the residue comprises one or more of an organic residue or a portion of the carrier.

96. The method of claim 90, wherein cleaning the portion of the second bonding surface comprises cleaning the portion of the second bonding surface using one or more of a CMP process, a brush cleaning process, or an ultra-high frequency sonic cleaning process.

97. The method of claim 90, wherein the known good grains comprise first known good grains, the method further comprising:

After cleaning the portion of the second bonding surface, when bonding the first known good die directly to the substrate, bonding a second known good die directly to the portion of the second bonding surface of the first known good die.

98. The method of claim 97, further comprising:

the portion of the second bonding surface of the first known good die is activated prior to bonding the second known good die directly to the portion of the second bonding surface of the first known good die.

99. The method of claim 97, further comprising:

the first known good die and the substrate are heat treated prior to bonding the second known good die directly to the portion of the second bonding surface of the first known good die.

100. A method of forming a microelectronic assembly, the method comprising:

Singulating the wafer into a plurality of die assemblies, wherein the plurality of die assemblies comprise known good die, and wherein the known good die comprises a portion of a first bonding surface and a portion of the second bonding surface;

Cleaning the plurality of die assemblies on the carrier;

removing the known good die from the carrier after cleaning the plurality of die assemblies;

Directly bonding the portion of the first bonding surface of the known good die to a surface of a substrate;

cleaning the portion of the second bonding surface of the known good die; and

The second die is bonded directly to the portion of the second bonding surface.

101. The method of claim 100, wherein the known good grains comprise first known good grains, and wherein the second grains comprise second known good grains.

102. The method of claim 100, wherein cleaning the portion of the second bonding surface of the known good die comprises cleaning residue or organic residue from the portion of the second bonding surface of the known good die.

103. The method of claim 100, wherein cleaning the portion of the second bonding surface comprises cleaning the portion of the second bonding surface with a CMP process, a brush cleaning process, or an ultra-high frequency sonic cleaning process.

104. The method of claim 100, further comprising:

the portion of the second bonding surface is activated prior to bonding the second die directly to the portion of the second bonding surface.

105. The method of claim 100, wherein the second die comprises a third bonding surface, and wherein bonding a second die directly to the portion of the second bonding surface comprises bonding the third bonding surface directly to the portion of the second bonding surface, the method further comprising:

the third bonding surface is activated prior to directly bonding the third bonding surface to the portion of the second bonding surface.

106. The method of claim 100, further comprising:

After bonding the second die directly to the portion of the second bonding surface, the known good die, the second die, and the substrate are heat treated.

107. A method of forming a microelectronic assembly, the method comprising:

Applying a protective layer to the first bonding surface;

Singulating the wafer into a plurality of die components, wherein the plurality of die components comprises known good die, wherein the known good die comprises a portion of the first bonding surface and a portion of the second bonding surface, and wherein the portion of the first bonding surface comprises a portion of the protective layer;

Cleaning the known good die, wherein cleaning the known good die comprises removing the portion of the protective layer from the portion of the first bonding surface;

removing the known good grains from the carrier;

After bonding the portion of the first bonding surface directly to the surface of the substrate, the portion of the second bonding surface of the known good die is cleaned.

108. The method of claim 107, wherein cleaning the portion of the second bonding surface comprises cleaning the portion of the second bonding surface with one or more of a CMP process, a brush cleaning process, or an ultra-high frequency sonic cleaning process.

109. The method of claim 107, wherein the known good grains comprise first known good grains, the method further comprising: