TW201423873A - Flip-chip bonding method including wafer level picking-up - Google Patents
Flip-chip bonding method including wafer level picking-up Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Abstract
Description
本發明係有關於半導體晶片安裝技術，特別係有關於一種包含晶圓級撿晶之覆晶接合方法。 The present invention relates to semiconductor wafer mounting techniques, and more particularly to a flip chip bonding method including wafer level twinning.
傳統地，由一半導體晶圓切割出複數個晶片時，需要逐一撿拾到晶粒載盤，在移轉到黏晶機或是覆晶接合機。如為覆晶接合的凸塊化晶片時，在晶粒載盤內的凸塊位於晶片之上表面，尚需要一道翻轉凸塊化晶片之動作，才可使晶片表面突出之凸塊朝向欲接合之基板。而晶片的撿拾製程與覆晶接合製程都是逐一晶片的處理，不僅製程繁瑣且成本較高。 Conventionally, when a plurality of wafers are cut from a semiconductor wafer, it is necessary to pick up the die carriers one by one and transfer them to the die bonder or the flip chip bonder. In the case of a flip chip bonded bump wafer, the bumps in the die carrier are located on the upper surface of the wafer, and a flipping of the bump wafer is required to make the bump protruding from the wafer surface to be bonded. The substrate. The wafer pick-up process and the flip chip bonding process are processed one by one, which is not only cumbersome and costly.
本國發明專利I338028號揭示一種「半導體裝置之製造方法及晶圓加工用膠帶」，其係研磨具凸塊晶圓之背面。使用一特殊晶圓加工用膠帶黏貼晶圓之主動面，晶圓之凸塊埋入至膠帶之黏合層，黏合層與基板膜之間為一可移除黏著層，此一黏貼狀態下，晶圓背面外露，由晶圓背面入刀，切割晶圓成為複數個晶片。保持黏合層自基板膜剝離但仍黏合於個別晶片之狀態下拾取晶片，進行覆晶接合。該前案技術雖可不需要翻轉晶片之動作，但晶圓背面一般未定義有切割道，又原本在晶圓主動面之可辨識切割道或定位標記已被黏合層覆蓋，容易有切割不準確之問題。此外，特殊晶圓加工用膠帶的材料成本亦相當的高。 Japanese Patent No. I338028 discloses a "method for manufacturing a semiconductor device and a tape for wafer processing" for polishing the back surface of a bump wafer. Using a special wafer processing tape to adhere to the active surface of the wafer, the bump of the wafer is buried into the adhesive layer of the tape, and a removable adhesive layer is formed between the adhesive layer and the substrate film. The back of the circle is exposed, and the wafer is cut into the back side of the wafer to cut the wafer into a plurality of wafers. The wafer is picked up while the adhesive layer is peeled off from the substrate film but still adhered to the individual wafer, and the flip chip bonding is performed. Although the prior art technology does not need to flip the wafer, the back surface of the wafer is generally not defined with a dicing street, and the identifiable scribe line or the positioning mark originally on the active surface of the wafer has been covered by the adhesive layer, which is easy to cut inaccurately. problem. In addition, the material cost of special wafer processing tapes is also quite high.
第1A至1G圖繪示一種已普遍使用中之習知覆晶接合方法由凸塊化晶圓之切割至覆晶接合等各步驟中之元件截面示意圖。 1A to 1G are schematic cross-sectional views showing an element in a conventionally used flip-chip bonding method from the cutting of a bumped wafer to a flip chip bonding.
如第1A圖所示，提供一半導體晶圓110，係包含複數個一體連接之晶片111，該半導體晶圓110之主動面112上係設置有複數個凸塊114，該半導體晶圓110之背面113係貼附於一具有暫時性黏著層121之切割載膜120。如第1B圖所示，以切割刀具130切割該半導體晶圓110，以使該些晶片111單獨黏附於該暫時性黏著層121。 As shown in FIG. 1A, a semiconductor wafer 110 is provided, which includes a plurality of integrally connected wafers 111. The active surface 112 of the semiconductor wafer 110 is provided with a plurality of bumps 114 on the back side of the semiconductor wafer 110. The 113 series is attached to a cutting carrier film 120 having a temporary adhesive layer 121. As shown in FIG. 1B, the semiconductor wafer 110 is diced by the dicing tool 130 so that the wafers 111 are individually adhered to the temporary adhesive layer 121.
如第1C圖所示，將該切割載膜120固定在一撿晶機之晶圓載台141上，習知撿晶機係具有由該晶圓載台141頂出之一個或多個頂針144，逐一地一個一個頂出該些晶片111並以上方之第一撿拾吸嘴145吸附被頂昇之晶片111。如第1D圖所示，移動該第一撿拾吸嘴145以將被撿拾的晶片111放置一晶粒載盤150(tray)之凹槽152內。 As shown in FIG. 1C, the cutting carrier film 120 is fixed on a wafer stage 141 of a crystallizer having one or more thimbles 144 ejected by the wafer stage 141, one by one. The wafers 111 are ejected one by one and the wafers 111 that are lifted are adsorbed by the first pick-up nozzles 145 above. As shown in FIG. 1D, the first pick-up nozzle 145 is moved to place the wafer 111 to be picked up in a groove 152 of a die carrier 150.
如第1E圖所示，移轉該晶粒載盤150至一覆晶接合機160，該覆晶接合機160係具有一第二撿拾吸嘴162以及一覆晶接合頭161(如第1F圖所示)。以該第二撿拾吸嘴162將該晶粒載盤150內之晶片111逐一撿拾吸附再翻轉該第二撿拾吸嘴162，以使被撿拾之晶片111之背面朝上(如第1F圖所示)。接著，如第1F圖所示，以該覆晶接合頭161對準於該第二撿拾吸嘴162以吸附被 撿拾之晶片111之背面。最後，如第1G圖所示，以該覆晶接合頭161往一基板170下壓，並加熱使該晶片111之凸塊114接合至該基板170，以使被撿拾之晶片111上片結合於該基板170上。故習知在晶片撿拾過程中須以頂針144頂推晶片之機械動作容易造成晶片111在撿拾時之破壞或報廢。另外，在覆晶接合過程中之逐一晶片翻轉與對位動作，亦會造成覆晶接合效率的降低。 As shown in FIG. 1E, the die carrier 150 is transferred to a flip chip bonding machine 160. The flip chip bonding machine 160 has a second pick-up nozzle 162 and a flip chip bonding head 161 (eg, FIG. 1F). Shown). The second wafer pick-up nozzle 162 picks up the wafers 111 in the die tray 150 one by one and then flips the second pick-up nozzles 162 to make the back side of the wafer 111 being picked up upward (as shown in FIG. 1F). ). Next, as shown in FIG. 1F, the flip chip bonding head 161 is aligned with the second pick-up nozzle 162 to be adsorbed by The back of the wafer 111 is picked up. Finally, as shown in FIG. 1G, the flip chip bonding head 161 is pressed down to a substrate 170, and heated to bond the bumps 114 of the wafer 111 to the substrate 170, so that the wafer 111 to be picked up is bonded to the substrate 111. On the substrate 170. Therefore, it is known that the mechanical action of pushing the wafer by the ejector pin 144 during the wafer pick-up process is liable to cause damage or scrapping of the wafer 111 during picking up. In addition, the wafer flipping and alignment operations during the flip chip bonding process also cause a decrease in the flip chip bonding efficiency.
為了解決上述之問題，本發明之主要目的係在於提供一種包含晶圓級撿晶之覆晶接合方法，防止習知以頂針頂推晶片之機械動作中造成晶片在撿拾時之破壞或報廢，並可在同一時間將整片晶圓中之晶片快速撿拾，無須使用習知承載盤逐一擺放晶片。 In order to solve the above problems, the main object of the present invention is to provide a flip chip bonding method including wafer level twinning, which prevents the destruction or scrapping of the wafer during picking up by the mechanical action of pushing the wafer by the ejector pin, and The wafers in the entire wafer can be quickly picked up at the same time, without the need to use a conventional carrier to place the wafers one by one.
本發明之次一目的係在於提供一種包含晶圓級撿晶之覆晶接合方法，在覆晶接合機中不需要針對每一晶片作翻轉晶片之動作以及兩吸嘴間轉載吸附之動作，以減輕對晶片上凸塊的傷害，以節省覆晶接合時間並降低覆晶接合製程之成本。 A second object of the present invention is to provide a flip chip bonding method including wafer level twinning, in which a flip chip operation for each wafer and a transfer between two nozzles are not required in the flip chip bonding machine, Reduce damage to bumps on the wafer to save flip-chip bonding time and reduce the cost of the flip chip bonding process.
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種包含晶圓級撿晶之覆晶接合方法，包含以下步驟：提供一半導體晶圓，係包含複數個一體連接之晶片，每一晶片係具有一主動面及一背面，其中該主動面上係設置有複數個凸塊，該背面係貼附於一具有感光性黏著層之切割載膜。之後，切割該半 導體晶圓，以使該些晶片單獨黏附於該感光性黏著層。之後，在一晶圓級撿晶設備中，翻轉該切割載膜並對準在一晶圓真空吸盤(wafer vacuum plate)上，該晶圓真空吸盤係固定於該晶圓級撿晶設備之一晶圓載台(wafer table)，該晶圓真空吸盤係具有複數個真空吸孔，用以提供一第一晶粒吸附力。之後，利用該晶圓級撿晶設備之一照射光源，光照射該切割載膜，使得該感光性黏著層之晶粒單元黏性降低至小於該第一晶粒吸附力，在該第一晶粒吸附力之作用下，該些晶片係由該切割載膜剝離並被吸附固定於該晶圓真空吸盤。之後，移轉該晶圓真空吸盤至一覆晶接合機，並利用該覆晶接合機之一覆晶接合頭，提供一第二晶粒吸附力以吸附其中一晶片之背面，其中該第二晶粒吸附力係大於該第一晶粒吸附力，以使上述被撿拾之晶片由該晶圓真空吸盤脫離，並保持其它未撿拾之晶片仍吸附於該晶圓真空吸盤。最後，移動該覆晶接合頭，以使上述被撿拾之晶片接合至一基板。 The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a flip chip bonding method including wafer level twinning, comprising the steps of: providing a semiconductor wafer comprising a plurality of integrally connected wafers, each wafer having an active surface and a back surface, wherein the active The surface is provided with a plurality of bumps attached to a cutting carrier film having a photosensitive adhesive layer. After that, cut the half The conductor wafer is such that the wafers are individually adhered to the photosensitive adhesive layer. Thereafter, in a wafer level twinning apparatus, the cutting carrier film is flipped and aligned on a wafer vacuum plate, the wafer vacuum chuck is fixed to one of the wafer level twinning devices. A wafer table having a plurality of vacuum suction holes for providing a first grain adsorption force. Thereafter, the light source is irradiated by one of the wafer level twinning devices, and the cutting carrier film is irradiated with light, so that the grain unit viscosity of the photosensitive adhesive layer is reduced to be smaller than the first crystal grain adsorption force, in the first crystal Under the action of the particle adsorption force, the wafers are peeled off from the cutting carrier film and adsorbed and fixed to the wafer vacuum chuck. Thereafter, transferring the wafer vacuum chuck to a flip chip bonding machine, and using a flip chip bonding head of the flip chip bonding machine to provide a second die attaching force to adsorb the back surface of one of the wafers, wherein the second The die attaching force is greater than the first die attaching force to cause the wafer to be picked up to be detached from the wafer vacuum chuck, and to keep other unsold wafers still adsorbed to the wafer vacuum chuck. Finally, the flip chip bond head is moved to bond the wafer being picked up to a substrate.
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。 The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述之覆晶接合方法中，該晶圓真空吸盤之該些真空吸孔係可劃分為複數個晶粒化區塊，以使該些真空吸孔對準吸附該些個別晶片之該些凸塊，達到整片晶圓中個別晶片在該晶圓真空吸盤內的自動對位式吸附固定。 In the above-mentioned flip chip bonding method, the vacuum suction holes of the wafer vacuum chuck can be divided into a plurality of graining blocks, so that the vacuum suction holes are aligned to adsorb the convex portions of the individual wafers. The block reaches the automatic alignment adsorption fixing of individual wafers in the wafer in the vacuum chuck of the wafer.
在前述之覆晶接合方法中，該切割載膜之周邊係黏附固定於一晶圓環，而在上述光照射該切割載膜之步驟 中，可藉由一環形光罩係遮護該晶圓環使其不受光照射，以保持在光照射過程中，該切割載膜仍貼附固定於該晶圓環。 In the above flip chip bonding method, the periphery of the dicing carrier film is adhered and fixed to a wafer ring, and the step of irradiating the cutting carrier film with the light is performed. The wafer ring can be shielded from light by an annular mask to keep the cutting carrier attached to the wafer ring during light irradiation.
在前述之覆晶接合方法中，該照射光源之光照射面積係可相當於該晶圓環之一晶圓容置開孔，故可不影響該切割載膜對該晶圓環之黏性。 In the above-described flip chip bonding method, the light irradiation area of the illumination source can correspond to one of the wafer ring receiving openings, so that the viscosity of the cutting carrier film to the wafer ring can be prevented.
在前述之覆晶接合方法中，該晶圓真空吸盤係可具有一尺寸對應於該半導體晶圓之晶圓凹陷區，該些真空吸孔係位於該晶圓凹陷區內，可維持該晶圓真空吸盤之該第一晶粒吸附力。 In the above flip chip bonding method, the wafer vacuum chuck may have a recessed area corresponding to the semiconductor wafer, and the vacuum chucks are located in the recessed area of the wafer to maintain the wafer The first grain adsorption force of the vacuum chuck.
在前述之覆晶接合方法中，該晶圓級撿晶設備之該晶圓載台係可為無頂針結構，不需要頂推該切割載膜。 In the foregoing flip chip bonding method, the wafer stage of the wafer level twinning device may be a thimbleless structure, and the cutting carrier film does not need to be pushed up.
在前述之覆晶接合方法中，該照射光源係可為一紫外光照度器(UV spot equipment)，可使該光罩為固定尺寸並結合在該照射光源內，以專屬應用於固定尺寸之半導體晶圓。 In the above-mentioned flip chip bonding method, the illumination source may be a UV spot equipment, and the reticle may be fixed in size and combined in the illumination source to be exclusively applied to a fixed size semiconductor crystal. circle.
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種 選置性之設計，詳細之元件佈局可能更為複雜。 The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual implementation of the number, shape and size ratio is a kind The optional design of the components may be more complicated.
依據本發明之一具體實施例，一種包含晶圓級撿晶之覆晶接合方法舉例說明於第2A至2G圖之於各步驟中之元件截面示意圖、第3圖為在第2C圖步驟中之立體示意圖、第4圖為在第2D圖步驟中之立體示意圖、第5圖為在第2F圖步驟中之立體示意圖、以及第6圖為在第2G圖步驟中之立體示意圖。該覆晶接合方法包含以下之步驟。 According to an embodiment of the present invention, a flip chip bonding method including wafer level twins is exemplified in the cross-sectional views of the elements in the steps 2A to 2G, and FIG. 3 is in the step 2C. 3D is a perspective view in the 2D step, FIG. 5 is a perspective view in the 2F step, and FIG. 6 is a perspective view in the 2G step. The flip chip bonding method includes the following steps.
如第2A圖所示，提供一半導體晶圓210，係包含複數個一體連接之晶片211，每一晶片211係具有一主動面212及一背面213，其中該主動面212上係設置有複數個凸塊214，該背面213係貼附於一具有感光性黏著層221之切割載膜220。在一具體實施例中，該切割載膜220之周邊係黏附固定於一晶圓環222(如第3圖所示)。該半導體晶圓210係已可經過晶背研磨，該主動面212上可已製作好所欲的積體電路、光感測元件、微機電元件等主動元件，該些凸塊214為該些晶片211之對外接點。在本實施例中，該些凸塊214係可為如銅柱之柱狀凸塊214，其端面係可形成有銲料215。 As shown in FIG. 2A, a semiconductor wafer 210 is provided, which includes a plurality of integrally connected wafers 211, each of which has an active surface 212 and a back surface 213, wherein the active surface 212 is provided with a plurality of The bump 214 is attached to a cutting carrier film 220 having a photosensitive adhesive layer 221 . In one embodiment, the perimeter of the dicing film 220 is adhered to a wafer ring 222 (as shown in FIG. 3). The semiconductor wafer 210 can be subjected to crystal back grinding. The active surface 212 can be formed with active components such as an integrated circuit, a light sensing component, and a microelectromechanical component. The bumps 214 are the wafers. 211 external contacts. In this embodiment, the bumps 214 may be columnar bumps 214 such as copper pillars, and the end faces thereof may be formed with solder 215.
之後，如第2B圖所示，以一雷射或機械刀輪之切割刀具230切割該半導體晶圓210，以使該些晶片211單獨黏附於該感光性黏著層221。 Thereafter, as shown in FIG. 2B, the semiconductor wafer 210 is cut by a laser or mechanical cutter cutting tool 230 so that the wafers 211 are individually adhered to the photosensitive adhesive layer 221.
之後，如第2C及3圖所示，在一晶圓級撿晶設備240中，翻轉該切割載膜220並對準在一晶圓真空吸盤 250(wafer vacuum plate)上，該晶圓真空吸盤250係固定於該晶圓級撿晶設備240之一晶圓載台241(wafer table)，該晶圓真空吸盤250係具有複數個真空吸孔251，用以提供一第一晶粒吸附力F1。較佳地，該晶圓真空吸盤250之該些真空吸孔251係可劃分為複數個晶粒化區塊252(如第3圖所示)，以使該些真空吸孔251對準吸附該些個別晶片211之該些凸塊214，達到整片晶圓中個別晶片211在該晶圓真空吸盤250內的自動對位式吸附固定。該晶圓級撿晶設備240係另包含一照射光源242，係位於該晶圓載台241之上方。 Thereafter, as shown in FIGS. 2C and 3, in a wafer level twinning device 240, the cutting carrier film 220 is flipped and aligned to a wafer vacuum chuck. On the 250 (wafer vacuum plate), the wafer vacuum chuck 250 is fixed to a wafer table 241 of the wafer level twinning device 240. The wafer vacuum chuck 250 has a plurality of vacuum suction holes 251. For providing a first grain adsorption force F1. Preferably, the vacuum suction holes 251 of the wafer vacuum chuck 250 can be divided into a plurality of graining blocks 252 (as shown in FIG. 3), so that the vacuum suction holes 251 are aligned and adsorbed. The bumps 214 of the individual wafers 211 achieve automatic alignment and adsorption fixation of the individual wafers 211 in the wafer vacuum chuck 250 in the entire wafer. The wafer level twinning device 240 further includes an illumination source 242 located above the wafer stage 241.
在一較佳型態中，該晶圓真空吸盤250係可具有一尺寸對應於該半導體晶圓210之晶圓凹陷區253(如第3圖所示)，該些真空吸孔251係位於該晶圓凹陷區253內，可維持該晶圓真空吸盤250之該第一晶粒吸附力F1。 In a preferred embodiment, the wafer vacuum chuck 250 can have a recessed area 253 corresponding to the semiconductor wafer 210 (as shown in FIG. 3), and the vacuum suction holes 251 are located therein. The first die adhesion force F1 of the wafer vacuum chuck 250 can be maintained in the wafer recessed area 253.
之後，如第2D及4圖所示，利用該晶圓級撿晶設備240之一照射光源242，光照射該切割載膜220，使得該感光性黏著層221之晶粒單元黏性降低至小於該第一晶粒吸附力F1。此時該感光性黏著層221會產生氮氣(N2 gas)而將該些晶片211排出。同時在下方該晶圓真空吸盤250之該第一晶粒吸附力F1之作用下，整片晶圓上的該些晶片211將由該切割載膜220剝離並被吸附固定於該晶圓真空吸盤250。故該晶圓級撿晶設備240之該晶圓載台241係可為無頂針結構，不需要頂推該切割載膜220。 Thereafter, as shown in FIGS. 2D and 4, the light source 242 is irradiated by one of the wafer level twinning devices 240, and the cutting carrier film 220 is irradiated with light, so that the grain unit viscosity of the photosensitive adhesive layer 221 is reduced to less than The first crystal grain has an adsorption force F1. At this time, the photosensitive adhesive layer 221 generates nitrogen gas (N 2 gas) to discharge the wafers 211. At the same time, under the action of the first die attaching force F1 of the wafer vacuum chuck 250, the wafers 211 on the entire wafer are peeled off from the cut carrier film 220 and adsorbed and fixed on the wafer vacuum chuck 250. . Therefore, the wafer stage 241 of the wafer level twinning device 240 can be a thimbleless structure, and the cutting carrier film 220 does not need to be pushed up.
此外，在上述光照射該切割載膜220之步驟中，較佳可藉由一環形光罩243係遮護該晶圓環222使其不受光照射，以保持在光照射過程中，該切割載膜220仍貼附固定於該晶圓環222。因此，該照射光源242之光照射面積係可相當於該晶圓環222之一晶圓容置開孔223，故可不影響該切割載膜220對該晶圓環222之黏性。在本實施例中，該照射光源242係可為一紫外光照度器(UV spot equipment)，可使該光罩為固定尺寸並結合在該照射光源242內，以專屬應用於固定尺寸之半導體晶圓。 In addition, in the step of irradiating the cutting carrier film 220 with light, the wafer ring 222 is preferably shielded from light by an annular mask 243 to maintain the light during the illumination process. The film 220 is still attached to the wafer ring 222. Therefore, the light irradiation area of the illumination light source 242 can correspond to one of the wafer ring openings 223 of the wafer ring 222, so that the viscosity of the cutting carrier film 220 to the wafer ring 222 can be prevented. In this embodiment, the illumination source 242 can be a UV spot device, and the reticle can be fixedly combined and integrated in the illumination source 242 for exclusive use in a fixed size semiconductor wafer. .
之後，如第2E、2F及5圖所示，移轉該晶圓真空吸盤250至一覆晶接合機260，並利用該覆晶接合機260之一覆晶接合頭261，提供一第二晶粒吸附力F2以吸附其中一晶片211之背面213，其中該第二晶粒吸附力F2係大於該第一晶粒吸附力F1，以使上述被撿拾之晶片211由該晶圓真空吸盤250脫離，並保持其它未撿拾之晶片211仍吸附於該晶圓真空吸盤250。較佳地，在移轉該晶圓真空吸盤250之過程中，保持該晶圓環222以及該已照光之切割載膜220蓋合於該晶圓真空吸盤250上，以防止該晶圓真空吸盤250在機台移轉時之破真空發生，直到該晶圓真空吸盤250被裝載入該覆晶接合機260時再拔除該晶圓環222與該切割載膜220。 Thereafter, as shown in FIGS. 2E, 2F, and 5, the wafer vacuum chuck 250 is transferred to a flip chip bonding machine 260, and a bonding die 261 is flip-chip bonded by one of the flip chip bonding machines 260 to provide a second crystal. The particle adsorption force F2 is to adsorb the back surface 213 of one of the wafers 211, wherein the second grain adsorption force F2 is greater than the first grain adsorption force F1, so that the picked-up wafer 211 is separated from the wafer vacuum chuck 250. And keeping other unsold wafers 211 still adsorbed to the wafer vacuum chuck 250. Preferably, during the transfer of the wafer vacuum chuck 250, the wafer ring 222 and the illuminated cutting carrier film 220 are held on the wafer vacuum chuck 250 to prevent the wafer vacuum chuck. The vacuum breaking occurs when the machine is transferred, until the wafer vacuum chuck 250 is loaded into the flip chip bonding machine 260, and the wafer ring 222 and the cutting carrier film 220 are removed.
最後，如第2G及6圖所示，移動該覆晶接合頭261，以使上述被撿拾之晶片211接合至一基板270。該基板270係可為一封裝載板、一導線架、一印刷電路板、一 晶片211或是一晶片211堆疊體之上方晶片211。 Finally, as shown in FIGS. 2G and 6, the flip chip bonding head 261 is moved to bond the wafer 211 to be picked up to a substrate 270. The substrate 270 can be a loading board, a lead frame, a printed circuit board, and a The wafer 211 is either a wafer 211 above the stack of wafers 211.
因此，本發明提供一種包含晶圓級撿晶之覆晶接合方法能防止習知以頂針頂推晶片之機械動作中造成晶片在撿拾時之破壞或報廢，並可在同一時間將整片晶圓中之晶片快速撿拾，無須使用習知承載盤逐一擺放晶片。此外，在覆晶接合機中不需要針對每一晶片作翻轉晶片之動作以及兩吸嘴間轉載吸附之動作，以減輕對晶片上凸塊的傷害，以節省覆晶接合時間並降低覆晶接合製程之成本。 Therefore, the present invention provides a flip chip bonding method including wafer level twinning, which can prevent the wafer from being damaged or scrapped during the mechanical action of pushing the wafer by the ejector pin, and can process the entire wafer at the same time. The wafers in the middle are quickly picked up, and the wafers need not be placed one by one using conventional carrier disks. In addition, in the flip chip bonding machine, there is no need to perform the action of flipping the wafer for each wafer and the action of transferring the adsorption between the two nozzles to reduce the damage to the bumps on the wafer, thereby saving the flip chip bonding time and reducing the flip chip bonding. The cost of the process.
以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，雖然本發明已以較佳實施例揭露如上，然而並非用以限定本發明，任何熟悉本項技術者，在不脫離本發明之技術範圍內，所作的任何簡單修改、等效性變化與修飾，均仍屬於本發明的技術範圍內。 The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.
110‧‧‧半導體晶圓 110‧‧‧Semiconductor wafer
111‧‧‧晶片 111‧‧‧ wafer
112‧‧‧主動面 112‧‧‧Active surface
113‧‧‧背面 113‧‧‧Back
114‧‧‧凸塊 114‧‧‧Bumps
120‧‧‧切割載膜 120‧‧‧ cutting carrier film
121‧‧‧暫時性黏著層 121‧‧‧ Temporary adhesive layer
130‧‧‧切割刀具 130‧‧‧Cutting tools
141‧‧‧晶圓載台 141‧‧‧ Wafer stage
144‧‧‧頂針 144‧‧‧ thimble
145‧‧‧第一撿拾吸嘴 145‧‧‧First pick up nozzle
150‧‧‧晶粒載盤 150‧‧‧Grade carrier
152‧‧‧凹槽 152‧‧‧ Groove
160‧‧‧覆晶接合機 160‧‧‧Face welding machine
161‧‧‧覆晶接合頭 161‧‧‧Face bonded joint
162‧‧‧第二撿拾吸嘴 162‧‧‧Second pick up nozzle
170‧‧‧基板 170‧‧‧Substrate
210‧‧‧半導體晶圓 210‧‧‧Semiconductor wafer
211‧‧‧晶片 211‧‧‧ wafer
212‧‧‧主動面 212‧‧‧Active surface
213‧‧‧背面 213‧‧‧ back
214‧‧‧凸塊 214‧‧‧Bumps
215‧‧‧銲料 215‧‧‧ solder
220‧‧‧切割載膜 220‧‧‧ cutting carrier film
221‧‧‧感光性黏著層 221‧‧‧Photosensitive adhesive layer
222‧‧‧晶圓環 222‧‧‧ wafer ring
223‧‧‧晶圓容置開孔 223‧‧‧ wafer mounting opening
230‧‧‧切割刀具 230‧‧‧Cutting tools
240‧‧‧晶圓級撿晶設備 240‧‧‧Watt-level twinning equipment
241‧‧‧晶圓載台 241‧‧‧ Wafer stage
242‧‧‧照射光源 242‧‧‧ illumination source
243‧‧‧環形光罩 243‧‧‧Circular mask
250‧‧‧晶圓真空吸盤 250‧‧‧ wafer vacuum chuck
251‧‧‧真空吸孔 251‧‧‧Vacuum suction hole
252‧‧‧晶粒化區塊 252‧‧‧Gradized blocks
253‧‧‧晶圓凹陷區 253‧‧‧ Wafer recessed area
260‧‧‧覆晶接合機 260‧‧‧Face welding machine
261‧‧‧覆晶接合頭 261‧‧‧Face bonded joint
270‧‧‧基板 270‧‧‧Substrate
F1‧‧‧第一晶粒吸附力 F1‧‧‧first grain adsorption
F2‧‧‧第二晶粒吸附力 F2‧‧‧Second grain adsorption force
第1A至1G圖：繪示一種習知覆晶接合方法於各步驟中之元件截面示意圖。 1A to 1G are views showing a cross-sectional view of a conventional flip chip bonding method in each step.
第2A至2G圖：依據本發明之一具體實施例，繪示一種包含晶圓級撿晶之覆晶接合方法於各步驟中之元件截面示意圖。 2A to 2G are diagrams showing a cross-sectional view of an element in each step of a flip chip bonding method including wafer level twins in accordance with an embodiment of the present invention.
第3圖：依據本發明之一具體實施例，繪示在該覆晶接合方法在第2C圖步驟中之立體示意圖。 Figure 3 is a perspective view showing the flip chip bonding method in the step 2C in accordance with an embodiment of the present invention.
第4圖：依據本發明之一具體實施例，繪示在該覆晶接 合方法在第2D圖步驟中之立體示意圖。 Figure 4: According to an embodiment of the present invention, the flip chip is illustrated A perspective view of the method in the 2D step.
第5圖：依據本發明之一具體實施例，繪示在該覆晶接合方法在第2F圖步驟中之立體示意圖。 Fig. 5 is a perspective view showing the flip chip bonding method in the step of Fig. 2F according to an embodiment of the present invention.
第6圖：依據本發明之一具體實施例，繪示在該覆晶接合方法在第2G圖步驟中之立體示意圖。 Figure 6 is a perspective view showing the method of the flip chip bonding in the step of the second G pattern according to an embodiment of the present invention.
211‧‧‧晶片 211‧‧‧ wafer
212‧‧‧主動面 212‧‧‧Active surface
214‧‧‧凸塊 214‧‧‧Bumps
220‧‧‧切割載膜 220‧‧‧ cutting carrier film
222‧‧‧晶圓環 222‧‧‧ wafer ring
223‧‧‧晶圓容置開孔 223‧‧‧ wafer mounting opening
241‧‧‧晶圓載台 241‧‧‧ Wafer stage
242‧‧‧照射光源 242‧‧‧ illumination source
243‧‧‧環形光罩 243‧‧‧Circular mask
250‧‧‧晶圓真空吸盤 250‧‧‧ wafer vacuum chuck
251‧‧‧真空吸孔 251‧‧‧Vacuum suction hole
252‧‧‧晶粒化區塊 252‧‧‧Gradized blocks
253‧‧‧晶圓凹陷區 253‧‧‧ Wafer recessed area
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101145351A TW201423873A (en) | 2012-12-03 | 2012-12-03 | Flip-chip bonding method including wafer level picking-up |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101145351A TW201423873A (en) | 2012-12-03 | 2012-12-03 | Flip-chip bonding method including wafer level picking-up |
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| Publication Number | Publication Date |
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| TW201423873A true TW201423873A (en) | 2014-06-16 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11742314B2 (en) | 2020-03-31 | 2023-08-29 | Adeia Semiconductor Bonding Technologies Inc. | Reliable hybrid bonded apparatus |
| US11742315B2 (en) | 2017-04-21 | 2023-08-29 | Adeia Semiconductor Bonding Technologies Inc. | Die processing |
| US11855064B2 (en) | 2018-02-15 | 2023-12-26 | Adeia Semiconductor Bonding Technologies Inc. | Techniques for processing devices |
-
2012
- 2012-12-03 TW TW101145351A patent/TW201423873A/en unknown
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11742315B2 (en) | 2017-04-21 | 2023-08-29 | Adeia Semiconductor Bonding Technologies Inc. | Die processing |
| US11855064B2 (en) | 2018-02-15 | 2023-12-26 | Adeia Semiconductor Bonding Technologies Inc. | Techniques for processing devices |
| US11742314B2 (en) | 2020-03-31 | 2023-08-29 | Adeia Semiconductor Bonding Technologies Inc. | Reliable hybrid bonded apparatus |
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