CN117650098A - 制造包括导电线的半导体器件的方法 - Google Patents

制造包括导电线的半导体器件的方法 Download PDF

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Publication number
CN117650098A
CN117650098A CN202310238399.6A CN202310238399A CN117650098A CN 117650098 A CN117650098 A CN 117650098A CN 202310238399 A CN202310238399 A CN 202310238399A CN 117650098 A CN117650098 A CN 117650098A
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China
Prior art keywords
layer
conductive layer
trench
deposition process
hole
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CN202310238399.6A
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English (en)
Inventor
尹在万
金俊基
金泰均
朴靖雨
河在源
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SK Hynix Inc
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SK Hynix Inc
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Publication of CN117650098A publication Critical patent/CN117650098A/zh
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    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
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Abstract

一种制造半导体器件的方法包括：提供绝缘中间层；通过对绝缘中间层进行刻蚀而在绝缘中间层中形成沟槽；使用第一沉积工艺在绝缘中间层的上表面上以及沟槽的底部表面和侧表面上形成导电层，在沟槽的底部表面上的导电层比在沟槽的侧表面上的导电层厚；使用与第一沉积工艺不同的第二沉积工艺在沟槽中形成牺牲层，该牺牲层覆盖形成在沟槽的底部表面上的导电层；选择性地去除通过牺牲层暴露的、形成在绝缘中间层的上表面上的导电层以及形成在沟槽的侧表面上的导电层；以及选择性地去除牺牲层，以使用保留在沟槽的底部表面上的导电层来形成导电线。

Description

制造包括导电线的半导体器件的方法
相关申请的交叉引用
本申请要求2022年9月2日在韩国知识产权局提交的申请号为10-2022-0111259的韩国专利申请的优先权，其通过引用整体合并于此。
技术领域
各种实施例总体上涉及一种制造半导体器件的方法，并且更具体地，涉及一种制造包括导电线的半导体器件的方法。
背景技术
由于半导体器件的宽度已经变细并且半导体器件的集成度已经增大，所以可以使用镶嵌技术形成导电线。
在镶嵌技术中，可以在绝缘层中形成线性沟槽。可以用导电层填充沟槽，以形成导电线。近来，由于半导体器件已经被高度集成，所以半导体器件的宽度已经大大减小，使得已经提出用导电层填充沟槽而没有电气缺陷的技术。
发明内容
根据本公开的是一种制造半导体器件的方法。该方法包括：提供绝缘中间层；通过对绝缘中间层的选定部分进行刻蚀而在绝缘中间层中形成沟槽；使用第一沉积工艺在绝缘中间层的上表面上以及沟槽的底部表面和侧表面上形成导电层，其中，形成在沟槽的底部表面上的导电层的厚度大于形成在沟槽的侧表面上的导电层的厚度；使用与第一沉积工艺不同的第二沉积工艺在沟槽中形成牺牲层，以覆盖形成在沟槽的底部表面上的导电层；选择性地去除通过牺牲层被暴露的、形成在绝缘中间层的上表面上的导电层以及形成在沟槽的侧表面上的导电层；以及选择性地去除牺牲层，以使用保留在沟槽的底部表面上的导电层来形成导电线。
根据本公开的是一种制造半导体器件的方法。该方法包括：提供包括第一孔的绝缘层，该第一孔具有第一高宽比(aspect ratio)；通过第一沉积工艺在绝缘层上形成导电层，该第一沉积工艺在第一孔的侧表面上具有第一沉积速率以及在第一孔的底部表面上具有第二沉积速率，并且第二沉积速率高于第一沉积速率；在第一孔中形成牺牲层以覆盖第一孔的底部表面上的导电层；选择性地去除通过牺牲层暴露的、形成在第一孔的侧表面上的导电层；去除牺牲层以限定第二孔，该第二孔在第一孔中的导电层上，该第二孔具有比第一高宽比小的第二高宽比；以及在第二孔中形成间隙填充绝缘层。
根据本公开的是一种制造半导体器件的方法。该方法包括：提供包括杂质区域的半导体衬底；对半导体衬底进行刻蚀以形成沟槽；在沟槽的表面以及半导体衬底的上表面上形成栅极绝缘层；通过第一沉积工艺在栅极绝缘层上形成第一栅极导电层，第一沉积工艺在与半导体衬底的上表面基本平行的部分上具有第一沉积速率以及在与半导体衬底的上表面基本垂直的部分上具有第二沉积速率，其中第二沉积速率高于第一沉积速率；在沟槽中形成牺牲层，以使在半导体衬底的上表面上的第一栅极导电层和在沟槽的侧表面上的第一栅极导电层暴露；选择性地去除通过牺牲层暴露的第一栅极导电层；以及去除牺牲层，以使用保留在沟槽中的第一栅极导电层形成掩埋栅极。
附图说明
从结合附图的以下详细描述中，将更清楚地理解本公开的主题的上述方面和其他方面、特征和优点，其中：
图1A至图1H是示出根据示例性实施例的形成半导体器件的导电线的方法的横截面图；
图2是示出根据示例性实施例的PVD工艺的原理的视图；
图3A至图3G是示出根据示例性实施例的通过镶嵌工艺形成导电线的方法的透视图；以及
图4A至图4G是示出根据示例性实施例的形成半导体器件的掩埋栅极的方法的横截面图。
具体实施方式
将参考附图更详细描述本教导的各种实施例。附图是各种实施例(和中间结构)的示意图示。这样，可以预期例如由于制造技术和/或公差而导致的图示的配置和形状的变化。因此，所描述的实施例不应被解释为限于本文所示的特定配置和形状，而是可以包括不脱离如所附权利要求所限定的本教导的精神和范围的配置和形状的偏差。
本文中参考理想化实施例的横截面图和/或平面图示描述了本教导。然而，本教导的实施例不应被解释为限制本发明构思。尽管将示出和描述本教导的几个实施例，但是本领域的普通技术人员将理解的是，在不脱离本教导的原则和精神的情况下，可以对这些实施例进行改变。
图1A至图1H是示出根据示例性实施例的形成半导体器件的导电线的方法的横截面图。
参考图1A，可以在衬底Sub的上表面上形成绝缘层10。例如，绝缘层10可以包括以下之中的至少一种：具有低介电常数的绝缘层、氧化硅层、以及氮化硅层，但不限于此。
各种电路层和各种绝缘层可以介于衬底Sub与绝缘层10之间。可以对绝缘层10进行刻蚀以形成接触孔H。接触孔H可以包括通孔、沟槽、凹槽等。从平面图看，接触孔H可以具有线性形状或图案形状。
参考图1B，可以通过第一沉积工艺在接触孔H中形成第一导电层20。第一沉积工艺可能具有较差的台阶覆盖特性。例如，在第一沉积工艺中，可以在面向靶材(targetmaterial)TM(例如，导电材料)的表面上更多地执行沉积。因此，在接触孔H的侧表面上的第一导电层20的第一部分的厚度可以比面向靶材TM的在绝缘层10的上表面上以及接触孔H的底部表面上的第一导电层20的第二部分的厚度薄。即，在绝缘层10的上表面以及接触孔H的底部表面上的第一导电层20中的第二部分的厚度可以比在接触孔H的侧表面上的第一导电层20中的第一部分的厚度厚。接触孔H的底部表面可以与衬底Sub的上表面基本平行。
第一沉积工艺可以包括物理气相沉积(PVD)工艺，诸如溅射工艺和热蒸发。因为第一沉积工艺可以具有相对于一个方向的良好的沉积特性，所以当层可以被沉积在非平坦表面上时，第一沉积工艺可以具有相对低的台阶覆盖特性。
图2是示出根据示例性实施例的PVD工艺的原理的视图。
参考图2，可以在PVD室70(例如溅射室)中执行第一沉积工艺。
PVD室70可以包括：支撑构件72，其被配置为支撑衬底Sub；和靶75，其面对支撑构件72。靶75可以对应于图1B中的附图标记TM。靶75可以是第一导电层20的主要材料。
PVD室70还可以包括真空泵77和泵送管线PL。PVD室可以包括：内部空间，其通过真空泵77和泵送管线PL处于高真空状态下。
为了生成用于附着靶75的离子，作为反应气体的氩气可以在真空状态下被引入到PVD室70中。当RF功率或大约5000V的DC电压可以被施加到PVD室70时，可以在靶75与衬底Sub之间生成电场E，使得氩气可以被转换成带有电子和阳离子的等离子体状态。
氩气可以是具有中性状态的惰性气体。然而，氩原子的最外层电子可以被等离子体释放。所释放的电子可以与靶75碰撞以使靶75的化学键断裂。因此，靶75的金属离子可以被直接移向衬底Sub以将靶沉积在衬底Sub上。
PVD工艺可以使用从靶75释放的金属离子的直线度。因此，可以根据金属离子的方向而改变沉积速率。由PVD工艺形成的层可能不包括杂质。当第一导电层20可以通过PVD工艺形成时，第一导电层20在面对(平行于)靶75的接触孔H的底部表面以及绝缘层10的上表面上的沉积速率可以相对高于第一导电层20在与靶75基本垂直的接触孔H的侧表面(侧壁)上的沉积速率。因此，在接触孔H的底部表面上以及绝缘层10的上表面上的第一导电层20的第二部分可以具有设定厚度。相反，在接触孔H的侧表面上的第一导电层20的第一部分的厚度可以低于设定厚度。可替代性地，第一导电层20可能不形成在接触孔H的侧表面上。
在示例性实施例中，第一导电层20可以包括以下各者中的至少一者：具有至少一种金属元素的金属层；具有至少一种金属元素和氮元素的金属氮化物层；具有至少一种金属元素、氮元素、以及氧元素的金属氮氧化物层；具有至少一种金属元素和硅元素的金属硅化物；以及包括导电杂质的掺杂多晶硅层。例如，金属层可以包括W、Al、Cu、Ti、Ta、Ru、Zr、Mo、Rh、TiW、TaW等。金属氮化物层可以包括TiN、TaN、WN、MoN、NbN、TiSiN、TiAlN、TiBN、ZrSiN、WSiN、WBN、ZrAlN、MoSiN、MoAlN、TaSiN、TaAlN等。金属氮氧化物层可以包括TiON、TiAlON、WON、TaON等。金属硅化物可以包括TiSi、TaSi、PtSi、MoSi、WSi等。然而，第一导电层20可以包括各种金属或导电材料，不限于上述材料。
参考图1C，可以在第一导电层20之上形成牺牲层30。
在示例性实施例中，牺牲层30可以通过第二沉积工艺形成。第二沉积工艺可以具有比第一沉积工艺更好的台阶覆盖率。牺牲层30可以通过化学气相沉积(CVD)工艺、等离子体增强化学气相沉积(PECVD)工艺、原子层沉积(ALD)工艺、等离子体增强原子层沉积(PEALD)工艺等形成。因为牺牲层30可以沿着具有第一导电层20的接触孔H的内表面形成，所以尽管牺牲层30可以通过具有良好台阶覆盖率的第二沉积工艺形成，但是可以在牺牲层30中生成空隙V或缝隙。
牺牲层30可以起到保护接触孔H的底部表面上的第一导电层20的作用。例如，牺牲层30可以包括：相对于第一导电层20和绝缘层10具有良好的高刻蚀选择性的材料。牺牲层30可以包括氮化硅层。
参考图1D，可以选择性地刻蚀(或去除)牺牲层30以使第一导电层20暴露。
在示例性实施例中，可以对牺牲层30进行各向异性地刻蚀以使在绝缘层10上的第一导电层20暴露。在接触孔H的底部表面上的第一导电层20可以保持被牺牲层30覆盖。
参考图1E，可以使用剩余的牺牲层30作为掩模来选择性地去除所暴露的第一导电层20。因为选择性地刻蚀可以存在于第一导电层20与牺牲层30之间，所以可以选择性地去除：在接触孔H外部的绝缘层10的上表面上、以及接触孔H的侧表面上的第一导电层20。
在示例性实施例中，可以通过湿法刻蚀工艺和干法刻蚀工艺中的至少一种来去除第一导电层20。因为牺牲层30可以覆盖位于接触孔H的底部表面上的第一导电层20，所以可能不会去除位于接触孔H的底部表面上的第一导电层20。
参考图1F，可以选择性地去除接触孔H中的牺牲层30。
可以使用相对于绝缘层10和第一导电层20具有良好的刻蚀选择性的刻蚀剂来选择性地去除牺牲层30。例如，可以通过湿法刻蚀工艺去除牺牲层30，但不限于此。例如，当牺牲层30包括氮化硅层时，可以使用PH3溶液去除牺牲层30。
通过去除牺牲层30，第一导电层20可以保留在接触孔H的底部表面上。相反，第一导电层20可以不保留在接触孔H的侧表面上。可替代性地，微量的第一导电层20可以保留在接触孔H的侧表面上。
当微量的第一导电层20保留在接触孔H的侧表面上时，可以通过清洗(cleaning)工艺去除在接触孔H的侧表面上的第一导电层20。因为清洗工艺可以去除微量的第一导电层20，所以在接触孔H的底部表面上的第一导电层20的厚度不会受到清洗工艺的影响。清洗工艺可以包括湿法清洗工艺或干法清洗工艺，但不限于此。
参考图1G，可以通过清洗工艺去除在接触孔H的侧表面上的第一导电层20。第一导电层20可以作为图案形状保留在接触孔H′的底部表面上。因此，接触孔H′中的空的空间的高度h1可以小于初始接触孔H的高度h2，以通过第一导电层20形成具有改进的高宽比的接触孔H′。
参考图1H，可以在具有第一导电层20的接触孔H′中形成掩埋层40。掩埋层40可以包括导电层和绝缘层中的至少一者。在示例性实施例中，掩埋层40可以包括：在接触孔H′中的间隙填充绝缘层。间隙填充绝缘层可以包括具有良好的掩埋特性的旋涂电介质(spin ondielectric)。可替代性地，掩埋层40可以包括：在第一导电层20上的第二导电层、和在第二导电层上的间隙填充绝缘层。第二导电层可以包括：与第一导电层20的材料不同的材料。例如，第二导电层可以包括：掺杂有杂质的多晶硅层。
在示例性实施例中，掩埋层40可以通过与第一沉积工艺不同的第三沉积工艺形成。第三沉积工艺的台阶覆盖率可以比第一沉积工艺的台阶覆盖率更好。第三沉积工艺可以与第一沉积工艺基本相同。可替代性地，第三沉积工艺的台阶覆盖率可以大于第二沉积工艺的台阶覆盖率。
例如，第三沉积工艺可以包括CVD工艺、PECVD工艺、ALD工艺、PEALD工艺或旋涂工艺。
掩埋层40可以通过第三沉积工艺形成在具有改进的高宽比的接触孔H′中。因此，可能不会在接触孔H′中生成空隙或缝隙。然后可以通过化学机械抛光(CMP)工艺去除掩埋层40。
图3A至图3G是示出根据示例性实施例的通过镶嵌工艺形成导电线的方法的透视图。例如，导电线可以是位线。
参考图3A，可以在衬底Sub上形成绝缘中间层110。外围电路层(未示出)可以被布置在衬底Sub与绝缘中间层110之间。例如，外围电路层可以包括：用于驱动存储单元的多个电路图案。绝缘中间层110可以包括：多个接触插塞CP，其与外围电路层电连接，具有不同的功能；以及导电端子，其被形成在绝缘中间层110中或被形成在绝缘中间层110上。
例如，绝缘中间层110可以包括氧化硅层。可替代性地，绝缘中间层110可以包括：具有平坦化绝缘层的多层。
可以对绝缘中间层110进行刻蚀以形成具有线性形状的沟槽t。沟槽t可以被形成在要形成半导体存储器件的位线的区域处。可以考虑位线的线宽来确定沟槽t的宽度。一些接触插塞CP可以通过沟槽t的底部表面被暴露。沟槽t可以具有比绝缘中间层110的厚度h4小的高度h3。
参考图3B，可以通过诸如PVD工艺的第一沉积工艺在绝缘中间层110上和沟槽t内形成用于位线的导电层120。如上所述，因为PVD工艺可以使面向靶材的部分具有高沉积速率，所以在沟槽t的底部表面和绝缘中间层110上的导电层120可以具有相对较厚的厚度。导电层120的厚度可以比位线的厚度厚约1％至约20％。当可能在随后的清洗工艺中损失导电层120时，可以考虑导电层120的厚度。在图3B中，附图标记120a可以指的是：用于在沟槽t的底部表面上的第一位线的导电层。附图标记120b可以指的是：用于在沟槽t的侧表面上和绝缘中间层110的上表面上的第二位线的导电层。例如，用于第一位线的导电层120a可以包括：具有至少一种金属元素的金属层；具有至少一种金属元素和氮元素的金属氮化物层；具有至少一种金属元素、氮元素、以及氧元素的金属氮氧化物层；具有至少一种金属元素和硅元素的金属硅化物；掺杂多晶硅层等。
例如，金属层可以包括W、Al、Cu、Ti、Ta、Ru、Zr、Mo、Rh、TiW、TaW等。金属氮化物层可以包括TiN、TaN、WN、MoN、NbN、TiSiN、TiAlN、TiBN、ZrSiN、WSiN、WBN、ZrAlN、MoSiN、MoAlN、TaSiN、TaAlN等。金属氮氧化物层可以包括TiON、TiAlON、WON、TaON等。金属硅化物可以包括TiSi、TaSi、PtSi、MoSi、WSi等。然而，导电层120a可以包括各种金属或导电材料，不限于上述材料。
参考图3C，可以在沟槽t中形成牺牲层130。例如，牺牲层130可以包括：具有与绝缘中间层110和导电层120的刻蚀选择性不同的刻蚀选择性的材料。例如，牺牲层130可以包括氮化硅层。牺牲层130可以通过CVD工艺形成，CVD工艺的台阶覆盖率比PVD工艺的台阶覆盖率更好。牺牲层130的厚度可以被设置为不填满沟槽t。例如，牺牲层130的厚度可以小于具有导电层120的沟槽t的宽度。然而，在沉积牺牲层130时，可以通过具有不规则厚度的导电层120在沟槽t的入口处生成悬垂部(overhang)，以在沟槽t中产生空隙v。
参考图3D，可以对牺牲层130进行回蚀，以暴露用于第二位线的导电层120b。在示例性实施例中，可以通过被刻蚀的牺牲层130a部分地暴露用于第二位线的导电层120b的一部分以及导电层120b的上表面。
参考图3E，可以选择性地去除所暴露的用于第二位线的导电层120b。例如，可以通过湿法刻蚀工艺去除用于第二位线的导电层120b。通过湿法刻蚀工艺对用于第二位线的导电层120b进行刻蚀，可以通过牺牲层130a与绝缘中间层110之间的间隙很容易地去除保留在沟槽t的侧表面上的用于第二位线的导电层120b。与此相反，因为牺牲层130a可以覆盖用于第一位线的导电层120a，所以可以在湿法刻蚀工艺中保护用于第一位线的导电层120a。
参考图3F，可以选择性地去除牺牲层130a，以暴露用于第一位线的导电层120a。导电层120a可以是位线BL。
尽管未在附图中描绘，但是位线BL可以与图3A中的接触插塞CP电连接。
当在去除牺牲层130a之后用于第二位线的导电层120b可以部分地保留在绝缘中间层110的上表面以及沟槽t的侧表面上时，可以通过清洗工艺去除所保留的用于第二位线的导电层120b。尽管用于第一位线的导电层120a可以与用于第二位线的导电层120b一起被部分地去除，但是如上所述，用于位线的导电层120的厚度可以被设置为损失部分，使得电气特性的问题不会成为问题。
参考图3G，可以在沟槽t中形成间隙填充绝缘层140。因为沟槽t的高宽比可以通过位线BL的厚度来补偿，所以在间隙填充绝缘层140中不会生成空隙。间隙填充绝缘层140可以通过具有比PVD工艺的台阶覆盖率更好的台阶覆盖率的沉积工艺形成。例如，可以通过基本等于或大于用于形成牺牲层130的工艺来形成间隙填充绝缘层140。
图4A至图4G是示出根据示例性实施例的形成半导体器件的掩埋栅极的方法的横截面图。
参考图4A，可以制备半导体衬底200。
在示例性实施例中，半导体衬底200可以包括硅、单晶硅、多晶硅、非晶硅、硅锗、单晶硅锗、多晶硅锗、掺杂有碳的硅、它们的组合、它们的多层等。半导体衬底200可以包括诸如锗的半导体材料。半导体衬底200可以包括绝缘体上硅(SOI)衬底。可以在半导体衬底200的上区域中形成至少一个导电杂质区域210。
可以在半导体衬底200中形成沟槽T。可以考虑要在沟槽T中形成的晶体管的电气特性来设置沟槽T的深度和宽度。导电杂质区域210可以通过沟槽T被划分，以限定源极S和漏极D。从平面图看，沟槽T可以具有线性形状。
在形成沟槽T之后，可以在具有沟槽T的半导体衬底200的表面上共形地形成栅极绝缘层215。栅极绝缘层215可以包括氧化硅、氮化硅、氮氧化硅、高k材料、它们的组合等。例如，可以通过ALD工艺形成栅极绝缘层215。
可以在具有栅极绝缘层215的半导体衬底200上形成栅极金属层220。在示例性实施例中，可以通过诸如PVD工艺的第一沉积工艺形成栅极金属层220。栅极金属层220可以具有比栅极的设计厚度厚约1％至约20％的厚度。附图标记220a可以指的是形成在沟槽T的底部表面上的第一栅极金属层。附图标记220b可以指的是形成在半导体衬底200的上表面上和沟槽T的上侧表面上的第二栅极金属层。
参考图4B，可以在栅极金属层220上形成栅极牺牲层230。例如，栅极牺牲层230可以包括相对于栅极绝缘层215和栅极金属层220具有刻蚀选择性的材料。
栅极牺牲层230可以通过诸如CVD工艺的第二沉积工艺形成，该第二沉积工艺具有比第一沉积工艺的台阶覆盖率更好的台阶覆盖率。因此，可以沿着具有第一栅极金属层220a和第二栅极金属层220b的半导体衬底200的表面形成栅极牺牲层230。
参考图4C，可以对栅极牺牲层230进行回蚀，以暴露第二栅极金属层220b。栅极牺牲层230可以覆盖第一栅极金属层220a。附图标记230可以是被刻蚀的栅极牺牲层。
参考图4D，可以使用栅极牺牲层230作为掩模选择性地去除所暴露的第二栅极金属层220b。可以通过湿法刻蚀工艺去除第二栅极金属层220b。
参考图4E，可以选择性地去除沟槽T中的栅极牺牲层230。因为栅极牺牲层230可以相对于栅极绝缘层215和栅极金属层220具有刻蚀选择性，所以栅极绝缘层215和第一栅极金属层220a可以保护栅极牺牲层230免受用于对栅极牺牲层230进行刻蚀的刻蚀剂的影响。
如图4F所示，当在去除栅极牺牲层230之后第二栅极金属层220b可以部分地保留在沟槽T的侧表面上时，可以通过清洗工艺去除保留的第二栅极金属层220b。因此，第一栅极金属层220a可以保留在沟槽T的底部表面上。
参考图4G，可以在具有第一栅极金属层220a的沟槽T中形成栅极导电层240。栅极导电层240可以通过第三沉积工艺形成，该第三沉积工艺的台阶覆盖率和掩埋特性比第一沉积工艺的台阶覆盖率和掩埋特性更好。
栅极导电层240可以包括；掺杂有杂质的多晶硅层。栅极导电层240可以被凹陷以具有小于源极S的底部表面和漏极D的底部表面的厚度。因此，掩埋栅极G可以包括；顺序地堆叠的第一栅极金属层220a和凹陷的栅极导电层240。此外，可以在沟槽T中的掩埋栅极G上形成间隙填充绝缘层250。
根据示例性实施例，可以使用相对于特定方向具有高沉积速率的PVD工艺在沟槽的底部表面上选择性地形成导电线。此外，可以使用该工艺在接触孔的底部表面上选择性地形成导电图案，使得具有高的高宽比的沟槽或接触孔中的导电线或导电图案在无电气连接的情况下不会具有空隙或缝隙。
本教导的上述实施例旨在说明而不是限制本教导。各种替代和等同物是可能的。本教导不限于本文描述的实施例。本教导也不限于任何特定类型的半导体器件。考虑到本公开，增加、减少和/或修改是可能的，并且旨在落入所附权利要求的范围内。

Claims (19)

1.一种制造半导体器件的方法，所述方法包括：
提供绝缘中间层；
通过对所述绝缘中间层的选定部分进行刻蚀而在所述绝缘中间层中形成沟槽；
使用第一沉积工艺在所述绝缘中间层的上表面上以及所述沟槽的底部表面和侧表面上形成导电层，其中，形成在所述沟槽的底部表面上的所述导电层的厚度大于形成在所述沟槽的侧表面上的所述导电层的厚度；
使用与所述第一沉积工艺不同的第二沉积工艺在所述沟槽中形成牺牲层，以覆盖形成在所述沟槽的底部表面上的所述导电层；
选择性地去除通过所述牺牲层被暴露的、形成在所述绝缘中间层的所述上表面上的所述导电层以及形成在所述沟槽的所述侧表面上的所述导电层；以及
选择性地去除所述牺牲层，以使用保留在所述沟槽的所述底部表面上的所述导电层来形成导电线。
2.如权利要求1所述的方法，还包括：用材料层填充形成有所述导电线的所述沟槽。
3.如权利要求2所述的方法，其中，所述材料层包括：附加导电层和间隙填充绝缘层中的至少一者。
4.如权利要求1所述的方法，其中，所述第一沉积工艺是物理气相沉积工艺。
5.如权利要求1所述的方法，其中，形成所述牺牲层的步骤包括：
沿着在所述沟槽中和所述沟槽周围、形成在所述绝缘中间层上的所述导电层的表面共形地沉积所述牺牲层；以及
对所述牺牲层进行回蚀，以使在所述绝缘中间层的所述上表面上的所述导电层和在所述沟槽的侧表面上的所述导电层暴露。
6.如权利要求5所述的方法，其中，所述第二沉积工艺的台阶覆盖率比所述第一沉积工艺的台阶覆盖率更好。
7.如权利要求6所述的方法，其中，所述牺牲层通过化学气相沉积工艺、等离子体增强化学气相沉积工艺、原子层沉积工艺、以及等离子体增强原子层沉积工艺中的至少一者来形成。
8.如权利要求1所述的方法，其中，所述牺牲层包括：相对于所述绝缘中间层和所述导电层具有刻蚀选择性的材料。
9.如权利要求1所述的方法，还包括：去除所述牺牲层，其中，在去除所述牺牲层之后，形成在所述沟槽的侧表面上的所述导电层被去除。
10.如权利要求1所述的方法，其中，所述绝缘中间层包括多个接触插塞，
其中，当形成所述沟槽时，所述多个接触插塞中的至少一个接触插塞被暴露。
11.一种制造半导体器件的方法，所述方法包括：
提供包括第一孔的绝缘层，所述第一孔具有第一高宽比；
通过第一沉积工艺在所述绝缘层上形成导电层，所述第一沉积工艺在所述第一孔的侧表面上具有第一沉积速率以及在所述第一孔的底部表面上具有第二沉积速率，并且所述第二沉积速率高于所述第一沉积速率；
在所述第一孔中形成牺牲层以覆盖所述第一孔的所述底部表面上的所述导电层；
选择性地去除通过所述牺牲层暴露的、形成在所述第一孔的侧表面上的所述导电层；
去除所述牺牲层以限定第二孔，所述第二孔在所述第一孔中的所述导电层上，所述第二孔具有比所述第一高宽比小的第二高宽比；以及
在所述第二孔中形成间隙填充绝缘层。
12.如权利要求11所述的方法，其中，所述第一孔的平面形状具有线性形状或图案形状。
13.如权利要求11所述的方法，其中，形成所述牺牲层的步骤包括：
通过与所述第一沉积工艺不同的第二沉积工艺，沿着在所述第一孔中和所述第一孔周围的、形成在所述绝缘层上的所述导电层的表面形成所述牺牲层；以及
对所述牺牲层进行回蚀，以使在所述第一孔周围的、所述绝缘层的上表面上的所述导电层和在所述第一孔的侧表面上的所述导电层暴露。
14.如权利要求13所述的方法，其中，所述牺牲层通过化学气相沉积工艺、等离子体增强化学气相沉积工艺、原子层沉积工艺、以及等离子体增强原子层沉积工艺中的至少一者来形成。
15.如权利要求11所述的方法，还包括：去除所述牺牲层，其中，在去除所述牺牲层之后，形成在所述第一孔的侧表面上的所述导电层被去除。
16.如权利要求11所述的方法，还包括：在所述第二孔的底部处的所述导电层上形成附加导电层，以及然后在所述附加导电层之上、所述第二孔中形成所述间隙填充绝缘层。
17.如权利要求16所述的方法，其中，所述导电层包括以下各者中的至少一者：具有至少一种金属元素的金属层；具有至少一种金属元素和氮元素的金属氮化物层；具有至少一种金属元素、氮元素、以及氧元素的金属氮氧化物层；具有至少一种金属元素和硅元素的金属硅化物；以及包括导电杂质的掺杂多晶硅层；以及
所述附加导电层包括多晶硅层，所述多晶硅层包括所述导电杂质。
18.一种制造半导体器件的方法，所述方法包括：
提供包括杂质区域的半导体衬底；
对所述半导体衬底进行刻蚀以形成沟槽；
在所述沟槽的表面以及所述半导体衬底的上表面上形成栅极绝缘层；
通过第一沉积工艺在所述栅极绝缘层上形成第一栅极导电层，所述第一沉积工艺在与所述半导体衬底的所述上表面基本平行的部分上具有第一沉积速率以及在与所述半导体衬底的所述上表面基本垂直的部分上具有第二沉积速率，其中所述第二沉积速率高于所述第一沉积速率；
在所述沟槽中形成牺牲层，以使在所述半导体衬底的所述上表面上的所述第一栅极导电层和在所述沟槽的侧表面上的所述第一栅极导电层暴露；
选择性地去除通过所述牺牲层暴露的所述第一栅极导电层；以及
去除所述牺牲层，以使用保留在所述沟槽中的所述第一栅极导电层形成掩埋栅极。
19.如权利要求18所述的方法，其中，形成所述掩埋栅极的步骤包括：在所述第一栅极导电层上形成第二栅极导电层，其中，所述第二栅极导电层包括与所述第一栅极导电层的材料不同的材料。
CN202310238399.6A 2022-09-02 2023-03-10 制造包括导电线的半导体器件的方法 Pending CN117650098A (zh)

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