CN1175030A - 带有用于地址比较的－2减法器的列地址计数器 - Google Patents

带有用于地址比较的－2减法器的列地址计数器 Download PDF

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Publication number
CN1175030A
CN1175030A CN97117156A CN97117156A CN1175030A CN 1175030 A CN1175030 A CN 1175030A CN 97117156 A CN97117156 A CN 97117156A CN 97117156 A CN97117156 A CN 97117156A CN 1175030 A CN1175030 A CN 1175030A
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CN
China
Prior art keywords
address
circuit
counter
sequence
train
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN97117156A
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English (en)
Chinese (zh)
Inventor
伊藤和弥
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of CN1175030A publication Critical patent/CN1175030A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0879—Burst mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
CN97117156A 1996-07-19 1997-07-18 带有用于地址比较的－2减法器的列地址计数器 Pending CN1175030A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US2220496P 1996-07-19 1996-07-19
US022,204 1996-07-19

Publications (1)

Publication Number Publication Date
CN1175030A true CN1175030A (zh) 1998-03-04

Family

ID=21808370

Family Applications (1)

Application Number Title Priority Date Filing Date
CN97117156A Pending CN1175030A (zh) 1996-07-19 1997-07-18 带有用于地址比较的－2减法器的列地址计数器

Country Status (5)

Country Link
JP (1) JP3855002B2 (ko)
KR (1) KR980010696A (ko)
CN (1) CN1175030A (ko)
SG (1) SG82574A1 (ko)
TW (1) TW341675B (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002245779A (ja) * 2001-02-20 2002-08-30 Nec Microsystems Ltd 半導体記憶装置
KR20210074629A (ko) 2019-12-12 2021-06-22 주식회사 메타씨앤아이 메모리 장치에서 통합 카운터

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208782A (en) * 1989-02-09 1993-05-04 Hitachi, Ltd. Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement
US5506810A (en) * 1994-08-16 1996-04-09 Cirrus Logic, Inc. Dual bank memory and systems using the same
JP3141115B2 (ja) * 1994-12-23 2001-03-05 マイクロン・テクノロジー・インコーポレイテッド バーストｅｄｏメモリ装置アドレス・カウンタ

Also Published As

Publication number Publication date
JP3855002B2 (ja) 2006-12-06
JPH10177789A (ja) 1998-06-30
TW341675B (en) 1998-10-01
SG82574A1 (en) 2001-08-21
KR980010696A (ko) 1998-04-30

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C01 Deemed withdrawal of patent application (patent law 1993)
WD01 Invention patent application deemed withdrawn after publication