CN1175030A - Column address counter with 2 subtracter used for address compare - Google Patents
Column address counter with 2 subtracter used for address compare Download PDFInfo
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- CN1175030A CN1175030A CN97117156A CN97117156A CN1175030A CN 1175030 A CN1175030 A CN 1175030A CN 97117156 A CN97117156 A CN 97117156A CN 97117156 A CN97117156 A CN 97117156A CN 1175030 A CN1175030 A CN 1175030A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0879—Burst mode
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
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Abstract
A method and apparatus provide a burst address counter transmitting instantly a burst finish signal. In one of the prime example the synchronous storage comprises a counter driving a burst finish sequence by the output address. The counter drives a burst finish signal indicating finish of burst sequence. The counter comprises address registers, an adder, a minus 2 subtracter, and a comparator. The comparator can decide finish of burst sequence more quickly than a conventional counter by the minus 2 subtracter. Because, the minus 2 subtracter can decide an address one before the last of sequence, thereby, the comparator can transmit a burst finish signal at earlier point of time.
Description
Present invention generally relates to the semiconductor design technology, relate to more precisely and be used for showing a kind of method and apparatus that the counter sequence has finished.
Speed and sequential restriction are the significant considerations in the electronic system design always.The sequential that the most systems design must be satisfied employed whole elements requires and the optimization constantly in order to obtain high speed.Consequently many integrated circuit i.e. " chip " have adopted Synchronization Design.Synchronization Design is the design that a kind of chip component is connected to a synergic system clock (CLK).Synchronizing chip has latch, the register sum counter that is connected in input and output, all on a single monolithic chip.And synchronizing chip provides a lot of benefits for system designer, for example the travelling speed of external logic chip still less and Geng Gao.
An example of synchronizing chip is the Synchronous Dynamic Random Access Memory (SDRAM) that has address counter on the plate.With can carry out read or the processor of train of impulses write operation use usually by train of impulses for address counter.The train of impulses operation is a kind of method that a series of data is sent to another device from a device.For example, when processor started a train of impulses read operation to SDRAM, it provided a base address to read first memory of data position among the SDRAM to indicate.Processor then goes to read one or more memory location among the SDRAM in proper order according to predetermined train of impulses.
Because the train of impulses order has been scheduled, thus in case first memory location is accessed, so and the separated counter of processor be used to the memory location of expecting that the next one will be visited.Like this, because counter can produce the address of the memory location that the next one will visit apace, and can begin next memory location is conducted interviews as soon as possible, so improved the work of SDRAM.
When the travelling speed of processor is a frequency when improving, the corresponding rate request of address counter is also improved.Therefore, for improvement work, address counter be incorporated into SDRAM originally on one's body, thereby reduce any propagation delay that discrete counter and SDRAM cause.But as described below, processor frequencies improves constantly, causes simply the time requirement of settling conventional counter to be not enough to satisfy the strictness of many modern processors in SDRAM.
Fig. 1 is the block scheme of conventional counter, represents with reference number 10 usually.Counter 10 is combined in the SDRAM (not shown).The external address that counter 10 receives from outer address bus XADD.Obviously, be well-known in the art a memory device being applied an address, so seldom give unnecessary details.
The purpose of counter 10 is according to external address, and by predetermined train of impulses order, bus IADD in location goes up and produces home address inwardly.Though train of impulses can have a lot of different length, such as 1,2,4,8 or 16 address location, the typical pulse string of two address A1:A0 of 32 bit address A31:A0 is in proper order:
| ?A31：??A2 | ????A1 | ????A0 |
| ?A31：??A2 | ????A1 | ????A0 |
| ?A31：??A2 | ????A1 | ????A0 |
| ?A31：??A2 | ????A1 | ????A0 |
(note: symbol " " represent anti-phase address) above-mentioned typical pulse string order will be used for remaining and describe.But obviously, also can use other train of impulses order and length.In addition, the purpose of counter 10 is to produce a train of impulses termination signal WRAPDN, has finished to show burst sequence.The WRAPDN signal also must satisfy setting and the retention time that some processor is determined.
At work, the LOAD signal makes the external address on the outer address bus XADD can be loaded into address register 12,14,16.External address on the address register 16 driving internal address bus IADD is as first address of predetermined pulse string order.
The intermediate address A1 that address register 14 will equal external address is driven into subtracter 18.Subtracter 18 deducts 1 from middle address A1, to produce an intermediate address A2 who equals the 3rd home address of above-mentioned predetermined pulse string order.
Simultaneously, address register 12 drives an intermediate address A3 who equals external address at the beginning to incrementer 20.Incrementer 20 adds 1 for intermediate address A3, to produce an intermediate address A4 who equals the first train of impulses address of above-mentioned predetermined pulse string order.Intermediate address A4 is fed into burst sequence generator 24, and it produces an intermediate address A5 in proper order according to predetermined train of impulses.Intermediate address A5 is fed into address register 16 then.Thereby address register 16 is updated to the home address on the internal address bus IADD next address of predetermined pulse string order.
Intermediate address A4 also is returned to address register 12, the location so that the calculating next pulse is ploughed.And intermediate address A4 is fed into comparer 22, and it compares with intermediate address A2 therein.Like this, in case intermediate address A4 equals the 3rd train of impulses address (it is the FA final address of predetermined pulse string order), comparer 22 just can be concluded the WRAPDN signal.
Fig. 2 is the sequential chart of the conventional counter circuit of Fig. 1.External address, the first train of impulses address, the second train of impulses address and the 3rd train of impulses address are represented with reference number B0, B1, B2 and B3 respectively.
The waveform of WRAPDN signal particularly importantly.The WRAPDN signal produces at times 32 place that is decided by propagation delay 33.Propagation delay 33 is that first delay 34 and second postpones 36 sums.First propagation delay that postpones 34 incrementers 20 when ploughing location B3 by driving pulse causes.Incrementer 20 drives the train of impulses address B3 on the intermediate address A4 after intermediate address A3 equals train of impulses address B2.Second delay 36 is the delays by the caused rising of propagation of passing through comparer 22.
Equally, the WRAPDN signal disappears at times 38 place that is decided by propagation delay 39.Propagation delay 39 equals delay 42 sums of retention time delay 40 with the caused decline of propagation of passing through comparer 22 of incrementer 20.
The sequence problem that postpones the conventional counter 10 of 33 and 39 generations.For the purpose of for example, the frequency of clock signal clk is 100MHz, and the period T that it provides is 10ns.The typical time of delay 34 is 8ns, and postpones 36 the 2ns that is.Consequently, for determining that the delay 33 that the WRAPDN signal is accumulated is 10ns (8ns+2ns), i.e. 1 clock period.Such delay is oversize for the time requirement that is provided with of satisfying many conventional processors.Consequently, when waiting WRAPDN signal to be determined, wasted 1 clock period.If determine the clock period that the WRAPDN signal is wasted with saving as early as possible, when being favourable.
Thereby the present invention is a kind of Method and circuits that is used to provide the train of impulses address counter that has the signal of having finished train of impulses fast.In a most preferred embodiment, synchronous memory device comprises a counter that is used for producing according to external address the train of impulses address sequence.In addition, counter drives the signal finished train of impulses and shows and finish burst sequence.This counter comprises that a register that is used for receiving external address, one are used for making external address to increase progressively-2 subtracters and a comparer that incrementer with the next address that produces the train of impulses address sequence, one are used for determining the penult train of impulses address of burst sequence.
Utilize-2 subtracters, the comparable conventional counter of comparer is earlier determined the terminal point of burst sequence.This is because-2 subtracters are determined the penult address of sequence, makes comparer can earlier begin to determine to have finished the signal of train of impulses.
The technological merit that the present invention reached is to have determined the completed signal of train of impulses as early as possible, so that can satisfy the time requirement of high speed processor.
Fig. 1 is the block scheme of conventional counter.
Fig. 2 is the sequential chart of the conventional counter of Fig. 1.
Fig. 3 is the block scheme that embodies 64 megabit SDRAM of characteristics of the present invention.
Fig. 4 be used for Fig. 3 64 megabit SDRAM improvement the block scheme of counter.
Fig. 5 be Fig. 4 improvement the sequential chart of counter, show characteristics of the present invention.
As mentioned above, Fig. 1 and 2 shows conventional counter and relevant sequential chart.
With reference to Fig. 3, synchronous memory device that embodies characteristics of the present invention of reference number 100 expressions.Though in most preferred embodiment of the present invention, device 100 is Synchronous Dynamic Random Access Memories (SDRAM) of one 64 megabit, but obviously, the present invention is not limited to and uses SDRAM, and can and adopt the circuit devcie of counter to use together with any high-speed cruising.
Device 100 receives outside positive supply (V by input solder joint 102 and 104 respectively
DD) and outside negative supply (V
Ss).Device 100 transmits and receives data input-outputs (I/O) by I/O solder joint 106a, 106b, 106c and 106d.And device 100 comprises common a plurality of input buffers, output buffer and other circuit of representing with I/O circuit bank 108.I/O circuit bank 108 and input solder joint 106a-106d are conventional to most of SDRAM, so seldom describe in detail.
Device 100 receives external address by address pads 110a, 110b, 110c and 110d, and by solder joint 112a, 112b, 112c, 112d, 112e and 112f respectively control signal RAS, CAS, CLK, CKE, WE and DQM.Signal RAS, CAS, CLK, CKE, WE and DQM in each all be conventional, and wherein some is used to drive internal signal LOAD and COUNTUP.As above described with reference to Fig. 1, LOAD and COUNTUP signal also are conventional internal signals.Device 100 also drives an internal control signal WRAPDN '.In most preferred embodiment, can have more address and control signal solder joint, but their function can be represented with solder joint 110a-110d and 112a-112f.
Device 100 also comprises common a plurality of address buffers and the code translator of representing with address buffer pool 114, row address decoder group 116 and column address decoder group 118.Address buffer group 114 and code translator group 116 and the 118 couples of most of DRAM and SDRAM are conventional, so seldom describe in detail.
Device 100 contains the individual storage unit of 64,000,000 (1,000,000 equal 1,048,576).Storage unit is divided into 4 equal-sized group 120,122,124,126, and a upper and lower of representing with subscript u and l is respectively respectively arranged.Storage unit is conventional, and adopts many different signal wires, amplifier circuit and decoder circuit.Because it is conventional storage unit that group 120-126 contains most of 64 megabit DRAM, so few its function that describes in detail.
Device 100 contains a counter 130.Counter 130 is improvement of conventional counter 10 (Fig. 1); Therefore, will the representing with identical reference number of the counter 130 that has improved with conventional counter 10 identical circuit and signal, and any change, revised or the circuit and the signal of improved will be represented with new reference number.
Counter 130 is connected in address buffer 114 by outer address bus XADD.Equally, counter 130 is connected in column decoder 118 by internal address bus IADD.Counter 1 30 also is connected to power supply V
DDAnd V
Ss
Counter 130 receives from the external address of outer address bus XADD and outside and internal control signal CLK, LOAD and COUNTUP as input.The home address that counter 130 drives on the internal address bus IADD that simulates the predetermined pulse string sequence.Though train of impulses can be multiple different length, such as 1,2,4,8 or 16 address location, for example, the predetermined pulse string sequence is:
| ?A31：??A2 | ????A1 | ????A0 |
| ?A31：??A2 | ????A1 | ????A0 |
| ?A31：??A2 | ????A1 | ????A0 |
| ?A31：??A2 | ????A1 | ????A0 |
With reference to Fig. 4, counter 130 comprises 12,14,16, incrementers of three address registers 20, a comparer 22 and a burst sequence generator 24.In these circuit each is the circuit in the conventional counter 10 that is used in Fig. 1 all.In the register 12,14,16 each is all by drive and the K signal Synchronization that derive from three control signal LOAD, CLK and COUNTUP by clock circuit 26.
Counter 130 also comprises one-2 subtracter 138.-2 subtracters 138 are used to determine the penult address of predetermined pulse string sequence.Adopt above-mentioned predetermined pulse string sequence, can only reverse the simply address wire (A1) of an external address of-2 subtracters 138.
At work, the LOAD signal makes the external address from outer address bus XADD can be written into address register 12,14,16.External address on the address register 16 driving internal address bus IADD is as first address of predetermined pulse string sequence.
Simultaneously, address register 12 drives an intermediate address A3 who equals external address at the beginning to incrementer 20.Incrementer 20 adds 1 with intermediate address A3 and equals the intermediate address A4 of the first train of impulses address of above-mentioned predetermined pulse string sequence with generation.Intermediate address A4 is fed into burst sequence generator 24, produces intermediate address A5.Intermediate address A5 then is fed into address register 16 to drive the home address on the internal address bus IADD.Address register 16 upgrades home address.Intermediate address A4 also is sent back to address register 12 so that calculate the next pulse location of ploughing.
Intermediate address A3 also is fed into comparer 22, compares with intermediate address A2 ' therein.Like this, in case intermediate address A3 equals the second train of impulses address, comparer 22 just can begin to determine WRAPDN ' signal.
With reference to Fig. 5, external address, the first train of impulses address, the second train of impulses address and the 3rd train of impulses address are represented with reference number B0, B1, B2 and B3 respectively.The waveform of WRAPDN ' signal particularly importantly.WRAPDN ' signal of Fig. 5 is the improvement to the WRAPDN signal of Fig. 2.WRAPDN ' signal produces at 36 determined times 140 of the delay place by comparer 22 caused risings when in a single day middle address A2 equals the second train of impulses address B2.Equally, the WRAPDN signal disappears at 42 determined times 142 of the delay place by comparer 22 caused declines when in a single day middle address A2 equals the 3rd train of impulses address B3.
For benefit of the present invention is described, the same time example that is used for conventional Fig. 2 is added on Fig. 5.The frequency of clock signal clk is 100MHz, and period T is 10ns.The typical time of delay 36 is 2ns.But it is to be noted, do not exist as conventional counter 10 and postpone 34 from the B3 that plough from middle address A3 generation pulse.Consequently, WRAPDN ' signal of the present invention is than the early definite 8ns of the WRAPDN signal of conventional Fig. 2.
Though described exemplary embodiment of the present invention, can make modification, change and replace foregoing disclose, and in some cases, some characteristic of the present invention can be used and other characteristics need not be correspondingly adopted.And, extra impact damper, driver, delay circuit and other circuit can be added exemplary embodiment and do not change scope of the present invention.Therefore, obviously claims broadly and with scope of the present invention are as one man set up.
Fig. 6 is a sequential chart, shows based on the train of impulses operational example of the burst sequence of characteristics of the present invention such as the sequential chart of train of impulses read operation.After first address is chosen, can in pulse string mode, wait for by the burst length and the CAS in 2 cycles with 8 cycles, obtain continuous 8 bit data.Fig. 7 shows each constituent element of finishing the train of impulses read operation.
Fig. 7 shows a plurality of storage unit that are arranged in matrix at word line and bit line infall; Sensor amplifier SA corresponding to storage unit MC; The a pair of selection MOS transistor ST that sensor amplifier SA is connected in the I/O line; Main amplifier MA who is connected in the I/O line and one are used for latching and export the output latch circuit OL of the output of main amplifier MA.Each is connected in the column decoder CD of reception from the column address of column counter CC to selecting MOS transistor ST by the YS line.
After the output latch circuit OL that offers public I/O line will get up by the data latching that bit line, sensor amplifier SA, I/O line and main amplifier MA read from storage unit MC, as long as by means of disconnecting the I/O line, just may carry out such as the I/O line that has heavy load electric capacity being carried out other operation that precharge is taken out latched data simultaneously from output latch circuit OL.
Column counter CC shown in Figure 7 and column decoder CD are equivalent to counter 130 and the column decoder 118 of Fig. 3 respectively.Storage unit MC, sensor amplifier SA and selection MOS transistor ST can be included in the group 120,122,124,126, and main amplifier MA and output latch circuit OL can be included in the I/O circuit 108.
In the train of impulses read operation, shown in the sequential chart of Fig. 6, in the synchronous mode of operation that adopts clock CLK, the order and the address at place, storage array receive clock CLK forward position.According to activating (ACTV) order, storage array receives row address (RA) to select corresponding word line.The cell signal of reading in bit line (is 8 bit lines in this situation) is read out amplifier SA and amplifies.According to two cycles after the activation command send read (READ) order, storage array receives column address (CA), by means of a pair of selection MOS transistor ST, read line from the signal that corresponding bit line will amplify, and output to external circuit with signal that clock CLK synchronously will amplify to I/O.
At this moment, column counter CC can produce the address of next storage unit MC to be visited immediately.Therefore, when column address is specified by column counter CC, corresponding to the YS line of the column address (CA to CA+7) of designated address by selected and select MOS transistor ST to be driven in succession, thereby 8 signals are outputed to the I/O line continuously from corresponding 8 bit lines.This output (MO1-MO8) is output latch cicuit OL and latchs after being amplified by main amplifier MA, synchronously data (OUT1-OUT8) is outputed to external circuit with clock CLK then.
Following the carrying out of data output in this train of impulses read operation.After receiving row address according to activation command, receive column address according to read command, when receiving after the column address 2 cycles, synchronously be output according to priority from data and the clock CLK of OUT1-OUT8, so in 8 cycles, export all data in succession from OUT1-OUT8.
Herein we to have described burst length be that 8 cycles and CAS wait for being 2 operations under the cycle situation.CAS wait for be the data output function in 3 cycles except the number of cycles difference of output from the address specification to data, also comprise identical built-in function.For other burst length, also can with such as 1,2,4 or whole periodicities export data continuously such as 2,4,16,256 or 1024 required figure place.
Fig. 8 shows the address register 12 of the counter 130 that for example is included in Fig. 4 and the carry generation circuit in the totalizer 20.
Carry generation circuit for example is a column address (CA)=(Y9, Y8, Y0) 10 bit parallel totalizers, it have one by means of the totalling of carrying out each digital addend and summand with seek part and, simultaneously independently all numerals are carried out carry computation, then will part and with the carry digit addition, with the adder circuit structure of the pre-lock of secondary carry that improves addition speed.
This carry generation circuit comprise 10 be used for calculating section and control register CTR0-CTR9 and one comprise the gate circuit of NAND door, NOR door and be connected in the input stage of these control registers and all numerals carried out the phase inverter of carry computation.Carry generation circuit is designed to make the carry output (C) from the control register of low-order digit to be reflected in the carry input (CR) of all control registers of high-order digit more.Produce 10 bit data (Y0-Y9) from the output (S) of control register CTR0-CTR9 corresponding to intermediate address A4 shown in Figure 4.
For example, the input of the carry of 0 control register CTR0 is fixed in noble potential, and its carry output is taken into the carry input of 1 control register CTR1.Simultaneously, the output of the carry of control register CTR0 also is taken into a carry input of the 2 input NAND doors that are connected in 2 control register CTR2, and is taken into a carry input of the three input NAND doors that are connected in 3 control register CTR3.The output of these NAND doors is fed into 2 and 3 s' control register CTR2, CTR3 by phase inverter.
4 to 6 control register CTR4-CTR6 and the input of the carry of low-order bit, respectively by phase inverter and 2 input NOR doors, by 2 input NAND doors and 2 input NOR doors and by 3 input NAND doors and 2 input NOR doors, be fed into the control register of higher-order bits.Equally, for 7 to 9 control register CTR7-CTR9, the carry input can be imported the NOR doors, import the NOR doors and be taken into control register by 3 input NAND doors and 3 input NOR doors by 2 input NAND doors and 3 by phase inverter and 3 respectively.
Except importing (CR) signal, control register CTR0-CTR9 also receives control signal and the address signal such as CPU, CASP and INTEL, and these signals are all not shown.Fig. 9 of the internal logic structure of the details of these signals reference explanation after a while control register CTR0-CTR9 describes.
As shown in Figure 9, the control register of Fig. 8 each all can constitute a so-called binary scaler that comprises the feedback circuit form of the logic gate such as a plurality of clock phase inverter CIV1-CIV4, a plurality of phase inverter IV1-IV4 and NAND door and transmit CMOS transistor T T.Clock phase inverter CIV1-CIV4 and phase inverter IV1-IV4 are made of the combination of CMOS transistor or PMOS transistor AND gate nmos pass transistor.These all are to use routinely so do not add to explain.
In these control registers each all comprise a suspension control signal CPU, the clock phase inverter CIV1 of CPU control and receiving feedback signals; A transmission CMOS transistor T T who is connected in clock phase inverter CIV1 and its grid suspension control signal CUP control via phase inverter IV1; One via phase inverter IV2 be connected in transmit CMOS transistor T T and suspension control signal CR, the clock phase inverter CIV2 of CR control; And suspension control signal CR, a CR in parallel with phase inverter IV2 and clock phase inverter CIV2 the clock phase inverter CIV3 of control; One be connected in the connected node that transmits between CMOS transistor T T and the phase inverter IV2 and suspension control signal CASP, the clock phase inverter CIV4 of CASP control; And one be connected in clock phase inverter CIV4 and feedback with the NAND door of address signal ADD and control signal INTEL.Phase inverter IV1, IV2 are connected to phase inverter IV3, the IV4 that inverse parallel connects statically, so that keep electric charge by means of floating of clock phase inverter.
Control register receives following control signal.Control signal CUP, CUP be COUNTUP signal and the reversed phase signal thereof of Fig. 5; Control signal CR, CR be signal and reversed phase signal thereof by lower-order position control register carry; Control signal CASP, CASP be LOAD signal and the reversed phase signal thereof of Fig. 5; And control signal INTEL is the control signal that is used for changing pulse string mode.Address signal ADD is corresponding to the external address by outer address bus XADD input shown in Figure 5.
The work of control register is as follows.At first, in the initial setting of address, control register is fed to the address signal ADD of NAND door with reception according to CASP signal controlling clock phase inverter CIV4.This address is first address of burst sequence.Second address of the back of first address is by means of producing to amount to first address with CUP signal controlling clock phase inverter CIV1 and transmission CMOS transistor T T.In this way, amounted to the next address of burst sequence before the address is fed continuously in the loop.
When the address was amounted to the FA final address of burst sequence, the CUP signal was terminated.That is the M signal of burst sequence generator is fed into the comparer 22 of Fig. 4, and when it became the final pulse address that equals the predetermined pulse sequence, comparer 22 produced a WRAPDN ' signal that is used for stopping amounting to burst sequence.
When control register for example received a high level carry signal CR from lower-order position control register, control register was with the carry signal CR paraphase that receives and because control register outputs to the higher-order bits control register by the 3 grades of phase inverter work that comprises clock phase inverter CIV1, phase inverter IV1 and clock phase inverter CIV3 with the signal of paraphase 3.When control register received a low level carry signal CR, it was by comprising 4 grades of phase inverter work of clock phase inverter CIV1, phase inverter IV1, phase inverter IV2 and clock phase inverter CIV2, thereby carry signal is outputed to the higher-order bits control register.
As mentioned above, the exportable data Y 0 (Y1-Y9) corresponding to everybody of each control register also will be reflected on all higher-order bits control registers from the carry signal of lower-order position control register as a burst sequence address.
This is in the pulse train, and delay is a key issue.The address register 12 in the counter 130 of Fig. 4 and the logical organization of totalizer 20 have been described in detail.Address register 14 and-2 subtracters 138 also have the carry generation circuit shown in Fig. 8 and 9, and have similar substantially logical organization, so no longer describe in detail.
Claims (22)
1. one kind is used for producing the train of impulses address sequence and producing the train of impulses counter that signal finished with the marker pulse string sequence that finished from external address, and this counter comprises:
A register that is used for receiving external address;
One is used for increasing progressively first circuit of external address with the next address of generation train of impulses address sequence;
A second circuit that is used for determining the penult train of impulses address of train of impulses address sequence;
One is used for determining whether next address equals the penult address and determine corresponding to finished the tertiary circuit of signal of its train of impulses.
2. counter as claimed in claim 1, first circuit wherein are incrementer circuit.
3. counter as claimed in claim 1, second circuit wherein are one-2 subtraction circuits.
4. counter as claimed in claim 1, tertiary circuit wherein are comparers.
5. counter as claimed in claim 1, first circuit wherein comprises a burst sequence generator, makes the train of impulses address sequence able to programme.
6. synchronous memory device, it comprises a plurality of memory cell arrangements, a plurality of address pads that is used for receiving external address and one and is used for producing according to predetermined sequence the counter of a plurality of home addresses, and this counter comprises:
One is used for advancing first circuit of external address with the next address of generation predetermined sequence;
A second circuit that is used for determining the penult address of this sequence;
One is used for determining whether next address equals the penult address and determine corresponding to finished the tertiary circuit of signal of its train of impulses.
7. synchronous memory device as claimed in claim 6, wherein first circuit of counter is an incrementer circuit.
8. synchronous memory device as claimed in claim 6, wherein the second circuit of counter is one-2 subtraction circuit.
9. synchronous memory device as claimed in claim 6, wherein the tertiary circuit of counter is a comparer.
10. the synchronous memory device of claim 6, wherein first circuit of counter comprises a burst sequence generator, makes the train of impulses address sequence able to programme.
11. a method that is used to provide based on the train of impulses address sequence of external address, the method comprises the following step:
(a) receive external address in register;
(b) address that will receive in the register is fed to sequence generation circuit;
(c) to being fed to the address serialization of sequence generation circuit, to produce the next address of sequence;
(d) receive next address in register;
(e) will receive in the register the address be used for determining that the reference address when sequence finishes compares.
12. the method for claim 11 also comprises the following step:
If sequence do not finish as yet, then repeating step (b), (c), (d) and (e);
If sequence finishes, then establish the train of impulses signal that finished.
13. the method for claim 11 also comprises following step:
(f) address that will receive in the register is driven into a memory circuitry.
14. the method for claim 11, reference address wherein is decided by external address.
15. the method for claim 11, reference address wherein are decided by to deduct 2 from external address.
16. the method for claim 11, reference address wherein are decided by the paraphase part of external address.
17. the method for claim 11, ordering is wherein finished by incrementer.
18. the method for claim 11, ordering wherein may be programmed to different burst sequences.
19. a semiconductor memory, it comprises:
One comprise a plurality of bit lines to, a plurality of and bit line be to the word line that intersects, a plurality of storage unit and a plurality of memory array that is connected in the right sense amplifier circuit of bit line;
It is right to be used for a right common data line of a plurality of bit lines;
One optionally with the predetermined bit line of a plurality of bit line pairs to being connected in the right on-off circuit of common data line;
The adder circuit of an output continuation address;
One will remain the address holding circuit of the Input Address of adder circuit from the OPADD of adder circuit;
First address according to continuation address forms the subtraction circuit of an address before, last address of continuation address;
The comparator circuit of the Input Address of a reception adder circuit and the OPADD of subtraction circuit; And
Control circuit according to continuation address gauge tap circuit;
Wherein the work of adder circuit is stopped by the consistance detectable signal from comparator circuit.
20. according to the semiconductor memory of claim 19, subtraction circuit wherein is one and deducts 2 circuit from first address.
21. according to the semiconductor memory of claim 20, first address wherein is an external address, and the initial value of address holding circuit is this first address.
22. the semiconductor memory according to claim 21 also comprises:
One produces the internal clocking generation circuit of internal clock signal according to external timing signal, and wherein adder circuit and internal clock signal are synchronously worked.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US2220496P | 1996-07-19 | 1996-07-19 | |
| US022,204 | 1996-07-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1175030A true CN1175030A (en) | 1998-03-04 |
Family
ID=21808370
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97117156A Pending CN1175030A (en) | 1996-07-19 | 1997-07-18 | Column address counter with 2 subtracter used for address compare |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JP3855002B2 (en) |
| KR (1) | KR980010696A (en) |
| CN (1) | CN1175030A (en) |
| SG (1) | SG82574A1 (en) |
| TW (1) | TW341675B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002245779A (en) * | 2001-02-20 | 2002-08-30 | Nec Microsystems Ltd | Semiconductor memory |
| KR20210074629A (en) | 2019-12-12 | 2021-06-22 | 주식회사 메타씨앤아이 | Combined counter in memory device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5208782A (en) * | 1989-02-09 | 1993-05-04 | Hitachi, Ltd. | Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement |
| US5506810A (en) * | 1994-08-16 | 1996-04-09 | Cirrus Logic, Inc. | Dual bank memory and systems using the same |
| JP3141115B2 (en) * | 1994-12-23 | 2001-03-05 | マイクロン・テクノロジー・インコーポレイテッド | Burst EDO memory device address counter |
-
1997
- 1997-05-23 JP JP13384297A patent/JP3855002B2/en not_active Expired - Fee Related
- 1997-07-01 TW TW086109276A patent/TW341675B/en active
- 1997-07-14 KR KR1019970032604A patent/KR980010696A/en not_active Application Discontinuation
- 1997-07-15 SG SG9702380A patent/SG82574A1/en unknown
- 1997-07-18 CN CN97117156A patent/CN1175030A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JP3855002B2 (en) | 2006-12-06 |
| JPH10177789A (en) | 1998-06-30 |
| TW341675B (en) | 1998-10-01 |
| SG82574A1 (en) | 2001-08-21 |
| KR980010696A (en) | 1998-04-30 |
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