CN117374000A - 一种高性能整流管芯片的制作工艺 - Google Patents
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 48
- 239000010703 silicon Substances 0.000 claims abstract description 48
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- 238000003486 chemical etching Methods 0.000 claims abstract description 20
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- 239000011521 glass Substances 0.000 claims description 12
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- 238000005245 sintering Methods 0.000 claims description 2
- 239000002253 acid Substances 0.000 abstract description 6
- 238000002791 soaking Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 2
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- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 4
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 210000003323 beak Anatomy 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000003698 laser cutting Methods 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
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- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
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- 239000011863 silicon-based powder Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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Abstract
一种高性能整流管芯片的制作工艺,属于半导体技术领域。该芯片在制备过程中,所采用的开沟处理方法包括:将需要开沟处理的硅片在清洗后,先用激光切割,形成初步加工沟槽;然后,使用切割刀片在初步沟槽的基础上进行切割,形成深度加工沟槽;最后,对深度加工沟槽进行化学蚀刻,蚀刻时间3‑6min,形成所需的有效沟槽。本发明改变了现有普通整流管芯片的制备方法,由原来的直接采用浸泡混酸的化学蚀刻开沟方式,变为先通过物理方式开沟,再用化学方式进一步加工的方法,缩短了化学蚀刻开沟时间,改善了沟槽形貌,提高了芯片性能。
Description
技术领域
本发明涉及一种高性能整流管芯片的制作工艺,属于半导体技术领域。
背景技术
通常,普通整流管芯片(standardRectifierChip,STD)的制备方法包括:将硅片依序进行表面处理、磷扩、分片、单片减薄处理、硼扩、分片、表面处理、开沟、玻烧、金属化等,最后进行切割包装。
但是,现有的普通整流管芯片制备过程中,所采用的开沟处理方法一般是通过硅与酸发生化学反应(即化学蚀刻)来形成沟槽,此过程时间较长,大约为15min左右完成开沟。
如图1所示,化学反应后所形成的沟槽,沟槽横截面为弧形,由于在化学蚀刻之前,会在硅片表面、无需开沟区域涂覆保护胶,使硅片表面无需开沟区域不参与化学反应,所以沟槽槽顶的两侧边缘会形成鸟嘴状结构5,化学反应时间越长,沟槽槽顶两侧的形状越不规则,鸟嘴状结构就更加凸出,会造成沟槽内玻璃层厚度有差异,可能引起鸟嘴尖角放电。
发明内容
本发明的目的是针对上述现有技术的不足,提供一种高性能整流管芯片的制作工艺,以改进现有化学蚀刻的开沟处理方法,缩短开沟时间,改善沟槽形貌,提高芯片性能,保证芯片质量。
本发明的技术方案如下:
一种高性能整流管芯片的制作工艺,其特征是,该芯片在制备过程中,所采用的开沟处理方法包括:
将需要开沟处理的硅片在清洗后,先用激光切割,形成初步加工沟槽,沟槽的深度在15-20μm;
然后,使用切割刀片在初步沟槽的基础上进行切割,切割刀片的宽度为100μm,形成深度加工沟槽,深度加工沟槽的宽度为100μm、深度为70μm;
最后,对深度加工沟槽进行化学蚀刻,将硅片浸泡混酸处理,蚀刻时间3-6min,温度-5—-10℃,形成所需的有效沟槽。
上述方案中,改变原有开沟处理时只采用化学蚀刻的方法,创新性地采用先激光切割、再刀片切割、最后化学蚀刻的组合式开沟处理方法,缩短了开沟时间,改善了沟槽形貌。先用激光切割,形成初步加工沟槽,便于引导后续步骤中刀片进入开沟区域,能够大大减少刀片切割可能产生的应力破坏,不容易破片;采用刀片切割,便于加大沟槽尺寸,清扫开沟产生的硅粉,缩减开沟时间;改进后方案中所采用的化学蚀刻,可以改善物理开沟后沟槽表面光滑度,相较于以前的化学蚀刻方法,缩短了化学蚀刻时间,改善了沟槽形貌。
进一步的,对于切割刀片处理后形成深度加工沟槽的硅片,在化学蚀刻之前,先进行清洗,再进行一次黄光处理。
进一步的,上述一种高性能整流管芯片的制作工艺,包括以下步骤:
1)将硅片进行清洗,然后依次进行磷扩、硼扩;
2)将硼扩后的硅片进行上述开沟处理;
3)将开沟处理后的硅片进行RCA清洗,去除硅片表面(包括沟槽)有机物以及杂质;
4)将RCA清洗后的硅片进行LPCVD,在硅片表面(包括沟槽)生成半绝缘多晶硅膜;
5)将步骤4)处理后的硅片,进行光阻玻璃涂布,然后进行曝光、显影,得到所需图形;
6)将步骤5)处理后的硅片,进行玻璃高温烧结,在表面形成玻璃钝化;
7)将步骤6)处理后的硅片,进行LTO,生成氧化膜,然后进行三次黄光处理,去除多余钝化层;
8)将步骤7)处理后的硅片,进行表面金属化,然后对硅片进行测试、切割,得到高性能整流管芯片。
上述技术方案,改变了现有普通整流管芯片的制备方法,由原来的直接采用浸泡混酸的化学蚀刻开沟方式,变为先通过物理方式开沟(为避免直接采用刀片切割致使应力集中释放而破片,采用先激光再刀片的物理方式开沟),再用化学方式进一步加工的方法,缩短了化学蚀刻开沟时间,改善沟槽鸟嘴状结构过于凸出的情况,保证了沟槽的形状,便于深尺寸沟槽的开沟,进一步提高了产品的电压,玻璃层厚度均匀,降低了产品漏电。
附图说明
图1为背景技术中直接采用化学蚀刻开沟方式后,在硅片上形成的沟槽示意图;
图2为采用本发明开沟处理方法后,在硅片上形成的有效沟槽示意图;
图3为采用本发明方法制备的普通整流管芯片,芯片沟槽位置示意图;
图中:1玻璃层、2金属层、3硅片、4沟槽、5鸟嘴状结构。
具体实施方式
一种高性能整流管芯片的制作工艺,具体包括以下步骤:
1)硅片进行清洗,磷扩,硼扩;
2)将硼扩后硅片按照需要进行激光切割,激光频率50-80KHz,速度5-8mm/s,真空-30—50KPa,形成初步加工沟槽,切割深度在15-20μm;然后在激光切割的基础上采用切割刀片切割,切割刀片的规格选用宽度为100μm,形成深度加工沟槽,切割宽度约为100μm,深度约为70μm;
3)切割刀片切割后硅片进行清洗,然后进行一次黄光处理;
4)将步骤3)处理好的硅片放入配有混酸的石英槽,进行浸泡混酸处理,继续开槽,时间约为3-5min,温度-5—-10℃,得出所需的有效沟槽,如图2所示;混酸中包括硝酸、氢氟酸、醋酸、硫酸,硝酸:氢氟酸:醋酸:硫酸=9:9:12:7(体积比),比例可调整根据工艺不同来调整;
5)将步骤4)处理好的硅片,进行RCA清洗,去除表面有机物以及杂质;通过氨水、盐酸、双氧水的清洗,达到对表面杂质清洗的目的;
6)步骤5)处理好的硅片,进行LPCVD,通过低压沉积的方式在表面生成半绝缘多晶硅膜;
7)步骤6)处理好的硅片,进行光阻玻璃涂布(通过匀胶机将在硅片表面均匀的涂一层光阻玻璃),然后进行曝光、显影,得到想要的图形;
8)步骤7)处理好的硅片,进行玻璃高温烧结,通过升温、高温熔融再降温的过程,在表面形成玻璃钝化;
9)步骤8)处理好的硅片,进行LTO,生成氧化膜,然后进行三次黄光,去除多余钝化层;
10)步骤9)处理好的硅片,进行表面金属化,然后将材料进行测试、切割,得到高性能整流管芯片,包装出货。
经过以上制备方法得出产品结构如图3所示,优势在于缩短了化学蚀刻时间,沟槽形状更加规则,玻璃层能够更好的保护PN结,使产品耐压能力更强,降低了产品漏电参数。
在相同扩散工艺批次中取六组实验,分别用传统只采用化学蚀刻开沟处理方法与本发明组合式开沟处理方法产出芯片,测试数据结论如下表1,相同条件下,本发明能有效缩减开沟时间,提高产品电压,降低产品漏电。
表1 传统开沟处理方法与本发明开沟处理方法产出芯片的测试数据
Claims (7)
1.一种高性能整流管芯片的制作工艺,其特征是,该芯片在制备过程中,所采用的开沟处理方法包括:
将需要开沟处理的硅片在清洗后,先用激光切割,形成初步加工沟槽;然后,使用切割刀片在初步沟槽的基础上进行切割,形成深度加工沟槽;最后,对深度加工沟槽进行化学蚀刻,蚀刻时间3-6min,形成所需的有效沟槽。
2.根据权利要求1所述的一种高性能整流管芯片的制作工艺,其特征是,所述初步加工沟槽的深度在15-20μm。
3.根据权利要求2所述的一种高性能整流管芯片的制作工艺,其特征是,所述切割刀片的宽度为100μm。
4.根据权利要求3所述的一种高性能整流管芯片的制作工艺,其特征是,所述深度加工沟槽的宽度为100μm、深度为70μm。
5.根据权利要求1或4所述的一种高性能整流管芯片的制作工艺,其特征是,对切割刀片处理后的硅片进行清洗,然后进行一次黄光处理。
6.根据权利要求5所述的一种高性能整流管芯片的制作工艺,其特征是,在进行化学蚀刻时,将硅片浸泡混酸处理,时间为3-6min,温度-5—-10℃。
7.根据权利要求6所述的一种高性能整流管芯片的制作工艺,其特征是,包括以下步骤:
1)将硅片进行清洗,然后依次进行磷扩、硼扩;
2)将硼扩后的硅片进行开沟处理;
3)将开沟处理后的硅片进行RCA清洗,去除表面有机物以及杂质;
4)将RCA清洗后的硅片进行LPCVD,在表面生成半绝缘多晶硅膜;
5)将步骤4)处理后的硅片,进行光阻玻璃涂布,然后进行曝光、显影,得到所需图形;
6)将步骤5)处理后的硅片,进行玻璃高温烧结,在表面形成玻璃钝化;
7)将步骤6)处理后的硅片,进行LTO,生成氧化膜,然后进行三次黄光处理,去除多余钝化层;
8)将步骤7)处理后的硅片,进行表面金属化,然后对硅片进行测试、切割,得到高性能整流管芯片。
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