CN117096124A - 电子封装件及其电子结构 - Google Patents

电子封装件及其电子结构 Download PDF

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CN117096124A
CN117096124A CN202210554158.8A CN202210554158A CN117096124A CN 117096124 A CN117096124 A CN 117096124A CN 202210554158 A CN202210554158 A CN 202210554158A CN 117096124 A CN117096124 A CN 117096124A
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conductive
electronic
layer
electronic structure
openings
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李泳达
黄柏凯
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
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Abstract

一种电子封装件及其电子结构，包括将电子结构以多个导电元件接合于一承载结构上，其中，各该导电元件以多个导电柱连接该电子结构的单一接点，以于其中一个导电柱失效时，各该导电元件仍可利用其它导电柱电性连接各该接点，藉以增加电性导通率。

Description

电子封装件及其电子结构
技术领域
本发明有关一种半导体装置，尤指一种可提升封装可靠度的电子封装件及其电子结构。
背景技术
传统覆晶式(flip chip)半导体封装技术主要于半导体芯片的接点上形成焊料元件(solder bump)，再通过该焊料元件直接与封装基板电性连接，故相比于打线(wirebonding)方式而言，覆晶技术的电路路径较短，且具有较佳的电性品质，同时因可设计为晶背裸露形式，亦可提高该半导体芯片的散热性。
如图1A及图1B所示的半导体芯片1，其芯片本体11形成有集成电路，且于最外侧设有电极垫12，并将如钝化层的绝缘层13形成于该芯片本体11及该集成电路上(但外露该电极垫12)，且将导电元件15形成于该电极垫12上，以供结合至封装基板上，其中，该绝缘层13上形成有一外露该电极垫12的开孔130，以令该导电元件15延伸至该开孔130中，供作为导电柱14，使该导电元件15通过该导电柱14电性连接该电极垫12。
然而，现有半导体芯片1中，该导电柱14的深度D与宽度R的比值(即深宽比)极小，导致该导电元件15无法稳固设于该电极垫12上，故当封装基板与半导体芯片1的导电元件15进行覆晶接合时，该导电元件15容易因挤压而应力集中于该导电柱14之处，导致该导电元件15于该导电柱14处发生碎裂的问题。
再者，当该导电柱14因碎裂而电性失效时，该导电元件15与该电极垫12之间即断路，导致该半导体芯片1的电性导通率不佳。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种电子封装件及其电子结构，可增加电性导通率。
本发明的电子结构，包括：电子本体；多个接点，其设于该电子本体上；绝缘层，其设于该电子本体上且具有多个开孔，以令各该接点的部分表面外露于该多个开孔；多个导电柱，其设于该多个开孔中并电性连接该多个接点；以及多个导电元件，其设于该多个导电柱上，且令单一该导电元件与单一该接点之间通过该多个导电柱相连接。
前述的电子结构中，该多个开孔的其中至少一者的深宽比大于0.38。
前述的电子结构中，该多个导电柱的深宽比均相同。
前述的电子结构中，该多个导电柱的其中至少两者的深宽比不相同。
前述的电子结构中，该绝缘层于该电子本体上为非连续布设，使相邻的该多个导电元件之间的绝缘层互不相连。
本发明亦提供一种电子封装件，包括：承载结构，其包含一具有线路层的基板本体、设于该基板本体上的绝缘保护层、及设于绝缘保护层上的多个电性接触垫，且该多个电性接触垫通过多个导电盲孔电性连接该线路层；以及前述的电子结构，其以其多个导电元件接合该多个电性接触垫。
前述的电子封装件中，单一该电性接触垫通过多个该导电盲孔电性连接该线路层。
前述的电子封装件中，该多个导电盲孔的深宽比与该多个导电柱的深宽比不相同。
前述的电子封装件中，单一该电性接触垫的垂直投影面积大于单一该导电元件的垂直投影面积。
前述的电子封装件中，该多个导电元件的其中至少两者所对应的导电柱的深宽比不相同。
由上可知，本发明的电子封装件及其电子结构中，主要通过单一该导电元件与单一该接点之间通过该多个导电柱相连接，以提高各该导电柱的深宽比，因而可提升电镀该导电柱的良率，使该导电元件可稳固设于该接点上，进而增加整个电子结构的可靠性，故相比于现有技术，当本发明的电子结构以其导电元件接合于一承载结构上时，该导电元件于挤压时可通过该多个导电柱分散应力，以避免该导电元件于该导电柱处发生碎裂的问题。
再者，单一该导电元件与单一该接点之间通过该多个导电柱作为电性连接途径，以于其中一个导电柱失效时，仍可利用其它导电柱进行电性连接，故可增加电性导通率。
附图说明
图1A为现有半导体芯片的局部剖面示意图。
图1B为图1A的局部上视示意图。
图2A为本发明的电子结构的局部剖面示意图。
图2B为图2A的局部放大示意图。
图2C为图2B的局部上视示意图。
图2D为图2C的另一实施例的上视示意图。
图3A为图2B的另一实施例的剖面示意图。
图3B为图2A的另一实施例的剖面示意图。
图4A为本发明的电子封装件的第一实施例的局部剖面示意图。
图4B为图4A的另一实施例的局部上视示意图。
图4B-1为图4B的另一实施例的上视示意图。
图4B-2及图4B-3为图4B-1的其它实施例的上视示意图。
图4C及图4D为图4B的其它不同实施例的局部上视示意图。
图5为本发明的电子封装件的第二实施例的剖面示意图。
主要组件符号说明
1 半导体芯片
11 芯片本体
12 电极垫
13,23,33 绝缘层
130,230,330 开孔
14,24,24a,44a 导电柱
15,25,25a,25b,45a 导电元件
2a,3a,5a 电子结构
21 电子本体
22 接点
4,5 电子封装件
4a,90 承载结构
40,901 基板本体
41,91 焊锡材料
42,902 线路层
43,903 绝缘保护层
44,904 导电盲孔
45,905 电性接触垫
510 导电穿孔
52 导电体
53 绝缘膜
93 导电结构
95 封装层
96 布线结构
960 介电层
961 线路重布层
A 覆盖区域
D,d,h 深度
R,W,W1,W2,r 宽度
t 间距
P1,P2 垂直投影面积。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、及“一”等的用语，亦仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A、图2B及图2C为本发明的电子结构2a的剖面及上视示意图。如图2A至图2C所示，本发明的电子结构2a包括一电子本体21、多个接点22、至少一绝缘层23、多个导电柱24以及多个导电元件25。
所述的电子本体21为半导体基材，其内配置有多个层集成电路，以形成芯片规格。
所述的多个接点22配置于最外层的集成电路上。
所述的绝缘层23为钝化层，如氮化硅或氧化硅，但并不限于此。
于本实施例中，该绝缘层23于单一该接点22上形成有多个开孔230，以令单一该接点22的部分表面外露于该多个开孔230。例如，该绝缘层23可形成有三个如圆孔的开孔230，其直径大小相同且相互等距间隔排设，如图2C所示。应可理解地，有关该开孔230的数量及排列方式可依需求设计，如图2D所示的两个圆孔，并不限于上述。
再者，各该开孔230的深宽比可相同，如各该开孔230的深度d与宽度W的比值大于0.38。或者，该多个开孔230,330的其中至少两者的深宽比可相异，如图3A所示的不同宽度W1,W2或如图4B-1所示的导电元件25b上的导电柱24,24a的配置。
另外，该绝缘层23可形成于该电子本体21的整版面上。于另一实施例中，该绝缘层33可依需求仅对应形成于该接点22及其周围处，如图3B所示，以形成多个相互间隔(如图3B所示的间距t)的覆盖区域A。
所述的多个导电元件25通过多个导电柱24电性连接该多个接点22，其中，各该导电柱24形成于各该开孔230中以电性连接该接点22。
于本实施例中，各该导电元件25与多个该导电柱24为一体成形，且于单一接点22上配置多个导电柱24，供作多条电性连接的途径，以当其中一个导电柱24失效时，仍可利用其它导电柱24进行电性连接。其中，该元件可为铜柱(Cu pillar)、凸块(Bump)及其组合等。
因此，本发明的电子结构2a通过该多个导电柱24连接单一接点22的设计，使各该导电柱24具有较大的深宽比，故相比于现有技术，本发明的导电元件25能稳固设于该接点22上而不易形变。例如，当该电子结构2a作为半导体芯片并以多个导电元件25覆晶接合于一如封装基板的承载结构4a上时，如图4A所示的电子封装件4，各该导电元件25于挤压时能通过该多个导电柱24分散应力，以避免该导电元件25于该多个导电柱24处发生碎裂的问题。
所述的承载结构4a包含一具有线路层42的基板本体40、一形成于该基板本体40上的绝缘保护层43、及多个形成于绝缘保护层43上的电性接触垫45，如图4A所示，且各该电性接触垫45通过多个导电盲孔44电性连接该线路层42。
于本实施例中，该电性接触垫45采用微垫(u-pad)规格，且该导电元件25属于微元件(u-bump)规格，以通过焊锡材料41接合该导电元件25与该电性接触垫45或导电元件25与电性接触垫45以金属对金属(Metal-to-Metal Bonding)方式接合。例如，单一该电性接触垫45通过多个导电盲孔44连接至单一线路层42上，且各该导电盲孔44的深度h与宽度r的比值(即深宽比)均相同，较佳的深宽比为0.63。应可理解地，该导电盲孔44的深宽比与该导电柱24的深宽比相异。
再者，该电性接触垫45的垂直投影面积P1可大于该导电元件25的垂直投影面积P2，以避免因该导电元件25于回焊作业时偏位而造成焊接不良的问题。
另外，该多个导电元件25的其中至少两者所对应的导电柱24的深宽比不相同。例如，当该电子结构2a为矩形体时，不同位置的导电元件25所对应的导电柱24的深宽比可依需求调整。较佳地，如图4B及图4B-1所示，该电子结构2a的角落处的应力较大，故位于角落处的导电元件25a,25b所对应的导电柱24a的深宽比较小(即该导电柱24a的端面的面积较大)，而该电子结构2a的其它处的应力较小，故其它导电元件25所对应的导电柱24的深宽比较大(即该导电柱24的端面的面积较小)，甚至于该导电元件25a,25b所对应的不同大小的导电柱24,24a可依应力大小的方向作配置，如图4B-2及图4B-3所示的朝该电子结构2a的中心处配置较小端面的导电柱24。进一步，该导电元件25a,25b及/或其所对应的导电柱24a可依需求改变形状，如图4C及图4D所示的长条状(或类椭圆形)的导电柱44a及导电元件45a，以利于分散应力。因此，可依据该电子结构2a于封装时所产生的应力大小，调整该导电元件25,25a,25b,45a所对应的导电柱24,24a,44a的深宽比的大小。
另外，如图5所示，电子结构5a亦可作为中介板结构，其还包括多个形成于电子本体21中且电性连接接点22的如硅穿孔(Through Silicon Via，简称TSV)规格的导电穿孔510、多个设于该电子本体21相对该接点22的另一侧且电性连接该导电穿孔510的导电体52、及一包覆该多个导电体52的绝缘膜53。
进一步，该电子结构5a可应用于一电子封装件5中。如图5所示，该电子封装件5还包括一用以承载该电子结构5a的承载结构90、多个设于该承载结构90上的导电结构93、包覆该电子结构5a与多个导电结构93的封装层95、以及形成于该封装层95上的布线结构96。
所述的承载结构90例如为具有核心层的封装基板(substrate)或无核心层(coreless)式载板，其基板本体901于绝缘材上形成多个线路层902，如扇出型(fan out)重布线路层(redistribution layer，简称RDL)，且于最外侧的线路层902上形成有绝缘保护层903，并于绝缘保护层903上形成电性接触垫905，以令该电性接触垫905通过多个导电盲孔904电性连接该线路层902。例如，形成该线路层902、电性接触垫905与导电盲孔904的材质为铜，且该绝缘材如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)或其它等的介电材。
于本实施例中，该电子结构5a以其导电元件25通过焊锡材料91接合该电性接触垫905。
再者，该导电盲孔904的深宽比与该导电柱24的深宽比不相同。
所述的多个导电结构93为柱体并电性连接该线路层902，且形成该多个导电结构93的材质为如铜的金属材或焊锡材。
所述的封装层95形成于该承载结构90上，且通过整平制程，使该封装层95的表面齐平该多个导电结构93的端面与该电子结构5a的绝缘膜53(或该多个导电体52的端面)，令该多个导电结构93的端面与该电子结构5a的绝缘膜53(或该多个导电体52的端面)外露出该封装层95的表面。于本实施例中，该封装层95为绝缘材，如环氧树脂的封装胶体，其可用压合(lamination)或模压(molding)的方式形成于该承载结构90上。
所述的布线结构96电性连接该多个导电结构93与该电子结构5a的多个导电体52。于本实施例中，该布线结构96包括多个介电层960、及设于该介电层960上的多个线路重布层(RDL)961，且最外层的介电层960可作为防焊层，以令最外层的线路重布层961部分外露出该防焊层。应可理解地，该布线结构96亦可仅包括单一介电层960及单一线路重布层961。因此，于后续制程中，可于最外层的线路重布层961上接置至少一半导体芯片(图略)或其它电子元件。
因此，于该电子封装件5进行热处理期间(thermal cycle)，该导电元件25能将应力分散于该些导电柱24，使该些导电柱24不会因应力集中而发生碎裂的问题，以有效电性连接该接点22。
综上所述，本发明的电子结构2a,3a,5a中，主要通过该接点22与该导电元件25,25a,25b之间通过多个导电柱24,24a相接，以提高各该导电柱24,24a的深宽比，因而能提升电镀该导电柱24,24a的良率，进而增加整个电子结构2a,3a,5a的可靠性。较佳地，各该导电柱24,24a的深宽比大于0.38，以避免该导电元件25,25a的顶面形成凹盘(dish)的问题，因而能防止该导电元件25,25a,25b发生形变。
再者，通过多个导电柱24,24a电性连接该接点22与该导电元件25,25a,25b，使该接点22与该导电元件25,25a,25b之间具有多条电性连接的途径，故于封装后，若其中一导电柱24,24a失效时，仍可利用其它导电柱24,24a达到电性连接的目的，因而增加电性导通率。
另外，通过该绝缘层33为非连续布设，如图3B所示，使相邻的导电元件25之间的绝缘层33为非连续结构，以形成应力缓冲机制，故能避免该电子结构3a发生翘曲，以提升可靠性及导电良率。
另外，于封装时，本发明的电子封装件4,5通过该多个导电柱24连接单一接点22的设计，以将该导电元件25的应力分散于多个导电柱24中，故能避免该导电元件25于该导电柱24处发生碎裂的问题。同理地，亦可将该电性接触垫45,905的应力分散于多个导电盲孔44,904中，以避免该电性接触垫45,905于该导电盲孔44,904处发生碎裂的问题。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (10)

1.一种电子结构，包括：
电子本体；
多个接点，其设于该电子本体上；
绝缘层，其设于该电子本体上且具有多个开孔，以令各该接点的部分表面外露于该多个开孔；
多个导电柱，其设于该多个开孔中并电性连接该多个接点；以及
多个导电元件，其设于该多个导电柱上，且令单一该导电元件与单一该接点之间通过该多个导电柱相连接。
2.如权利要求1所述的电子结构，其中，该多个开孔的其中至少一者的深宽比大于0.38。
3.如权利要求1所述的电子结构，其中，该多个导电柱的深宽比均相同。
4.如权利要求1所述的电子结构，其中，该多个导电柱的其中至少两者的深宽比不相同。
5.如权利要求1所述的电子结构，其中，该绝缘层于该电子本体上为非连续布设，使相邻的该多个导电元件之间的绝缘层互不相连。
6.一种电子封装件，包括：
承载结构，其包含一具有线路层的基板本体、设于该基板本体上的绝缘保护层、及设于绝缘保护层上的多个电性接触垫，且该多个电性接触垫通过多个导电盲孔电性连接该线路层；以及
如权利要求1至5中任一项所述的电子结构，其以其多个导电元件接合该多个电性接触垫。
7.如权利要求6所述的电子封装件，其中，单一该电性接触垫通过多个该导电盲孔电性连接该线路层。
8.如权利要求6所述的电子封装件，其中，该多个导电盲孔的深宽比与该多个导电柱的深宽比不相同。
9.如权利要求6所述的电子封装件，其中，单一该电性接触垫的垂直投影面积大于单一该导电元件的垂直投影面积。
10.如权利要求6所述的电子封装件，其中，该多个导电元件的其中至少两者所对应的导电柱的深宽比不相同。
CN202210554158.8A 2022-05-13 2022-05-20 电子封装件及其电子结构 Pending CN117096124A (zh)

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