CN117080058A - 一种提升igbt器件可靠性的工艺方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 238000005530 etching Methods 0.000 claims abstract description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 12
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 230000007547 defect Effects 0.000 claims abstract description 9
- 239000011248 coating agent Substances 0.000 claims abstract description 5
- 238000000576 coating method Methods 0.000 claims abstract description 5
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 239000000126 substance Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 12
- 239000004065 semiconductor Substances 0.000 abstract description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 7
- 235000012431 wafers Nutrition 0.000 description 5
- 241000293849 Cordylanthus Species 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012797 qualification Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
Abstract
本发明公开了一种提升IGBT器件可靠性的工艺方法,属于半导体器件制造领域,在硅衬底表面涨一层二氧化硅膜;在二氧化硅膜上涂敷光刻胶;曝光、显影、硬烘形成刻蚀图案;直接刻蚀图案至Si衬底的5.x微米深处;在晶圆表面生长一层牺牲氧化层,对晶圆表面进行处理;去除牺牲氧化层,清除刻蚀过程带来的杂质;在沟槽内生长栅极氧化膜。在深沟槽刻蚀的过程中,光刻胶在生长了二氧化硅薄膜的硅衬底表面上胶、曝光、显影等形成刻蚀图案,然后直接刻蚀至硅衬底,可以降低生产成本、缩短生产周期、节省生产产能;减少工艺缺陷,提高产品良率;改善开启电压的不稳定性,提高器件的可靠性。
Description
技术领域
本发明涉及一种半导体器件的制造方法,具体而言是一种提升IGBT器件可靠性的工艺方法。
背景技术
IGBT(InsulatedGateBipolarTransistor),被称为绝缘栅双极型晶体管,是由(BipolarJunctionTransistor,BJT)双极型三极管和绝缘栅型场效应管(MetalOxideSemiconductor,MOS)组成的复合全控型电压驱动式功率半导体器件,兼有(Metal-Oxide-SemiconductorField-EffectTransistor,MOSFET)金氧半场效晶体管的高输入阻抗和电力晶体管(GiantTransistor,GTR)的低导通压降两方面的优点。GTR饱和压降低,载流密度大,但驱动电流较大;MOSFET驱动功率很小,开关速度快,但导通压降大,载流密度小。IGBT综合了以上两种器件的优点,驱动功率小而饱和压降低。非常适合应用于直流电压为600V及以上的变流系统如交流电机、变频器、开关电源、照明电路、牵引传动等领域。
在现有技术中,我们在对1200V的IGBT器件的沟槽结构刻蚀时,采用TEOS和Nitride作为阻挡层进行刻蚀,但是由于氮化硅的应力比较大,在进行干法刻蚀的时候,产生如图3的“鸟嘴”现象,会严重影响后续在沟槽内使用热氧化法生长的栅氧化薄膜的可靠性质量,进而影响开启电压的稳定性,而且沉积二氧化硅和氮化硅会严重浪费产能,使得刻蚀工艺复杂,因此,针对以上两个问题本发明提出了一种新的刻蚀方法。
现有IGBT器件的深沟槽刻蚀技术,其流程如图1所示,具体如下:
(1)在硅衬底表面生长一层SiO2薄膜;
(2)在SiO2薄膜上生长一层
(3)在Si3N4层上生长层;
(4)在TEOS表面涂光刻胶;
(5)对光刻胶进行曝光、显影形成刻蚀图案;
(6)对TEOS表面图案进行干刻,刻至衬底表面;
(7)去除剩余光刻胶;
(8)衬底表面进行刻蚀,刻至衬底内部5.x微米;
(9)去除TEOS;
(10)接着在晶圆表面生长一层牺牲氧化层,再去除牺牲氧化层;
(11)接着在深沟槽内通过热氧化法涨一层二氧化硅,作为栅极绝缘膜;
(12)用湿法刻蚀去除Si3N4。
在对步骤(2)与步骤(3)的沉积过程中,其沉积时间较长,沉积温度较高,对整个1200V的IGBT器件的生产流程带来很大的影响,除此之外,在对TEOS与Nitride进行刻蚀过程中,会产生很多缺陷和杂质,尤其是刻蚀过程中带来的粉末也会沾污其他的机台。
发明内容
为了解决上述技术问题,本发明提供一种提升IGBT器件可靠性的工艺方法,由以下步骤组成:
(1)在硅衬底表面涨一层二氧化硅膜;
(2)在二氧化硅膜上涂敷光刻胶;
(3)曝光、显影、硬烘形成刻蚀图案;
(4)直接刻蚀图案至Si衬底的5.x微米深处;
(5)使用湿化学法和干化学法去除多余的光刻胶;
(6)在晶圆表面生长一层牺牲氧化层,对晶圆表面进行处理;
(7)去除牺牲氧化层,清除刻蚀过程带来的杂质;
(8)在沟槽内生长栅极氧化膜。
进一步的,所述步骤(1)采用LPCVD或PECVD或热氧化法沉积。
进一步的,所述步骤(6)生长方法为热氧化法。
进一步的,所述步骤(7)去除牺牲氧化层采用湿化学法或者干化学法。
进一步的,所述步骤(8)使用热氧化法生长栅极氧化膜。
和现有技术相比,本发明具有以下有益效果:在对1200V的IGBT器件深沟槽刻蚀的过程中,将现有技术中利用LPCVD法生长的两步薄膜TEOS/Nitride直接用光刻胶代替,经过在生长了二氧化硅薄膜的硅衬底表面上胶、曝光、显影等形成刻蚀图案,然后直接刻蚀至硅衬底,可以降低生产成本、缩短生产周期、节省生产产能;减少工艺缺陷,提高产品良率;改善开启电压(Vth)的稳定性,提高器件的可靠性。
附图说明
图1是现有技术中现有深沟槽刻蚀流程图;
图2是本发明的深沟槽刻蚀流程;
图3是现有技术中存在的“鸟嘴”结构图;
图4是本发明产品的局部放大图;
图5是现有技术刻蚀后的缺陷图;
图6是本发明刻蚀后的缺陷图。
具体实施方式
下面结合附图对本发明的技术方案做进一步阐述。
与图1不同,如图2所示,本实施例提供的一种提升IGBT器件可靠性的工艺方法,与图1中的流程不同,参考图2,具体步骤为:
(1)在硅衬底表面沉积一层二氧化硅膜,其中沉积方法为LPCVD/PECVD/热氧化法;
(2)在沉积的二氧化硅薄膜上涂敷光刻胶;
(3)曝光、显影、硬烘形成刻蚀图案;
(4)使用干刻的方法刻至Si衬底的5.0-6.0微米深处;
(5)使用湿化学法和干化学法去除多余的光刻胶;
(6)热氧化法在晶圆表面使用热氧化法生长一层牺牲氧化层;
(7)采用湿化学法去除牺牲氧化层,清除刻蚀过程带来的缺陷杂质;
(8)热氧化法在沟槽底部和侧壁生长栅极氧化膜。
图3是针对现有工艺流程的产品通过聚焦离子束技术FIB(FocousionBeam,FIB)配合扫描电镜(SEM)等高倍数电子显微镜观察分析而来。本实施例的产品通过聚焦离子束技术FIB(FocousionBeam,FIB)配合扫描电镜(SEM)等高倍数电子显微镜观察分析如图4所示,按照本实施例的方法进行刻蚀,“鸟嘴”消失。
图5是针对现有工艺流程的产品通过KLA设备扫描得到,图6是本实施例的产品通过KLA设备扫描得到,可以看到缺陷明显得到改善。
现有工艺流程的产品和本实施例的产品通过CP测试方法测开启电压量测值而知,参考表1,本实施例的产品可以使得器件的开启电压稳定性得以改善。
表1
测试项目 | 现有技术测得值 | 本实施例测得值 |
Sigma | 90 | 86 |
Range | 227 | 190 |
在现有技术和本实施例技术的前提下,各对95片产品进行量测,得到表2,本实施例产品的合格率94%,现有技术的产品合格率85%,比现有技术合格率高出9%。
表2
量测晶圆片数 | 现有技术产品合格率(%) | 本实施例产品合格率(%) |
95 | 85 | 94 |
综合以上数据,本实施例提供的提升IGBT器件可靠性的工艺方法可以降低生产成本、缩短生产周期、节省生产产能;减少工艺缺陷,提高产品良率;改善开启电压(Vth)的稳定性,提高器件的可靠性。
Claims (5)
1.一种提升IGBT器件可靠性的工艺方法,其特征在于,由以下步骤组成:
步骤(1)在硅衬底表面沉积一层二氧化硅膜;
步骤(2)在沉积的二氧化硅薄膜上涂敷光刻胶;
步骤(3)曝光、显影、硬烘形成刻蚀图案;
步骤(4)使用干刻的方法刻至硅衬底的5.x微米深处;
步骤(5)使用干化学法和湿化学法去除多余的光刻胶;
步骤(6)在晶圆表面生长一层牺牲氧化层;
步骤(7)去除牺牲氧化层,清除刻蚀过程带来的缺陷杂质;
步骤(8)在沟槽底部和侧壁生长栅极氧化膜。
2.根据权利要求1所述提升IGBT器件可靠性的工艺方法,其特征在于,所述步骤(1)采用LPCVD或PECVD或热氧化法。
3.根据权利要求1所述提升IGBT器件可靠性的工艺方法,其特征在于,所述步骤(6)生长方法为LPCVD或PECVD或热氧化法。
4.根据权利要求1所述提升IGBT器件可靠性的工艺方法,其特征在于,所述步骤(7)去除牺牲氧化层采用湿化学法或者干化学法。
5.根据权利要求1所述提升IGBT器件可靠性的工艺方法,其特征在于,所述步骤(8)使用热氧化法生长栅极氧化膜。
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