CN116995092A - 一种igbt器件及其制备方法 - Google Patents

一种igbt器件及其制备方法 Download PDF

Info

Publication number
CN116995092A
CN116995092A CN202311266836.1A CN202311266836A CN116995092A CN 116995092 A CN116995092 A CN 116995092A CN 202311266836 A CN202311266836 A CN 202311266836A CN 116995092 A CN116995092 A CN 116995092A
Authority
CN
China
Prior art keywords
igbt
electrode
substrate
nmos tube
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202311266836.1A
Other languages
English (en)
Other versions
CN116995092B (zh
Inventor
侯晓伟
柴展
罗杰馨
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Gongcheng Semiconductor Technology Co Ltd
Original Assignee
Shanghai Gongcheng Semiconductor Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Gongcheng Semiconductor Technology Co Ltd filed Critical Shanghai Gongcheng Semiconductor Technology Co Ltd
Priority to CN202311266836.1A priority Critical patent/CN116995092B/zh
Publication of CN116995092A publication Critical patent/CN116995092A/zh
Application granted granted Critical
Publication of CN116995092B publication Critical patent/CN116995092B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41708Emitter or collector electrodes for bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66325Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明属于半导体集成电路设计及制造领域,特别是涉及一种IGBT器件及其制备方法,包括:衬底,所述衬底上形成有IGBT器件的IGBT发射极、IGBT栅极和IGBT集电极;NMOS管,所述NMOS管设置于所述衬底上,且设置于所述IGBT栅极和所述IGBT发射极之间,所述NMOS管的漏极与所述IGBT栅极电性连接,所述NMOS管的栅极和源极与所述IGBT发射极电性连接,所述NMOS管的栅极和所述IGBT发射极之间连接有电阻;本发明相比于现有技术,可通过调整在发射极框架的打线位置调整电阻值,从而调整NMOS导通时IGBT的短路电流值,本专利技术可以改善器件发热,提升功率密度,进而提升器件性能。

Description

一种IGBT器件及其制备方法
技术领域
本发明属于半导体集成电路设计及制造领域,特别是涉及一种IGBT器件及其制备方法。
背景技术
目前,IGBT 器件通常应用于电机,变频器,PFC等多种大电流应用领域,在大多数IGBT领域(如空调压缩机、内风机、汽车电机驱动、汽车PTC座椅加热、光伏逆变器等)中,需要IGBT能够有10us的短路时间,为保证器件有10us的短路时间,需降低IGBT器件电流密度,这样会极大的增加器件的导通损耗,使器件的工作效率降低。
因此,现有技术仍需要改进。
发明内容
本发明的目的在于解决现有技术在需要IGBT短路的时间中,需降低IGBT器件电流密度,这样会极大的增加器件的导通损耗,使器件的工作效率降低的问题。
为实现上述目的,本发明采用下述技术方案:
本发明提供一种IGBT器件,包括:
衬底,所述衬底上形成有IGBT器件的IGBT发射极、IGBT栅极和IGBT集电极;
NMOS管,所述NMOS管设置于所述衬底上,且设置于所述IGBT栅极和所述IGBT发射极之间,所述NMOS管的漏极与所述IGBT栅极电性连接,所述NMOS管的栅极和源极与所述IGBT发射极电性连接,所述NMOS管的栅极和所述IGBT发射极之间连接有电阻;
当所述IGBT器件短路时,所述IGBT发射极施加阈值电压,所述阈值电压同时施加于所述NMOS管的栅极以使所述NMOS管导通,从而使所述IGBT发射极与所述IGBT栅极短接,并使得电流下降。
进一步的,所述阈值电压的值为3V-5V。
进一步的,所述IGBT栅极与IGBT栅极总线电性连接,所述IGBT栅极总线设置为环形并且环绕于所述IGBT发射极外围。
进一步的,所述衬底包括相对的第一面和第二面,所述IGBT发射极、IGBT栅极和所述NMOS管的栅极设置于所述衬底的第一面,所述IGBT集电极设置于所述衬底的第二面,或/及所述IGBT器件还包括场截止层,设置于所述衬底中,并靠近所述IGBT集电极设置。
本发明还提供一种IGBT器件的制备方法,包括下列步骤:
提供一衬底,于所述衬底上形成IGBT器件的IGBT发射极、IGBT栅极、IGBT集电极;
于所述衬底上设置NMOS管,所述NMOS管置于所述IGBT栅极和所述IGBT发射极之间,所述NMOS管的漏极与所述IGBT栅极电性连接,所述NMOS管的栅极和源极与所述IGBT发射极电性连接,所述NMOS管的栅极和所述IGBT发射极之间连接有电阻。
进一步的,于所述衬底上设置NMOS管包括下列步骤:
通过离子注入工艺于所述衬底中形成P阱和;
于所述衬底上形成栅介质层和栅极层,并通过图形化工艺形成IGBT栅极和NMOS管的栅极;
通过离子注入工艺于所述P阱中形成NMOS管的源极和漏极;
于所述衬底上形成绝缘层,于所述绝缘层中形成接触孔,于所述接触孔和所述绝缘层上形成金属层,并通过图形化工艺形成布线层,通过所述接触孔和所述布线层,使得所述NMOS管的漏极与所述IGBT栅极电性连接,所述NMOS管源极与所述IGBT发射极电性连接,所述NMOS管的栅极与接触点电性连接。
进一步的,还包括步骤:通过外部管脚于所述NMOS管的栅极的接触点和所述IGBT发射极之间接入电阻。
进一步的,当所述IGBT器件短路时,所述IGBT发射极施加阈值电压,所述阈值电压同时施加于所述NMOS管的栅极以使所述NMOS管导通,从而使所述IGBT发射极与所述IGBT栅极短接,并使得电流下降。
进一步的,所述阈值电压的值为3V-5V。
进一步的,所述衬底包括相对的第一面和第二面,所述IGBT发射极、IGBT栅极和所述NMOS管的栅极设置于所述衬底的第一面,所述IGBT集电极设置于所述衬底的第二面,或/及所述IGBT器件还包括场截止层,设置于所述衬底中,并靠近所述IGBT集电极设置。
本发明的有益效果在于:不需降低IGBT本身的电流密度从而提升短路能力。此外,可通过调整在发射极框架的打线位置调整电阻值,从而调整NMOS导通时IGBT的短路电流值,本专利反映的技术可以改善器件发热,提升功率密度,进而提升器件性能。
附图说明
图1为本发明实施例的IGBT器件的电路原理示意图;
图2为本发明实施例的IGBT器件的布局结构示意图;
图3~6为本发明实施例的IGBT器件的制备方法各步骤所呈现的结构示意图。
具体实施方式
下面结合附图和实施例对本发明作进一步的详细说明。可以理解的是,此处所描述的具体实施例仅仅用于解释本发明,而非对本发明的限定。另外还需要说明的是,为了便于描述,附图中仅示出了与本发明相关的部分而非全部结构。
在本发明的描述中,除非另有明确的规定和限定,术语“相连”、“连接”、“固定”应做广义理解,例如,可以是固定连接,也可以是可拆卸连接,或成一体;可以是机械连接,也可以是电连接;可以是直接相连,也可以通过中间媒介间接相连,可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言,可以具体情况理解上述术语在本发明中的具体含义。
在本发明中,除非另有明确的规定和限定,第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触,也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且,第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方,或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方,或仅仅表示第一特征水平高度小于第二特征。
在本实施例的描述中,术语“上”、“下”、“右”、等方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述和简化操作,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。此外,术语“第一”、“第二”仅仅用于在描述上加以区分,并没有特殊的含义。
如图1~图6所示,本发明提供一种IGBT器件,包括:
衬底1,所述衬底1上形成有IGBT器件的IGBT发射极14、IGBT栅极12和IGBT集电极;
NMOS管30,所述NMOS管30设置于所述衬底上,且设置于所述IGBT栅极12和所述IGBT发射极14之间,所述NMOS管的漏极与所述IGBT栅极12电性连接,所述NMOS管的栅极13和源极与所述IGBT发射极14电性连接,所述NMOS管的栅极和所述IGBT发射极14之间连接有电阻21;
当所述IGBT器件短路时,所述IGBT发射极14施加阈值电压,所述阈值电压同时施加于所述NMOS管的栅极13以使所述NMOS管导通,从而使所述IGBT发射极14与所述IGBT栅极短接,并使得电流下降。
进一步的,所述阈值电压的值为3V-5V。
进一步的,所述IGBT栅极12与IGBT栅极总线10电性连接,所述IGBT栅极总线10设置为环形并且环绕于所述IGBT发射极14外围。
进一步的,所述衬底1包括相对的第一面和第二面,所述IGBT发射极14、IGBT栅极12和所述NMOS管的栅极13设置于所述衬底的第一面,所述IGBT集电极设置于所述衬底的第二面,或/及所述IGBT器件还包括场截止层,设置于所述衬底中,并靠近所述IGBT集电极设置。
本发明还提供一种IGBT器件的制备方法,包括下列步骤:
提供一衬底1,于所述衬底1上形成IGBT器件的IGBT发射极14、IGBT栅极12、IGBT集电极;
于所述衬底上设置NMOS管30,所述NMOS管30电性连接在所述IGBT栅极12和所述IGBT发射极14之间,所述NMOS管的漏极与所述IGBT栅极12电性连接,所述NMOS管的栅极和源极与所述IGBT发射极电性连接,所述NMOS管的栅极和所述IGBT发射极之间连接有电阻。
进一步的,于所述衬底1上设置NMOS管包括下列步骤:
通过离子注入工艺于所述衬底1中形成P阱2;
于所述衬底上形成栅介质层5和栅极层,并通过图形化工艺形成IGBT栅极12和NMOS管的栅极13;
通过离子注入工艺于所述P阱2中形成NMOS管的源极4和漏极3;
于所述衬底1上形成绝缘层20,于所述绝缘层中形成接触孔,于所述接触孔和所述绝缘层上形成金属层,并通过图形化工艺形成布线层,通过所述接触孔和所述布线层,使得所述NMOS管的漏极3通过第一连接线6与所述IGBT栅极12电性连接,所述NMOS管源极4通过第二连接线7与所述IGBT发射极14电性连接,所述NMOS管的栅极13与接触点8电性连接。
进一步的,还包括步骤:通过外部管脚于所述NMOS管的栅极的接触点8和所述IGBT发射极14之间接入电阻21。
进一步的,当所述IGBT器件短路时,所述IGBT发射极施加阈值电压,所述阈值电压同时施加于所述NMOS管的栅极以使所述NMOS管导通,从而使所述IGBT发射极与所述IGBT栅极短接,并使得电流下降。
进一步的,所述阈值电压的值为3V-5V。
进一步的,所述衬底包括相对的第一面和第二面,所述IGBT发射极、IGBT栅极和所述NMOS管的栅极设置于所述衬底的第一面,所述IGBT集电极设置于所述衬底的第二面,或/及所述IGBT器件还包括场截止层,设置于所述衬底中,并靠近所述IGBT集电极设置。
注意,上述仅为本发明的较佳实施例及所运用技术原理。本领域技术人员会理解,本发明不限于这里所述的特定实施例,对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本发明的保护范围。因此,虽然通过以上实施例对本发明进行了较为详细的说明,但是本发明不仅仅限于以上实施例,在不脱离本发明构思的情况下,还可以包括更多其他等效实施例,而本发明的范围由所附的权利要求范围决定。

Claims (9)

1.一种IGBT器件,其特征在于,包括:
衬底,所述衬底上形成有IGBT器件的IGBT发射极、IGBT栅极和IGBT集电极;
NMOS管,所述NMOS管设置于所述衬底上,且设置于所述IGBT栅极和所述IGBT发射极之间,所述NMOS管的漏极与所述IGBT栅极电性连接,所述NMOS管的栅极和源极与所述IGBT发射极电性连接,所述NMOS管的栅极和所述IGBT发射极之间连接有电阻;
当所述IGBT器件短路时,所述IGBT发射极施加阈值电压,所述阈值电压同时施加于所述NMOS管的栅极以使所述NMOS管导通,从而使所述IGBT发射极与所述IGBT栅极短接,并使得电流下降;
所述衬底包括相对的第一面和第二面,所述IGBT发射极、IGBT栅极和所述NMOS管的栅极设置于所述衬底的第一面,所述IGBT集电极设置于所述衬底的第二面,或/及所述IGBT器件还包括场截止层,设置于所述衬底中,并靠近所述IGBT集电极设置。
2.根据权利要求1所述的IGBT器件,其特征在于,所述阈值电压的值为3V-5V。
3.根据权利要求1所述的IGBT器件,其特征在于,所述IGBT栅极与IGBT栅极总线电性连接,所述IGBT栅极总线设置为环形并且环绕于所述IGBT发射极外围。
4.一种IGBT器件的制备方法,其特征在于,包括下列步骤:
提供一衬底,于所述衬底上形成IGBT器件的IGBT发射极、IGBT栅极、IGBT集电极;
于所述衬底上设置NMOS管,所述NMOS管置于所述IGBT栅极和所述IGBT发射极之间,所述NMOS管的漏极与所述IGBT栅极电性连接,所述NMOS管的栅极和源极与所述IGBT发射极电性连接,所述NMOS管的栅极和所述IGBT发射极之间连接有电阻。
5.根据权利要求4所述的IGBT器件的制备方法,其特征在于,
于所述衬底上设置NMOS管包括下列步骤:
通过离子注入工艺于所述衬底中形成P阱;
于所述衬底上形成栅介质层和栅极层,并通过图形化工艺形成IGBT栅极和NMOS管的栅极;
通过离子注入工艺于所述P阱中形成NMOS管的源极和漏极;
于所述衬底上形成绝缘层,于所述绝缘层中形成接触孔,于所述接触孔和所述绝缘层上形成金属层,并通过图形化工艺形成布线层,通过所述接触孔和所述布线层,使得所述NMOS管的漏极与所述IGBT栅极电性连接,所述NMOS管源极与所述IGBT发射极电性连接,所述NMOS管的栅极与接触点电性连接。
6.根据权利要求5所述的IGBT器件的制备方法,其特征在于,还包括步骤:通过外部管脚于所述NMOS管的栅极的接触点和所述IGBT发射极之间接入电阻。
7.根据权利要求6所述的IGBT器件的制备方法,其特征在于,当所述IGBT器件短路时,所述IGBT发射极施加阈值电压,所述阈值电压同时施加于所述NMOS管的栅极以使所述NMOS管导通,从而使所述IGBT发射极与所述IGBT栅极短接,并使得电流下降。
8.根据权利要求7所述的IGBT器件的制备方法,其特征在于,所述阈值电压的值为3V-5V。
9.根据权利要求4所述的IGBT器件的制备方法,其特征在于,所述衬底包括相对的第一面和第二面,所述IGBT发射极、IGBT栅极和所述NMOS管的栅极设置于所述衬底的第一面,所述IGBT集电极设置于所述衬底的第二面,或/及所述IGBT器件还包括场截止层,设置于所述衬底中,并靠近所述IGBT集电极设置。
CN202311266836.1A 2023-09-28 2023-09-28 一种igbt器件及其制备方法 Active CN116995092B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311266836.1A CN116995092B (zh) 2023-09-28 2023-09-28 一种igbt器件及其制备方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311266836.1A CN116995092B (zh) 2023-09-28 2023-09-28 一种igbt器件及其制备方法

Publications (2)

Publication Number Publication Date
CN116995092A true CN116995092A (zh) 2023-11-03
CN116995092B CN116995092B (zh) 2023-12-05

Family

ID=88528785

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311266836.1A Active CN116995092B (zh) 2023-09-28 2023-09-28 一种igbt器件及其制备方法

Country Status (1)

Country Link
CN (1) CN116995092B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117199120A (zh) * 2023-11-07 2023-12-08 上海功成半导体科技有限公司 Igbt器件结构及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102931960A (zh) * 2012-10-24 2013-02-13 华为技术有限公司 Igbt保护方法及保护电路
CN110854186A (zh) * 2019-12-09 2020-02-28 安徽瑞迪微电子有限公司 Igbt器件结构及其制备方法
KR20220026069A (ko) * 2020-08-25 2022-03-04 (주) 트리노테크놀로지 쇼트서킷 내량이 강화된 전력 반도체 소자
CN115985955A (zh) * 2023-02-06 2023-04-18 北京大学 一种低关断损耗的igbt开关器件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102931960A (zh) * 2012-10-24 2013-02-13 华为技术有限公司 Igbt保护方法及保护电路
CN110854186A (zh) * 2019-12-09 2020-02-28 安徽瑞迪微电子有限公司 Igbt器件结构及其制备方法
KR20220026069A (ko) * 2020-08-25 2022-03-04 (주) 트리노테크놀로지 쇼트서킷 내량이 강화된 전력 반도체 소자
CN115985955A (zh) * 2023-02-06 2023-04-18 北京大学 一种低关断损耗的igbt开关器件

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117199120A (zh) * 2023-11-07 2023-12-08 上海功成半导体科技有限公司 Igbt器件结构及其制备方法
CN117199120B (zh) * 2023-11-07 2024-01-23 上海功成半导体科技有限公司 Igbt器件结构及其制备方法

Also Published As

Publication number Publication date
CN116995092B (zh) 2023-12-05

Similar Documents

Publication Publication Date Title
CN116995092B (zh) 一种igbt器件及其制备方法
US10193250B2 (en) Substrate and terminals for power module and power module including the same
JP4450530B2 (ja) インバータモジュール
CN204442051U (zh) 电力转换装置内置型电动机、空调机、热水器及换气鼓风设备
CN1758522A (zh) 逆变器装置以及使用它的车辆驱动装置
CN109817612B (zh) 一种改善焊接型碳化硅功率模块电热性能的封装结构
JP5235443B2 (ja) トレンチゲート型半導体装置
CN105161491A (zh) 一种集成栅级驱动功率器件及其制备方法
CN102024814B (zh) Mos-栅功率半导体器件
CN220753430U (zh) 集成器件、电子电路、电路板和空调器
CN109768039A (zh) 一种双面散热功率模块
JP4944847B2 (ja) トレンチゲート型絶縁ゲートバイポーラトランジスタ
WO2021175130A1 (zh) 一种快速功率模块及功率模组
CN117012773B (zh) 一种igbt器件及其制备方法
CN106298737B (zh) 功率模块封装结构及其制造方法
WO2017199580A1 (ja) 絶縁ゲート型半導体装置及び絶縁ゲート型半導体装置の製造方法
CN113725209B (zh) 一种SiC/Si Cascode器件用多芯片并联结构
CN109585436A (zh) 一种穿插分支布局的功率模块
CN103730460A (zh) 一种超结功率器件版图结构及制作方法
CN110190114B (zh) 一种栅控双极-场效应复合碳化硅垂直双扩散金属氧化物半导体晶体管
CN113314345A (zh) 一种新型电极电容及功率模组
CN117238897B (zh) Igbt器件结构及其制备方法
CN105789160A (zh) 一种组合式电极及其三电平大功率模块
CN218827132U (zh) 一种增强型功率模块及功率模组
CN218918849U (zh) 集成式碳化硅功率单元

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant