CN1166071C - 数据存储通道编码器的编码方法 - Google Patents
数据存储通道编码器的编码方法 Download PDFInfo
- Publication number
- CN1166071C CN1166071C CNB998168777A CN99816877A CN1166071C CN 1166071 C CN1166071 C CN 1166071C CN B998168777 A CNB998168777 A CN B998168777A CN 99816877 A CN99816877 A CN 99816877A CN 1166071 C CN1166071 C CN 1166071C
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- code word
- parity
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10046—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter
- G11B20/10055—Improvement or modification of read or write signals filtering or equalising, e.g. setting the tap weights of an FIR filter using partial response filtering when writing the signal to the medium or reading it therefrom
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/31—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining coding for error detection or correction and efficient use of the spectrum
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
- H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/6331—Error control coding in combination with equalisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/6343—Error control coding in combination with techniques for partial response channels, e.g. recording
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/04—Conversion to or from representation by pulses the pulses having two levels
- H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
- H03M5/145—Conversion to or from block codes or representations thereof
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
- G11B2020/1446—16 to 17 modulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Signal Processing (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Error Detection And Correction (AREA)
Abstract
Description
Xm_Yn Xm_Yn000_1000 100_0100001_0001 101_0101010_0010 110_0110011_1001 111_1010 |
Xm_Yn,Zn,Zn+1 Xm_Yn,Zn,Zn+1000_100010 100_010001001_000101 101_010110010_001010 110_011001011_100101 111_101010 |
Claims (9)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14162299P | 1999-06-30 | 1999-06-30 | |
US60/141,622 | 1999-06-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1367953A CN1367953A (zh) | 2002-09-04 |
CN1166071C true CN1166071C (zh) | 2004-09-08 |
Family
ID=22496477
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB998168777A Expired - Fee Related CN1166071C (zh) | 1999-06-30 | 1999-12-31 | 数据存储通道编码器的编码方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US6388587B1 (zh) |
JP (1) | JP2003504778A (zh) |
KR (1) | KR100472524B1 (zh) |
CN (1) | CN1166071C (zh) |
DE (1) | DE19983965T1 (zh) |
GB (1) | GB2366708B (zh) |
WO (1) | WO2001003304A1 (zh) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6643814B1 (en) * | 1999-07-12 | 2003-11-04 | International Business Machines Corporation | Maximum transition run encoding and decoding systems |
US6662338B1 (en) * | 1999-09-30 | 2003-12-09 | Stmicroelectronics, Inc. | Parity- sensitive Viterbi detector and method for recovering information from a read signal |
US6526530B1 (en) * | 1999-12-22 | 2003-02-25 | Marvell International, Ltd. | Method and apparatus for encoding data incorporating check bits and maximum transition run constraint |
US6965636B1 (en) * | 2000-02-01 | 2005-11-15 | 2Wire, Inc. | System and method for block error correction in packet-based digital communications |
US6574773B1 (en) * | 2000-03-09 | 2003-06-03 | Stephen A. Turk | Cost-effective high-throughput enumerative ENDEC employing a plurality of segmented compare tables |
US6581184B1 (en) * | 2000-04-11 | 2003-06-17 | Texas Instruments Incorporated | Method and circuit for including parity bits in write data of a mass data storage device, or the like, using a 48/54 mtr (3:k) code constraint, and post-processing circuit and method for processing read back data that includes said code constraint |
US20020172305A1 (en) * | 2000-11-24 | 2002-11-21 | Younggyun Kim | Fixed decision delay detectors for timing recovery loop |
WO2002080373A1 (en) * | 2001-03-30 | 2002-10-10 | Koninklijke Philips Electronics N.V. | Methods and devices for converting as well as decoding a stream of data bits, signal and record carrier |
US6788223B2 (en) * | 2002-09-25 | 2004-09-07 | Infineon Technolgies Na Corp. | High rate coding for media noise |
WO2005020440A1 (en) * | 2003-08-13 | 2005-03-03 | Seagate Technology Llc | Dc-free code design with increased distance between code words |
KR100559730B1 (ko) * | 2003-09-22 | 2006-03-15 | 삼성전자주식회사 | 기록 시스템을 위한 데이터 부호화/복호화 방법 및 장치 |
US7191386B2 (en) * | 2004-06-29 | 2007-03-13 | Seagate Technology Llc | Method and apparatus for additive trellis encoding |
US7164371B2 (en) * | 2004-07-30 | 2007-01-16 | Hitachi Global Storage Technologies Netherlands B.V. | Method and apparatus for data coding for high density recording channels exhibiting low frequency contents |
US7496153B2 (en) * | 2004-10-14 | 2009-02-24 | Mitsubishi Electric Research Laboratories, Inc. | Modulating signals for coherent and differentially coherent receivers |
JP5011116B2 (ja) * | 2004-10-26 | 2012-08-29 | エージェンシー フォー サイエンス,テクノロジー アンド リサーチ | 変調の制約及び誤り制御を用いて情報の符号化及び復号化を実行する方法及びシステム |
US7126502B2 (en) * | 2005-02-01 | 2006-10-24 | Hitachi Global Storage Technologies Netherlands B.V. | Techniques for using interleaved encoders to obtain modulation constraints |
JP4571580B2 (ja) * | 2005-12-15 | 2010-10-27 | 富士通株式会社 | 復号器 |
KR20070077603A (ko) * | 2006-01-24 | 2007-07-27 | 삼성전자주식회사 | 비터비 디코딩 방법 및 비터비 디코더 |
JP2007242066A (ja) * | 2006-03-03 | 2007-09-20 | Fujitsu Ltd | Mtr符号化方法、mtr復号方法、mtr符号器、mtr復号器及び磁気記録装置 |
US8276038B2 (en) * | 2007-08-03 | 2012-09-25 | International Business Machines Corporation | Data storage systems |
US7616134B1 (en) * | 2008-06-19 | 2009-11-10 | International Business Machines Corporation | Systems and methods for enumerative encoding and decoding of maximum-transition-run codes and PRML (G,I,M) codes |
KR101757452B1 (ko) * | 2010-01-08 | 2017-07-13 | 삼성전자주식회사 | 무선 통신 시스템에서 자원 매핑 및 디매핑 방법 및 장치 |
RU2012152710A (ru) * | 2012-12-06 | 2014-06-20 | ЭлЭсАй Корпорейшн | Модуляционное кодирование битов четности, сформированных с использованием кода с исправлением ошибок |
WO2015107571A1 (ja) * | 2014-01-17 | 2015-07-23 | パナソニックIpマネジメント株式会社 | 復号装置および復号方法、記録再生装置および記録再生方法 |
EP2958238A1 (en) * | 2014-06-17 | 2015-12-23 | Thomson Licensing | Method and apparatus for encoding information units in code word sequences avoiding reverse complementarity |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5537112A (en) | 1994-01-12 | 1996-07-16 | Seagate Technology, Inc. | Method and apparatus for implementing run length limited codes in partial response channels |
US5576707A (en) * | 1994-06-10 | 1996-11-19 | Cirrus Logic, Inc. | Method and apparatus for detecting and decoding data in a PRML class-IV digital communication channel |
US5731768A (en) | 1996-01-31 | 1998-03-24 | Seagate Technology, Inc. | Method and apparatus for implementing codes with maximum transition run length |
US5859601A (en) | 1996-04-05 | 1999-01-12 | Regents Of The University Of Minnesota | Method and apparatus for implementing maximum transition run codes |
US5949357A (en) | 1997-01-13 | 1999-09-07 | Quantum Corporation | Time-varying maximum-transition-run codes for data channels |
US6011497A (en) * | 1997-04-01 | 2000-01-04 | Seagate Technology, Inc. | Location dependent maximum transition run length code with alternating code word length and efficient K constraint |
DE19882279T1 (de) * | 1997-04-01 | 2000-02-24 | Seagate Technology | Code mit Maximal-Übergangslauflänge |
US5936558A (en) * | 1997-05-14 | 1999-08-10 | Seagate Technology, Inc. | Signal space detector for channels utilizing a code having time varying constraints |
US6081210A (en) * | 1998-05-13 | 2000-06-27 | Texas Instruments Incorporated | Sliding block (rate 8/9) trellis code for magnetic recording |
-
1999
- 1999-12-31 KR KR10-2001-7016810A patent/KR100472524B1/ko not_active IP Right Cessation
- 1999-12-31 DE DE19983965T patent/DE19983965T1/de not_active Withdrawn
- 1999-12-31 GB GB0130127A patent/GB2366708B/en not_active Expired - Fee Related
- 1999-12-31 CN CNB998168777A patent/CN1166071C/zh not_active Expired - Fee Related
- 1999-12-31 US US09/476,629 patent/US6388587B1/en not_active Expired - Lifetime
- 1999-12-31 JP JP2001508602A patent/JP2003504778A/ja active Pending
- 1999-12-31 WO PCT/US1999/031199 patent/WO2001003304A1/en active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
GB2366708A (en) | 2002-03-13 |
CN1367953A (zh) | 2002-09-04 |
JP2003504778A (ja) | 2003-02-04 |
DE19983965T1 (de) | 2002-08-01 |
GB2366708B (en) | 2003-11-12 |
US6388587B1 (en) | 2002-05-14 |
KR20020015360A (ko) | 2002-02-27 |
KR100472524B1 (ko) | 2005-03-09 |
WO2001003304A1 (en) | 2001-01-11 |
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C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C06 | Publication | ||
PB01 | Publication | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CI01 | Publication of corrected invention patent application |
Correction item: Denomination of Invention Correct: Data storage channel encoder and coding method False: Encoding method for data storage channel encoder Number: 36 Page: 511 Volume: 20 |
|
CI03 | Correction of invention patent |
Correction item: Denomination of Invention Correct: Data storage channel encoder and coding method False: Encoding method for data storage channel encoder Number: 36 Page: The title page Volume: 20 |
|
COR | Change of bibliographic data |
Free format text: CORRECT: INVENTION NAME; FROM: DATA STORAGE CHANNEL ENCODER CODING METHOD TO: DATA SAVING CHANNEL DECODER AND DECODING METHOD |
|
ERR | Gazette correction |
Free format text: CORRECT: INVENTION NAME; FROM: DATA STORAGE CHANNEL ENCODER CODING METHOD TO: DATA SAVING CHANNEL DECODER AND DECODING METHOD |
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C56 | Change in the name or address of the patentee |
Owner name: SEAGATE TECHNOLOGY SCIENCE & TECHNOLOGY CO., LTD. Free format text: FORMER NAME OR ADDRESS: SEAGATE TECHNOLOGY LLC |
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CP03 | Change of name, title or address |
Address after: American California Patentee after: Seagate Technology LLC Address before: American California Patentee before: Seagate Technology, Inc. |
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CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040908 Termination date: 20141231 |
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EXPY | Termination of patent right or utility model |