CN116469779A - 一种三维封装的层间互连方法及结构 - Google Patents
一种三维封装的层间互连方法及结构 Download PDFInfo
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- 239000011229 interlayer Substances 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 189
- 229910052751 metal Inorganic materials 0.000 claims abstract description 71
- 239000002184 metal Substances 0.000 claims abstract description 71
- 238000004806 packaging method and process Methods 0.000 claims abstract description 33
- 239000010410 layer Substances 0.000 claims abstract description 32
- 238000001465 metallisation Methods 0.000 claims abstract description 15
- 230000008569 process Effects 0.000 claims abstract description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 20
- 229910052737 gold Inorganic materials 0.000 claims description 20
- 239000010931 gold Substances 0.000 claims description 20
- 229910000679 solder Inorganic materials 0.000 claims description 18
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 14
- DGAHKUBUPHJKDE-UHFFFAOYSA-N indium lead Chemical compound [In].[Pb] DGAHKUBUPHJKDE-UHFFFAOYSA-N 0.000 claims description 14
- 230000008018 melting Effects 0.000 claims description 11
- 238000002844 melting Methods 0.000 claims description 11
- 238000007747 plating Methods 0.000 claims description 10
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 9
- 238000012360 testing method Methods 0.000 claims description 9
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 8
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 229910000978 Pb alloy Inorganic materials 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000005476 soldering Methods 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 238000003466 welding Methods 0.000 claims description 4
- FRWYFWZENXDZMU-UHFFFAOYSA-N 2-iodoquinoline Chemical compound C1=CC=CC2=NC(I)=CC=C21 FRWYFWZENXDZMU-UHFFFAOYSA-N 0.000 claims description 3
- SWPMTVXRLXPNDP-UHFFFAOYSA-N 4-hydroxy-2,6,6-trimethylcyclohexene-1-carbaldehyde Chemical compound CC1=C(C=O)C(C)(C)CC(O)C1 SWPMTVXRLXPNDP-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- LTPBRCUWZOMYOC-UHFFFAOYSA-N beryllium oxide Inorganic materials O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 3
- 230000005496 eutectics Effects 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 239000010453 quartz Substances 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 239000011148 porous material Substances 0.000 claims description 2
- 230000008901 benefit Effects 0.000 abstract description 4
- 238000004377 microelectronic Methods 0.000 abstract description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 239000011651 chromium Substances 0.000 description 3
- 239000005022 packaging material Substances 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 229910001128 Sn alloy Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910001152 Bi alloy Inorganic materials 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- 229910001245 Sb alloy Inorganic materials 0.000 description 1
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- 239000002140 antimony alloy Substances 0.000 description 1
- GVFOJDIFWSDNOY-UHFFFAOYSA-N antimony tin Chemical compound [Sn].[Sb] GVFOJDIFWSDNOY-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- JWVAUCBYEDDGAD-UHFFFAOYSA-N bismuth tin Chemical compound [Sn].[Bi] JWVAUCBYEDDGAD-UHFFFAOYSA-N 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 229910000833 kovar Inorganic materials 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000010979 ruby Substances 0.000 description 1
- 229910001750 ruby Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910001174 tin-lead alloy Inorganic materials 0.000 description 1
- 229910000969 tin-silver-copper Inorganic materials 0.000 description 1
- MTPVUVINMAGMJL-UHFFFAOYSA-N trimethyl(1,1,2,2,2-pentafluoroethyl)silane Chemical compound C[Si](C)(C)C(F)(F)C(F)(F)F MTPVUVINMAGMJL-UHFFFAOYSA-N 0.000 description 1
- UONOETXJSWQNOL-UHFFFAOYSA-N tungsten carbide Chemical compound [W+]#[C-] UONOETXJSWQNOL-UHFFFAOYSA-N 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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Abstract
本发明涉及微电子封装技术领域,旨在解决现有的层间互连方法将层间互连后存在互连间隙的问题,提供一种三维封装的层间互连方法及结构;其中,层间互连方法包括准备基板和围框,在基板上需要实现层间互连的地方加工互连通孔、键合焊盘,互连通孔内壁进行金属化处理,在互连通孔中设置金属球,采用超声波键合金属球,使其发生变形将上下两层基板实现互连,依次堆叠基板并使用金属球进行互连,将堆叠互连后的基板封装在围框中,封装后基板之间几乎不存在间隙,有效解决了封装的层间互连间隙问题;层间互连结构采用上述层间互连方法得到;本发明互连基板的过程简单、操作便捷、互连温度低、互连后的层间间隙小,特加适合封装高频器件和热敏感器件。
Description
技术领域
本发明涉及微电子封装技术领域,具体而言,涉及一种三维封装的层间互连方法及结构。
背景技术
在微电子封装技术领域,封装的发展趋势向小型化、高集成度方向持续迈进,诸如手机、穿戴设备、传感器等都优先采用三维封装技术,在减少封装体积的同时,提高了集成度,增加更多功能。
三维封装主要有芯片级三维封装和多层板堆叠三维封装两种类型,芯片级三维封装是将同种或异种半导体芯片在空间上进行多次堆叠实现封装,多层堆叠板三维封装是将组装过芯片、元器件的多层板在空间上进行多次堆叠封装。不管是芯片级三维封装还是多层板堆叠三维封装都要实现层间的互连。
目前的层间互连技术主要有BGA层间互连、预制金属凸点的超声波键合互连、TSV互连等。
BGA层间互连应用广泛,技术也最成熟,专利CN201811574127公开了一种BGA层间互连的微带天线,层间互连后,每个层间会存在一个互连间隙,对封装空间造成浪费,对高频率器件封装存在插入损耗大等问题。
预制金属凸点的超声波键合互连,专利CN202210669029.3公开了一种预制金属凸点,然后采用超声波键合,使上下金属凸点键合互连,实现层间互连的方法。这种预制金属凸点的超声波键合也存在互连层间间隙,面对大面积键合时,容易出现部分凸点键合不上,部分凸点又键合变形过大等情况。
TSV互连即硅通孔互连,专利CN202211068311.2公开了采用若干个TSV转接板实现层间互连的结构,层间同样采用了预制金属凸点,然后采用超声波键合实现互连。这种结构同样存在互连后的层间间隙,面对大面积的三维封装,也容易出现部分凸点键合不上,部分凸点又键合变形过大等情况。封装的层间又加了很多层TSV转接板,封装空间利用率不高。
发明内容
本发明旨在提供一种三维封装的层间互连方法及结构,以解决现有的层间互连方法将层间互连后存在互连间隙的问题。
在复杂三维封装的实际应用中,通常会将多种封装材料和组装工艺混用,以达到封装的目的,通常这些封装材料和组装工艺的温度耐受程度完全不一样。为了更好兼容各种封装材料和组装工艺,必须寻找到一种封装温度更低、操作更简便的封装手段,适合三维封装的实际需要。
本发明提供一种三维封装的层间互连方法,包括以下步骤:
S1:准备多块基板和一个围框,基板上开设有内埋器件通孔和互连通孔,基板上制备有对应电路和互连焊盘,互连通孔内壁设有金属化层;
S2:将各块基板分别进行微组装,组装过程包括粘片、芯片倒装键合、引线键合、功能指标测试步骤,合格后将各块基板按顺序放在一侧备用;
S3:选取一块基板作为起始堆叠板,将其放入限位夹具,然后在起始堆叠板上放置第二块基板,调整限位夹具,将上层基板的互连通孔与下层基板的互连焊盘对齐,并将两块基板压紧;
S4:将金属球依次放入上层基板的互连通孔中,仔细检查并确保每个互连通孔里都有一枚金属球;
S5:将堆叠设置的基板放在超声波键合机工作台上,采用专用的键合劈刀,调整好键合参数,依次将各个金属球压扁变形,此时,所有变形的金属球将上下两块基板互连,变形后的金属球底面与下层基板的互连焊盘互连,变形后的金属球侧面与上层基板互连通孔内壁的金属化层互连;
S6:参照S3~S5的步骤,重复操作,将剩下的基板依次堆叠实现互连;
S7:将堆叠好的多层三维封装产品装入围框,在产品侧面与围框的缝隙里装上软钎料B,放入真空共晶炉加热,软钎料B熔化填满缝隙完成围框与产品的焊接;
S8:将焊完围框的产品放在网板下,对产品上下两个面分别印刷软钎料A;
S9:将产品放入回流炉中将软钎料A形成的金属凸块加热形成球形,最后进行清洗;
S10:将产品放入测试夹具进行测试,合格后抽真空包装入库。
作为优选的技术方案:
S1具体包括:
S11:准备多块基板,根据电路结构对各个基板进行开孔,在基板上需要设置内埋器件的位置开设内埋器件通孔,在基板上需要进行互连的位置开设互连通孔,然后根据电路结构在基板上制备对应电路和互连焊盘,过程中对互连通孔内壁与基板外侧进行镀金;
S12:准备一个金属围框,加工围框时对围框的外侧进行倒角,围框的内侧镀镍金,外侧镀镍。
作为优选的技术方案:
S11还包括:在基板的表面和底面四周布置接地焊盘。
作为优选的技术方案:
S5中,在键合时键合温度不超过150℃,每次只键合一个金属球。
作为优选的技术方案:
S7中,在产品侧面与围框的缝隙里装上熔点为220度的铟铅合金。
作为优选的技术方案:
S8中,对产品上下两个面分别印刷熔点为185℃的铟铅焊膏;
S9中,将产品放入210度的回流炉中将铟铅焊膏形成的金属凸块加热形成球形。
本发明进一步提供一种三维封装的层间互连结构,采用上述三维封装的层间互连方法得到。
作为优选的技术方案:
层间互连结构包括多块层叠设置的基板,基板上需要设置内埋器件的位置开设有内埋器件通孔,基板需要与另一基板进行互连的位置开设有互连通孔,基板的表面和底面根据电路结构制备有对应电路和互连焊盘,互连通孔内壁设置有金属化层;
上层基板的互连通孔与下层基板的互连焊盘相对齐,互连通孔内设置有金属球,金属球被超声波键合机压扁变形,所有变形的金属球将上下两块基板互连,变形后的金属球底面与下层基板的互连焊盘互连,变形后的金属球侧面与上层基板互连通孔内壁的金属化层互连;
堆叠完成之后的基板装配在围框中,基板与围框固定连接。
作为优选的技术方案:
基板可以采用FR-4基板、氧化铝基板、氧化锆基板、氧化铍基板、氮化铝基板、硅基板、石英基板、玻璃基板、LCP基板、LTCC基板或HTCC基板。
作为优选的技术方案:
基板的厚度为0.1~5毫米,互连通孔的直径为0.05~2毫米。
作为优选的技术方案:
互连焊盘直径为0.06~2毫米。
作为优选的技术方案:
金属球的直径为0.04~1.9毫米。
综上所述,由于采用了上述技术方案,本发明的有益效果是:
本发明在基板上需要实现层间互连的地方加工互连通孔、键合焊盘,互连通孔内壁进行金属化处理,在互连通孔中设置金属球,采用超声波键合金属球,使其发生变形将上下两层基板实现互连,封装后基板之间几乎不存在间隙,有效解决了封装的层间互连间隙问题,采用每个键合点单独键合的方式,解决了像预制金属凸点在大面积键合时键合不良的问题,同时具有较好的低温封装优势。
本发明互连基板的过程简单、操作便捷、互连温度低、互连后的层间间隙小,特加适合封装高频器件和热敏感器件。
附图说明
图1为本发明所述的三维封装的层间互连结构的结构示意图。
图2为图1中A处的放大图。
图3为金属球的键合过程示意图。
图标:1-基板,2-金属球,3-软钎料A,4-互连通孔,5-倒装键合球,6-内埋芯片,7-键合引线,8-互连通孔金属化层,9-键合劈刀,10-软钎料B,11-围框。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合附图对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
实施例1
如图1和图2所示,本实施例提出一种三维封装的层间互连结构,该结构包括至少两层基板1,所述基板1层叠设置,所述基板1上根据电路结构开设有孔。具体的,所述基板1上需要设置内埋器件的位置开设有内埋器件通孔,所述基板1需要与另一基板1进行互连的位置开设有互连通孔4。图1中,标号6为内埋芯片,标号7为键合引线,标号5为倒装键合球,由于有些芯片是正装芯片,通常采用引线键合,有些芯片是倒装芯片,通常使用金属球超声键合或者使用焊料球加热焊接实现,倒装键合球5是倒装芯片的互连球。
所述基板1可以采用FR-4基板、氧化铝基板、氧化锆基板、氧化铍基板、氮化铝基板、硅基板、石英基板、玻璃基板、LCP基板、LTCC基板、或HTCC基板;所述基板1的厚度为0.1~5毫米。在本实施例中,所述基板1采用厚度为0.38毫米的氧化铝陶瓷基板,共采用7块所述基板1,所有所述基板1层叠设置。
所述基板1的表面和底面根据电路结构制备有对应电路和互连焊盘,所述电路的材料可以为金、银、铜或铝,在所述基板1表面形成镀层。所述互连焊盘的材料可以为金、银、铜、铂、铝、镍、铬、铟、锡的单一金属及其合金。所述互连通孔4的内壁以及所述基板1的外侧设置有金属化层,所述金属化层的材料可以为金、银、铜、铂、铝、镍、铬、铟、锡的单一金属及其合金。图2和图3中标号8为互连通孔金属化层。所述互连通孔4内壁金属与所述互连焊盘金属一致。在本实施例中,所述互连通孔4的内壁以及所述基板1的外侧镀有金层,镀金厚度为4微米。所述基板1的表面和底面四周还布设有接地焊盘、宽度为0.1~5毫米。
将最下方的一块基板1作为起始堆叠板,然后在所述起始堆叠板上面放置第二块基板1,将第二块基板1与所述起始堆叠板互连,按此方式依次堆叠连接多块基板1。相邻两块基板1按照如下方式进行连接:首先将一块基板1作为下层基板1放置到位,在下层基板1的上方放置另一块基板1作为上层基板1,通过限位夹具将上层基板1上的互连通孔4与所述下层基板1上的互连焊盘对齐,并将两块基板1压紧,在上层基板1的互连通孔4中放置金属球,通过专用的键合劈刀9将所述互连通孔4中的金属球2压扁变形,所有变形的金属球2将上下两块基板1实现了互连,变形后的金属球2底面与下层基板1的互连焊盘互连,变形后的金属球2侧面与上层基板1互连通孔4内壁的金属化层互连,采用上述方式,从下至上依次将各块基板1相连,实现多层基板1的堆叠互连,且层间的互连间隙极小。
所述互连焊盘与所述互连通孔4的位置相对应,所述互连通孔4与所述互连焊盘的形状相适配,所述互连焊盘的尺寸大于或等于所述互连通孔4的尺寸,所述互连通孔4的形状可以为圆形或多边形,所述互连焊盘形状也可以为圆形或多边形。当所述互连通孔4的形状为圆形时,所述互连焊盘与所述互连通孔4的误差不超过所述互连通孔4直径的10%。所述互连通孔4的直径为0.05~2毫米,所述互连焊盘直径为0.06~2毫米。根据互连通孔4的直径加工金属球,所述金属球直径略小于所述互连通孔4的直径,所述金属球的直径通常为所述互连通孔4的直径的85~95%,便于互连时容易将金属球放入互连通孔4中。所述金属球的直径为0.04~1.9毫米,所述金属球的材料可以为金、银、铜、铂、铝、镍、铬、铟、锡的单一金属及其合金。在本实施例中,所述互连通孔4的直径为0.25毫米,所述金属球采用金球,所述金球的直径为0.2毫米。所述键合劈刀9端头为圆柱体或多面柱体,所述键合劈刀9的端头尺寸为0.03~1.8毫米,所述键合劈刀9材质可以为碳化钨硬质合金、碳化钛硬质合金、氧化铝陶瓷、氧化锆陶瓷、金属陶瓷、红宝石油石。
堆叠固定连接好的多层基板1作为三维封装产品装配在围框11中。在本实施例中,所述围框11采用金属围框,高度2.6毫米,厚度0.5毫米,所述围框11的内侧镀镍金,外侧镀镍。所述产品的侧面与所述围框11之间的缝隙中填满软钎料A3,所述产品的侧面与所述围框11焊接。焊完围框11的产品的顶面和底面分别印刷有软钎料B10。软钎料的熔点为120~400℃,软钎料可以为纯锡、锡铅合金、锡铋合金、锡银铜合金、锡锑合金、金锡合金、金锗合金、纯铟、铟铅合金、铟锡合金。在本实施例中,所述产品的侧面与所述围框11之间的缝隙中填满铟铅合金,所述产品的侧面与所述围框11焊接。焊完围框11的产品的顶面和底面分别印刷有熔点为185℃的铟铅焊膏,在210℃的回流炉中将产品顶面和底面印刷铟铅焊膏形成的金属凸块加热形成球形。
本实施例进一步提出一种三维封装的层间互连方法,包括以下步骤:
S1:准备基板1和围框11:
S11:准备7块厚度为0.38毫米的氧化铝陶瓷基板,根据电路结构对各个基板1进行开孔,在基板1上需要设置内埋器件的位置开设内埋器件通孔,在基板1上需要进行互连的位置开设互连通孔4,互连通孔4的直径为0.25毫米,然后根据电路结构在基板1上制备对应电路和互连焊盘,过程中对互连通孔4内壁与基板1外侧进行镀金,镀金厚度为4微米;
S12:准备一个金属围框11,围框11的材质采用柯伐合金4J34,加工围框11时对围框11的外侧进行倒角,围框11的高度为2.6毫米,厚度为0.5毫米,围框11的内侧镀镍金,外侧镀镍;
S2:将采用薄膜工艺加工而成的氧化铝陶瓷基板分别进行微组装,组装过程包括粘片、芯片倒装键合、引线键合、功能指标测试等步骤,合格后将各块基板1按顺序放在一侧备用;
S3:选取一块氧化铝陶瓷基板作为起始堆叠板,将其放入限位夹具,然后在起始堆叠板上放置第二块氧化铝陶瓷基板1,调整限位夹具,将上层基板1的互连通孔4与下层基板1的互连焊盘对齐,并将两块基板1压紧;
S4:将直径为0.2毫米的金球依次放入上层基板1的互连通孔4中,仔细检查并确保每个互连通孔4里都有一枚金球;
S5:如图3所示,将堆叠设置的基板1放在超声波键合机工作台上,采用专用的键合劈刀9,调整好键合参数,依次将各个金球压扁变形,此时,所有变形的金球将上下两块基板1互连,变形后的金球底面与下层基板1的互连焊盘互连,变形后的金球侧面与上层基板1互连通孔4内壁的金属化层互连,上下两块基板1间的总结合强度与板间的互连点数呈线性关系;在键合时,键合温度最高不超过150℃,每次只键合一个金球,保证每个金球都能键合到位;
S6:参照S3~S5的步骤,重复操作,将剩下的5片基板1依次堆叠实现互连;
S7:将堆叠好的多层陶瓷三维封装产品装入围框11,在产品侧面与围框11的缝隙里装上熔点为220度的铟铅合金,放入真空共晶炉加热,铟铅合金熔化填满缝隙完成围框11与产品的焊接;
S8:将焊完围框11的产品放在网板下,对产品上下两个面分别印刷熔点为185℃的铟铅焊膏;
S9:将产品放入210度的回流炉中将铟铅焊膏形成的金属凸块加热形成球形,最后进行清洗;
S10:将产品放入测试夹具进行测试,合格后抽真空包装入库。
实施例2
本实施例与实施例1的区别在于:不限于采用超声波将金属球键合变形,还可以采用热压键合工艺实现金属球键合变形,两种工艺键合后的互连效果都很不错。对小球径(通常小于300微米)的金属球尽可能采用超声波键合,因为超声波键合的劈刀端头可以加工得更小,对大球径的金属球,超声波键合和热压键合都能够取得很好的互连效果。
以上所述仅为本发明的优选实施例而已,并不用于限制本发明,对于本领域的技术人员来说,本发明可以有各种更改和变化。凡在本发明的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (10)
1.一种三维封装的层间互连方法,其特征在于:
包括以下步骤:
S1:准备多块基板和一个围框,基板上开设有内埋器件通孔和互连通孔,基板上制备有对应电路和互连焊盘,互连通孔内壁设有金属化层;
S2:将各块基板分别进行微组装,组装过程包括粘片、芯片倒装键合、引线键合、功能指标测试步骤,合格后将各块基板按顺序放在一侧备用;
S3:选取一块基板作为起始堆叠板,将其放入限位夹具,然后在起始堆叠板上放置第二块基板,调整限位夹具,将上层基板的互连通孔与下层基板的互连焊盘对齐,并将两块基板压紧;
S4:将金属球依次放入上层基板的互连通孔中,仔细检查并确保每个互连通孔里都有一枚金属球;
S5:将堆叠设置的基板放在超声波键合机工作台上,采用专用的键合劈刀,调整好键合参数,依次将各个金属球压扁变形,此时,所有变形的金属球将上下两块基板互连,变形后的金属球底面与下层基板的互连焊盘互连,变形后的金属球侧面与上层基板互连通孔内壁的金属化层互连;
S6:参照S3~S5的步骤,重复操作,将剩下的基板依次堆叠实现互连;
S7:将堆叠好的多层三维封装产品装入围框,在产品侧面与围框的缝隙里装上软钎料B,放入真空共晶炉加热,软钎料B熔化填满缝隙完成围框与产品的焊接;
S8:将焊完围框的产品放在网板下,对产品上下两个面分别印刷软钎料A;
S9:将产品放入回流炉中将软钎料A形成的金属凸块加热形成球形,最后进行清洗;
S10:将产品放入测试夹具进行测试,合格后抽真空包装入库。
2.根据权利要求1所述的三维封装的层间互连方法,其特征在于:
S1具体包括:
S11:准备多块基板,根据电路结构对各个基板进行开孔,在基板上需要设置内埋器件的位置开设内埋器件通孔,在基板上需要进行互连的位置开设互连通孔,然后根据电路结构在基板上制备对应电路和互连焊盘,过程中对互连通孔内壁与基板外侧进行镀金;
S12:准备一个金属围框,加工围框时对围框的外侧进行倒角,围框的内侧镀镍金,外侧镀镍。
3.根据权利要求2所述的三维封装的层间互连方法,其特征在于:
S11还包括:在基板的表面和底面四周布置接地焊盘。
4.根据权利要求1所述的三维封装的层间互连方法,其特征在于:
S5中,在键合时键合温度不超过150℃,每次只键合一个金属球。
5.根据权利要求1所述的三维封装的层间互连方法,其特征在于:
S7中,在产品侧面与围框的缝隙里装上熔点为220度的铟铅合金。
6.根据权利要求5所述的三维封装的层间互连方法,其特征在于:
S8中,对产品上下两个面分别印刷熔点为185℃的铟铅焊膏;
S9中,将产品放入210度的回流炉中将铟铅焊膏形成的金属凸块加热形成球形。
7.一种三维封装的层间互连结构,其特征在于:
采用权利要求1-6任一所述的三维封装的层间互连方法得到。
8.根据权利要求7所述的三维封装的层间互连结构,其特征在于:
包括多块层叠设置的基板,基板上需要设置内埋器件的位置开设有内埋器件通孔,基板需要与另一基板进行互连的位置开设有互连通孔,基板的表面和底面根据电路结构制备有对应电路和互连焊盘,互连通孔内壁设置有金属化层;
上层基板的互连通孔与下层基板的互连焊盘相对齐,互连通孔内设置有金属球,金属球被超声波键合机压扁变形,所有变形的金属球将上下两块基板互连,变形后的金属球底面与下层基板的互连焊盘互连,变形后的金属球侧面与上层基板互连通孔内壁的金属化层互连;
堆叠完成之后的基板装配在围框中,基板与围框固定连接。
9.根据权利要求8所述的三维封装的层间互连结构,其特征在于:
基板可以采用FR-4基板、氧化铝基板、氧化锆基板、氧化铍基板、氮化铝基板、硅基板、石英基板、玻璃基板、LCP基板、LTCC基板或HTCC基板。
10.根据权利要求8所述的三维封装的层间互连结构,其特征在于:
基板的厚度为0.1~5毫米,互连通孔的直径为0.05~2毫米。
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