CN116366008A - Design method of millimeter wave dual-band low-noise amplifier circuit - Google Patents
Design method of millimeter wave dual-band low-noise amplifier circuit Download PDFInfo
- Publication number
- CN116366008A CN116366008A CN202310404822.5A CN202310404822A CN116366008A CN 116366008 A CN116366008 A CN 116366008A CN 202310404822 A CN202310404822 A CN 202310404822A CN 116366008 A CN116366008 A CN 116366008A
- Authority
- CN
- China
- Prior art keywords
- common
- capacitor
- source
- matching network
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000013461 design Methods 0.000 title claims abstract description 16
- 239000003990 capacitor Substances 0.000 claims description 86
- 230000008878 coupling Effects 0.000 claims description 7
- 238000010168 coupling process Methods 0.000 claims description 7
- 238000005859 coupling reaction Methods 0.000 claims description 7
- 230000000694 effects Effects 0.000 claims description 2
- 230000003321 amplification Effects 0.000 abstract description 12
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 12
- 230000009977 dual effect Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 238000004891 communication Methods 0.000 description 4
- 238000012938 design process Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 101100172279 Paenibacillus polymyxa endR gene Proteins 0.000 description 1
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
- H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/534—Transformer coupled at the input of an amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/537—A transformer being used as coupling element between two amplifying stages
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/541—Transformer coupled at the output of an amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45172—A transformer being added at the input of the dif amp
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45228—A transformer being added at the output or the load circuit of the dif amp
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a design method of a millimeter wave dual-band low-noise amplifier circuit, which realizes the simultaneous amplification of two frequency band signals through a matching network. The millimeter wave dual-band low-noise amplifier circuit comprises an input matching network, a first-stage amplifier, an interstage matching network, a second-stage amplifier and an output matching network. The matching network and the amplifying circuit are equivalent, the design of the dual frequency band is equivalent to the design of a pole, and the forward transfer impedance Z in the Z parameter is utilized 21 The pole is determined by the equation of (2), and the pole is obtained by rapid calculationAnd parameters of the dual-band matching network are matched, so that the design efficiency is improved. The obtained millimeter wave dual-band low-noise amplifier circuit realizes the simultaneous amplification of input signals of two frequency bands under the condition of low noise.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, relates to a low-noise amplifier in microwave and millimeter wave chips, and in particular relates to a design method of a millimeter wave dual-band low-noise amplifier circuit.
Background
In recent years, with the rapid development of real-time high-definition video transmission, intelligent driving and cloud computing services, the requirements on high-speed communication and system capacity are higher and higher, so that the high-frequency microwaves, especially millimeter wave frequency bands become the main direction of the development of modern communication systems, and the method has very wide application prospects and is commonly used in the fields of communication, radar, medical treatment and the like.
Since the signal is attenuated very fast in space in the millimeter wave band, the signal that can be received by the receiver is weak. The signal receiving circuit of the millimeter wave circuit is very critical, and is the basis of the whole millimeter wave circuit. The Low Noise Amplifier (LNA) is used as a key circuit of the signal receiving and amplifying part of the millimeter wave front end system, and is mainly used for amplifying weak signals received from an antenna, reducing noise interference and determining the frequency range and the sensitivity of the system.
In the prior art, the millimeter wave low noise amplifier circuit can be realized through various schemes, and for the multi-band millimeter wave low noise amplifier circuit, the parameters to be determined are more due to the multi-stage matching network structure, and the optimization process is more complex, so that the research and the development and the application of the millimeter wave dual-frequency transceiver are greatly limited.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a design method of a millimeter wave dual-band low-noise amplifier circuit, which can quickly determine parameters of a matching network and realize simultaneous amplification and output of two-band input signals under the condition of keeping low noise.
The design method of the millimeter wave dual-band low-noise amplifier specifically comprises the following steps:
step 1, determining topology type and double-working frequency omega of a double-frequency-band low-noise amplifier 1 、ω 2 . The dual-band low-noise amplifier comprises an input matching network, a first-stage amplifier, an interstage matching network, a second-stage amplifier and an output matching network which are sequentially cascaded.
Step 2, extracting input impedance and output impedance of an active transistor in each stage of amplifier respectively, and performing single-ended equivalent to obtain an input end equivalent circuit and an output end equivalent circuit of each stage of amplifier; and simultaneously, carrying out single-ended circuit equivalent on the matching network.
And step 3, combining the matching network with the single-ended equivalent circuit of the amplifier connected with the matching network to obtain the whole equivalent circuit of the matching network. And then T model equivalent is carried out on the transformer part and the real part is ignored, so that a simplified equivalent circuit is obtained. The simplified equivalent circuit comprises an inductance L a 、L b 、L c And capacitor C a And C b . Wherein the capacitance C a 、C b One end of the capacitor is grounded, and the other end is respectively connected with the inductor L a 、L b Is connected to one end of the housing. Inductance L a 、L b Through inductance L c And (5) grounding.
Step 4, solving the coefficient Z in the Z parameter equation aiming at the simplified equivalent circuit obtained in the step 3 21 ：
Where k is the coupling coefficient of the two ends of the transformer, ω represents the resonant frequency, and j represents the imaginary number.
Step 5, determining the coupling coefficient k of the transformer and the inductances L at two sides a 、L b 、L c To make Z 21 The denominator is zero to find the pole frequency:
ω 4 C a C b (L a L b +L a L c +L b L c )-ω 2 (C a L a +C a L c +C b L b +C b L c )+1＝0
let L a ＝n 1 *L b ＝n 2 *L c ＝n 3 *L、C a ＝n 4 *C b ＝n 5 * C, the following steps are:
aC 2 L 2 ω 4 +bCLω 2 +1＝0
wherein,,
as can be seen from the formula, the product of C and L is determined by the resonant frequency ω, and the operating frequency ω of the circuit 1 、ω 2 It is known that two solutions C of the parameter C can thus be obtained correspondingly low And C high Taking C low And C high The average value of (2) is substituted into a simplified equivalent circuit, and the values of the transformer and the parallel capacitor in the matching network are obtained through calculation.
And 6, sequentially determining values of transformers and parallel capacitors in the input matching network, the interstage matching network and the output matching network by the method of the steps 3-5, and adjusting and optimizing the determined parameters according to actual effects to complete circuit design.
Preferably, the first stage amplifier is a common source amplifier, and the second stage amplifier is a common source common gate amplifier.
The input matching network converts weak signals input by a single end into differential signals and comprises a first transformer T1, a first capacitor C1 and a second capacitor C2. One end of the primary coil of the first transformer is used as an input end, and the other end of the primary coil of the first transformer is grounded. One end of the first capacitor C1 is connected with the input end, and the other end of the first capacitor C is grounded; the center tap of the secondary coil is connected with a direct-current voltage source, and two ends of the secondary coil are respectively connected with the grid electrodes of two transistors of the common source electrodes in the first-stage amplifier to provide bias voltage for the transistors. Two ends of the second capacitor are respectively connected with two ends of the secondary coil.
The inter-stage matching network comprises a second transformer T2, a fifth capacitor C5 and a sixth capacitor C6. The center tap of the second transformer T2 is connected with a direct-current voltage source, and two ends of the primary coil are respectively connected with the drains of the transistors of the two common sources in the first-stage amplifier to provide bias voltage for the transistors. Both ends of the fifth capacitor C5 are respectively connected to both ends of the primary coil. The center tap of the secondary coil is connected with a direct-current voltage source, and two ends of the secondary coil are respectively connected with the grid electrodes of two common source transistors in the second-stage amplifier to provide bias voltage for the two common source transistors. Both ends of the sixth capacitor C6 are respectively connected with both ends of the secondary coil.
The output matching network comprises a third transformer T3, a ninth capacitor C9 and a tenth capacitor C10. The center tap of the third transformer T3 is connected with a direct-current voltage source, and two ends of the primary coil are respectively connected with the drains of two common-gate transistors in the second-stage amplifier to provide bias voltage for the two common-gate transistors. Both ends of the ninth capacitor C9 are connected to both ends of the primary coil, respectively. One end of the secondary coil is used as an output end, and the other end of the secondary coil is grounded. One end of the tenth capacitor C10 is connected to the output terminal, and the other end is grounded.
Preferably, the first stage amplifier includes a first common source amplifying stage transistor M1, a second common source amplifying stage transistor M2, a third capacitor C3, and a fourth capacitor C4. The drain electrode of the first common-source amplifying stage transistor M1 is connected to the gate electrode M2 of the second common-source amplifying stage transistor through a third capacitor C3, the drain electrode of the second common-source amplifying stage transistor M2 is connected to the gate electrode of the first common-source amplifying stage transistor M1 through a fourth capacitor C4, and the source electrodes are all grounded.
The second-stage amplifier comprises a second-stage common-source amplifying stage, a second-stage common-gate amplifying stage, a seventh capacitor C7 and an eighth capacitor C8. The second-stage common-source amplifying stage comprises a third common-source amplifying stage transistor M3 and a fourth common-source amplifying stage transistor M4. The second-stage common-gate amplifying transistor comprises a first common-gate amplifying transistor M5 and a second common-gate amplifying transistor M6. The drain electrode of the third common-source amplifying stage transistor M3 is connected with the gate electrode of the fourth common-source amplifying stage transistor M4 through a seventh capacitor C7, the drain electrode of the fourth common-source amplifying stage transistor M4 is connected with the gate electrode of the third common-source amplifying stage transistor M3 through an eighth capacitor C8, and the source electrodes are grounded. The source of the first common-gate amplification stage transistor M5 is connected to the drain of the third common-source amplification stage transistor M3, and the source of the second common-gate amplification stage transistor M6 is connected to the drain of the fourth common-source amplification stage transistor M4. The grid electrode of the first common-gate amplifying stage transistor M5 is connected with the grid electrode of the second common-gate amplifying stage transistor M6 and then is connected with a direct-current voltage source, and grid bias voltage is provided for the transistors in the second common-gate amplifying stage.
Preferably, the transistors in the two-stage amplifier are NMOS transistors.
Preferably, the gate width of the transistor is 2um, and the number of the fingers is 16.
The invention has the following beneficial effects:
the invention performs equivalent on the matching network and the amplifying circuit, and the design of the dual-band is equivalent to the design of the pole, and Z is adopted 21 And the poles are determined, so that parameters of the dual-band matching network can be obtained through rapid calculation, and the design efficiency is improved. The obtained millimeter wave dual-band low-noise amplifier circuit realizes the simultaneous amplification of input signals of two frequency bands under the condition of low noise.
Drawings
FIG. 1 is a schematic diagram of a dual band LNA according to an embodiment;
FIG. 2 is a schematic circuit diagram of a dual band low noise amplifier according to an embodiment;
FIG. 3 is a diagram showing a design process and transmission characteristics S of an input matching network in an embodiment 21 ；
FIG. 4 is a schematic diagram of a design process and transmission characteristics S of an inter-stage matching network in an embodiment 21 ；
FIG. 5 is a diagram showing a design process and transmission characteristics S of an output matching network in an embodiment 21 ；
FIG. 6 shows the gain characteristic S of the dual band LNA according to the embodiment 21 。
Detailed Description
The invention is further explained below with reference to the drawings;
at a dual operating frequency omega 1 =26 GHz and ω 2 For example, 38.5GHz illustrates a design method of a millimeter wave dual-band low noise amplifier according to the present invention：
Step 1, as shown in fig. 1, the dual-band low noise amplifier comprises an input matching network, a first-stage amplifier, an interstage matching network, a second-stage amplifier and an output matching network which are sequentially cascaded. The amplifier topology type is shown in fig. 2, and the first stage amplifier includes a first common source amplifying stage transistor M1, a second common source amplifying stage transistor M2, a third capacitor C3, and a fourth capacitor C4. The drain electrode of the first common-source amplifying stage transistor M1 is connected to the gate electrode M2 of the second common-source amplifying stage transistor through a third capacitor C3, the drain electrode of the second common-source amplifying stage transistor M2 is connected to the gate electrode of the first common-source amplifying stage transistor M1 through a fourth capacitor C4, and the source electrodes are all grounded.
The second-stage amplifier comprises a second-stage common-source amplifying stage, a second-stage common-gate amplifying stage, a seventh capacitor C7 and an eighth capacitor C8. The second-stage common-source amplifying stage comprises a third common-source amplifying stage transistor M3 and a fourth common-source amplifying stage transistor M4. The second-stage common-gate amplifying transistor comprises a first common-gate amplifying transistor M5 and a second common-gate amplifying transistor M6. The drain electrode of the third common-source amplifying stage transistor M3 is connected with the gate electrode of the fourth common-source amplifying stage transistor M4 through a seventh capacitor C7, the drain electrode of the fourth common-source amplifying stage transistor M4 is connected with the gate electrode of the third common-source amplifying stage transistor M3 through an eighth capacitor C8, and the source electrodes are grounded. The source of the first common-gate amplification stage transistor M5 is connected to the drain of the third common-source amplification stage transistor M3, and the source of the second common-gate amplification stage transistor M6 is connected to the drain of the fourth common-source amplification stage transistor M4. The grid electrode of the first common-gate amplifying stage transistor M5 is connected with the grid electrode of the second common-gate amplifying stage transistor M6 and then is connected with a direct-current voltage source, and grid bias voltage is provided for the transistors in the second common-gate amplifying stage.
The input matching network converts weak signals input by a single end into differential signals and comprises a first transformer T1, a first capacitor C1 and a second capacitor C2. One end of the primary coil of the first transformer is used as an input end, and the other end of the primary coil of the first transformer is grounded. One end of the first capacitor C1 is connected with the input end, and the other end of the first capacitor C is grounded; the center tap of the secondary coil is connected with a direct-current voltage source, and two ends of the secondary coil are respectively connected with the grid electrodes of two transistors of the common source electrodes in the first-stage amplifier to provide bias voltage for the transistors. Two ends of the second capacitor are respectively connected with two ends of the secondary coil.
In the present embodiment, in the first stage amplifier, the gate bias voltage of the transistors M1, M2 is 0.5V, and the drain bias voltage is 1V; in the second-stage amplifier, the gate bias voltages of the transistors M3 and M4 are 0.5V, the gate bias voltages of the transistors M5 and M6 are 1.5V, and the drain bias voltages are 2V.
The inter-stage matching network comprises a second transformer T2, a fifth capacitor C5 and a sixth capacitor C6. The center tap of the second transformer T2 is connected with a direct-current voltage source, and two ends of the primary coil are respectively connected with the drains of the transistors of the two common sources in the first-stage amplifier to provide bias voltage for the transistors. Both ends of the fifth capacitor C5 are respectively connected to both ends of the primary coil. The center tap of the secondary coil is connected with a direct-current voltage source, and two ends of the secondary coil are respectively connected with the grid electrodes of two common source transistors in the second-stage amplifier to provide bias voltage for the two common source transistors. Both ends of the sixth capacitor C6 are respectively connected with both ends of the secondary coil.
The output matching network comprises a third transformer T3, a ninth capacitor C9 and a tenth capacitor C10. The center tap of the third transformer T3 is connected with a direct-current voltage source, and two ends of the primary coil are respectively connected with the drains of two common-gate transistors in the second-stage amplifier to provide bias voltage for the two common-gate transistors. Both ends of the ninth capacitor C9 are connected to both ends of the primary coil, respectively. One end of the secondary coil is used as an output end, and the other end of the secondary coil is grounded. One end of the tenth capacitor C10 is connected to the output terminal, and the other end is grounded.
The capacitors C1-C10 adopt MOM capacitors with interdigital structures, wherein the capacitors C3, C4, C7 and C8 are neutralization capacitors with capacitance values of 9.6fF and are used for improving the isolation degree of the transistors, and the capacitors C1, C2, C5, C6, C9 and C10 are all matched capacitors.
Step 2, extracting input impedance and output impedance of active transistors in each stage of amplifier respectively, and performing single-ended equivalent, wherein an input end equivalent circuit of the first stage of amplifier is a resistor R g1 And capacitor C gs1 Is an electric circuit with an equivalent circuit at the output endR resistance ds1 Parallel capacitor C ds1 And then series resistor R d1 Is provided. The equivalent circuit of the input end of the second-stage amplifier is a resistor R g2 And capacitor C gs2 The equivalent circuit at the output end is a resistor R ds2 Parallel capacitor C ds2 And then series resistor R d2 Is provided. And simultaneously, carrying out single-ended circuit equivalent on the matching network. The single-ended equivalent circuit of the input matching network is a parallel capacitor C of a first equivalent transformer T1s 1s And C 2s . The single-ended equivalent circuit of the interstage matching network is a second equivalent transformer T2s parallel capacitor C 5s And C 6s . The single-ended equivalent circuit of the output matching network is a third equivalent transformer T3s parallel capacitor C 9s And C 10s 。
And 3, combining the input matching network with the input end equivalent circuit of the first-stage amplifier to obtain an overall equivalent circuit of the input matching network, as shown in (a) of fig. 3. Then, the first equivalent transformer T1s is subjected to T model equivalent and the real part is ignored, resulting in a simplified equivalent circuit as shown in fig. 3 (b). Wherein the inductance L a1 、L b1 、L c1 The equivalent inductance and capacitance C of the first equivalent transformer T1s a1 And C b1 Is the capacitance across the transformer. Solving the coefficient Z in the Z parameter equation for the simplified equivalent circuit 21 ：
Wherein k is 1 For the coupling coefficient across the first equivalent transformer T1s ω represents the resonant frequency and j represents the imaginary number. Setting k according to experience 1 ＝0.4，L a1 ＝0，L b1 ＝6L c1 =600 pH, let L 1 ＝100pH、C a1 ＝6C b1 ＝6C 1 At the coefficient Z 21 The pole frequency is obtained when the denominator is zero:
solving to obtain a parameter C 1 The average value 41fF of the solutions 40fF and 42.7fF is substituted into a simplified equivalent circuit, and the values of the transformer and the parallel capacitor in the matching network are calculated, so that the working frequencies of the input matching network are 26.2GHz and 39.3GHz, as shown in (c) in fig. 3.
And 4, combining the interstage matching network with the output end equivalent circuit of the first-stage amplifier and the input end equivalent circuit of the second-stage amplifier simultaneously to obtain an overall equivalent circuit of the interstage matching network, and performing equivalent according to the method in the step 3 as shown in (a) of fig. 4 to obtain a simplified equivalent circuit as shown in (b) of fig. 4. Setting the coupling coefficient k at two ends of the second equivalent transformer T2s 2 ＝0.35，L a2 ＝L b2 ＝2L c2 ＝2L 2 ＝400pH，C a2 ＝2C b2 ＝2C 2 The same can be obtained:
solving to obtain a parameter C 2 Is 29.3fF and 34.7fF, taking the average value of 32fF and substituting into the simplified equivalent circuit, and obtaining the working frequencies of the interstage matching network to be 24.9GHz and 40.1GHz, as shown in (c) of fig. 4.
And 5, combining the output matching network with an output end equivalent circuit of the second-stage amplifier to obtain an overall equivalent circuit of the interstage matching network, and performing equivalent according to the method in the step 3 as shown in (a) of fig. 5 to obtain a simplified equivalent circuit as shown in (b) of fig. 5. Setting the coupling coefficient k of the two ends of the third equivalent transformer T3s 3 ＝0.45，L b3 ＝0，L a3 ＝4L c3 ＝4L 3 ＝560pH，C b3 ＝6C a3 ＝6C 3 The same can be obtained:
solving to obtain a parameter C 3 And (c) taking the average value of 37fF of the solutions 33.5fF and 40.7fF and substituting the average value into the simplified equivalent circuit to obtain the working frequencies of the interstage matching network of 24.7GHz and 40.4GHz, as shown in (c) of fig. 5.
The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (6)
1. A design method of a millimeter wave dual-band low-noise amplifier circuit is characterized by comprising the following steps of: the method specifically comprises the following steps:
step 1, determining topology type and double-working frequency omega of a double-frequency-band low-noise amplifier 1 、ω 2 The method comprises the steps of carrying out a first treatment on the surface of the The dual-band low-noise amplifier comprises an input matching network, a first-stage amplifier, an interstage matching network, a second-stage amplifier and an output matching network which are sequentially cascaded;
step 2, extracting input impedance and output impedance of an active transistor in each stage of amplifier respectively, and performing single-ended equivalent to obtain an input end equivalent circuit and an output end equivalent circuit of each stage of amplifier; meanwhile, the matching network is also subjected to single-ended circuit equivalence;
step 3, combining the matching network with a single-ended equivalent circuit of an amplifier connected with the matching network to obtain an overall equivalent circuit of the matching network; then performing T model equivalent on the transformer part in the transformer part and neglecting the resistance in the transformer part to obtain a simplified equivalent circuit; the simplified equivalent circuit comprises an inductance L a 、L b 、L c And capacitor C a And C b ；
Step 4, solving the coefficient Z in the Z parameter equation aiming at the simplified equivalent circuit obtained in the step 3 21 ：
Wherein k is a coupling coefficient of two ends of the transformer, ω represents a resonant frequency, and j represents an imaginary number;
step 5, determining the coupling coefficient k of the transformer and the inductances L at two sides a 、L b 、L c To make Z 21 The denominator is zero to find the pole frequency:
ω 4 C a C b (L a L b +L a L c +L b L c )-ω 2 (C a L a +C a L c +C b L b +C b L c )+1＝0
let L a ＝n 1 *L b ＝n 2 *L c ＝n 3 *L、C a ＝n 4 *C b ＝n 5 * C, the following steps are:
aC 2 L 2 ω 4 +bCLω 2 +1＝0
wherein,,
according to the operating frequency omega 1 、ω 2 Solving for two solutions C of parameter C low And C high Taking C low And C high Substituting the average value of the transformer and the parallel capacitor in the matching network into a simplified equivalent circuit, and calculating to obtain the value of the transformer and the parallel capacitor in the matching network;
and 6, sequentially determining values of the transformers and the parallel capacitors in the input matching network, the interstage matching network and the output matching network by the method of the steps 3-5, and adjusting and optimizing the determined parameters according to actual effects to complete circuit design.
2. The method for designing a millimeter wave dual-band low noise amplifier circuit as defined in claim 1, wherein: the first-stage amplifier is a common-source amplifier, and the second-stage amplifier is a common-source common-gate amplifier;
the input matching network converts weak signals input by a single end into differential signals and comprises a first transformer T1, a first capacitor C1 and a second capacitor C2; one end of the primary coil of the first transformer is used as an input end, and the other end of the primary coil of the first transformer is grounded; one end of the first capacitor C1 is connected with the input end, and the other end of the first capacitor C is grounded; the center tap of the secondary coil is connected with a direct-current voltage source, and two ends of the secondary coil are respectively connected with the grid electrodes of the transistors of the two common sources in the first-stage amplifier to provide bias voltage for the transistors; two ends of the second capacitor are respectively connected with two ends of the secondary coil;
the interstage matching network comprises a second transformer T2, a fifth capacitor C5 and a sixth capacitor C6; the center tap of the second transformer T2 is connected with a direct-current voltage source, and two ends of the primary coil are respectively connected with the drains of the transistors of the two common sources in the first-stage amplifier to provide bias voltage for the transistors; two ends of the fifth capacitor C5 are respectively connected with two ends of the primary coil; the center tap of the secondary coil is connected with a direct-current voltage source, and two ends of the secondary coil are respectively connected with the grid electrodes of two common source transistors in the second-stage amplifier to provide bias voltage for the two common source transistors; two ends of the sixth capacitor C6 are respectively connected with two ends of the secondary coil;
the output matching network comprises a third transformer T3, a ninth capacitor C9 and a tenth capacitor C10; the center tap of the third transformer T3 is connected with a direct-current voltage source, and two ends of the primary coil are respectively connected with the drains of two common-gate transistors in the second-stage amplifier to provide bias voltage for the two common-gate transistors; two ends of the ninth capacitor C9 are respectively connected with two ends of the primary coil; one end of the secondary coil is used as an output end, and the other end of the secondary coil is grounded; one end of the tenth capacitor C10 is connected to the output terminal, and the other end is grounded.
3. The method for designing a millimeter wave dual-band low noise amplifier circuit as defined in claim 1 or 2, wherein: the first-stage amplifier comprises a first common-source amplifying stage transistor M1, a second common-source amplifying stage transistor M2, a third capacitor C3 and a fourth capacitor C4; the drain electrode of the first common-source amplifying stage transistor M1 is connected with the grid electrode M2 of the second common-source amplifying stage transistor through a third capacitor C3, the drain electrode of the second common-source amplifying stage transistor M2 is connected with the grid electrode of the first common-source amplifying stage transistor M1 through a fourth capacitor C4, and the source electrodes are grounded;
the second-stage amplifier comprises a second-stage common-source amplifying stage, a second-stage common-gate amplifying stage, a seventh capacitor C7 and an eighth capacitor C8; the second-stage common-source amplifying stage comprises a third common-source amplifying stage transistor M3 and a fourth common-source amplifying stage transistor M4; the second-stage common-gate amplifying-stage transistor comprises a first common-gate amplifying-stage transistor M5 and a second common-gate amplifying-stage transistor M6; the drain electrode of the third common-source amplifying stage transistor M3 is connected with the gate electrode of the fourth common-source amplifying stage transistor M4 through a seventh capacitor C7, the drain electrode of the fourth common-source amplifying stage transistor M4 is connected with the gate electrode of the third common-source amplifying stage transistor M3 through an eighth capacitor C8, and the source electrodes are grounded; the source of the first common-gate amplifying stage transistor M5 is connected with the drain of the third common-source amplifying stage transistor M3, and the source of the second common-gate amplifying stage transistor M6 is connected with the drain of the fourth common-source amplifying stage transistor M4; the grid electrode of the first common-gate amplifying stage transistor M5 is connected with the grid electrode of the second common-gate amplifying stage transistor M6 and then is connected with a direct-current voltage source, and grid bias voltage is provided for the transistors in the second common-gate amplifying stage.
4. A method of designing a millimeter wave dual-band low noise amplifier circuit as defined in claim 3, wherein: the transistors in the amplifier are NMOS transistors.
5. A method of designing a millimeter wave dual-band low noise amplifier circuit as defined in claim 3, wherein: the gate width of the transistor is 2um, and the number of the interdigital is 16.
6. A method of designing a millimeter wave dual-band low noise amplifier circuit as defined in claim 3, wherein: in the first stage amplifier, the gate bias voltage of the transistors M1, M2 is 0.5V, and the drain bias voltage is 1V; in the second-stage amplifier, the gate bias voltages of the transistors M3 and M4 are 0.5V, the gate bias voltages of the transistors M5 and M6 are 1.5V, and the drain bias voltages are 2V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310404822.5A CN116366008A (en) | 2023-04-11 | 2023-04-11 | Design method of millimeter wave dual-band low-noise amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310404822.5A CN116366008A (en) | 2023-04-11 | 2023-04-11 | Design method of millimeter wave dual-band low-noise amplifier circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116366008A true CN116366008A (en) | 2023-06-30 |
Family
ID=86937784
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310404822.5A Pending CN116366008A (en) | 2023-04-11 | 2023-04-11 | Design method of millimeter wave dual-band low-noise amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116366008A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118300693A (en) * | 2024-06-05 | 2024-07-05 | 太景科技(南京)有限公司 | Radio frequency circuit in radar transceiver, transceiver and radar equipment |
-
2023
- 2023-04-11 CN CN202310404822.5A patent/CN116366008A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118300693A (en) * | 2024-06-05 | 2024-07-05 | 太景科技(南京)有限公司 | Radio frequency circuit in radar transceiver, transceiver and radar equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106712725A (en) | Ultra wideband high-gain low noise amplifier based on monolithic microwave integrated circuit | |
| CN206195723U (en) | Ultra wide band high -gain low -noise amplifier based on monolithic microwave integrated circuit | |
| CN111030614A (en) | Transconductance enhancement type millimeter wave low noise amplifier | |
| CN113381713A (en) | Dual-band low-noise amplifier based on reconfigurable inductor | |
| CN114024512B (en) | Ultra-wideband low noise amplifier of frequency division duplex | |
| CN108336976A (en) | A kind of multiband low-noise amplifier and amplification method | |
| CN112019168A (en) | Power amplifier based on slow wave microstrip line matching network | |
| CN109450394A (en) | A kind of compact high efficient twin-stage dual-band power amplifier | |
| CN114844470A (en) | Low-noise amplifier and chip | |
| CN116366008A (en) | Design method of millimeter wave dual-band low-noise amplifier circuit | |
| CN211046870U (en) | High-power two-dimensional traveling wave CMOS power amplifier | |
| CN114172470B (en) | Power amplifier interstage matching network and broadband low insertion loss optimization method | |
| WO2020108175A1 (en) | Ultra-low-noise amplifier | |
| CN114070208A (en) | High-gain millimeter wave broadband ultra-low noise amplifier based on gallium nitride process | |
| CN211063579U (en) | X-waveband low-noise amplifier | |
| CN111030607B (en) | Two-dimensional traveling wave high-gain broadband CMOS power amplifier | |
| CN113395043A (en) | High-efficiency dual-frequency power amplifier based on accurate harmonic control and design method thereof | |
| CN110113013B (en) | High octave ultra-wideband input matching circuit for low noise amplifier | |
| CN209844918U (en) | High-octave ultra-wideband input matching circuit for low-noise amplifier | |
| Datta et al. | A gain boosted fully concurrent dual-band interstage matched LNA operating in 900 MHz/2.4 GHz with sub-2dB Noise Figure | |
| CN114759882B (en) | Dual-frequency coupling low-noise amplification circuit and amplifier | |
| CN101079596A (en) | Wide frequency low-noise amplifier | |
| Phetpadriew et al. | Concurrent Multiband CMOS Low Noise Amplifier Design for Internet of Things Applications | |
| Gamal et al. | Concurrent dual-band LNA for automotive application | |
| US11742807B1 (en) | Dual-band coupling low-noise amplifying circuit and amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |