CN211046870U - High-power two-dimensional traveling wave CMOS power amplifier - Google Patents
High-power two-dimensional traveling wave CMOS power amplifier Download PDFInfo
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- CN211046870U CN211046870U CN201922454328.1U CN201922454328U CN211046870U CN 211046870 U CN211046870 U CN 211046870U CN 201922454328 U CN201922454328 U CN 201922454328U CN 211046870 U CN211046870 U CN 211046870U
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Abstract
The utility model discloses a high-power two-dimensional travelling wave CMOS power amplifier, which comprises an input power dividing network, a first input three-order artificial transmission line, a second input three-order artificial transmission line, a drain electrode bias network, a first high-gain two-pile PMOS amplifying network, a second high-gain two-pile PMOS amplifying network, a third high-gain two-pile PMOS amplifying network, a first high-gain two-pile NMOS amplifying network, a second high-gain two-pile NMOS amplifying network, a third high-gain two-pile NMOS amplifying network and an output two-dimensional three-order artificial transmission line network, wherein the core framework adopts the high power and high-gain characteristics of the high-gain two-pile PMOS and NMOS amplifying network in a microwave section, and simultaneously utilizes the ultra-wideband frequency response characteristic and the simplified series-connection voltage dividing structure of the two-dimensional travelling wave amplifier structure to ensure that the whole power amplifier obtains good broadband, high gain, high efficiency and high power output capability, meanwhile, the power supply network is simple.
Description
Technical Field
The utility model relates to a field effect transistor radio frequency power amplifier and integrated circuit field, especially to the high-power two-dimentional travelling wave CMOS power amplifier that the terminal emission module of radio frequency microwave transceiver was used.
Background
With the rapid development of wireless communication systems and rf microwave circuits, rf front-end transceivers are also developing in the direction of high performance, high integration, and low power consumption. Therefore, the rf and microwave power amplifiers of the transmitter are urgently required to have high output power, high gain, high efficiency, low cost and other performances in the market, and the integrated circuit is a key technology expected to meet the market demand. However, when the integrated circuit process design is adopted to realize the chip circuit of the radio frequency and microwave power amplifier, the performance and the cost are limited to a certain extent, and the method mainly comprises the following steps:
(1) the broadband high gain amplification capability is limited: the traditional single transistor is influenced by a gain-bandwidth product, and the ultra-wideband amplification capability can be obtained only by sacrificing gain, so that the high-gain amplification capability of the wideband is severely limited.
(2) The broadband high power amplification capability is limited: the characteristic frequency of transistors in semiconductor processes is higher and higher, thereby bringing about low breakdown voltage and limiting the power capacity of a single transistor. In order to obtain high power capability, multi-transistor power synthesis is often required, but the efficiency of the power amplifier is low due to energy loss of a multi-synthesis network, and the circuit cannot meet the requirements of low power consumption or green communication.
The circuit structure of the common ultra-wideband high-power amplifier is many, most typically the conventional distributed amplifier, but it is difficult for the conventional distributed amplifier to satisfy the requirements of various parameters at the same time, mainly because:
① in the traditional distributed power amplifier, the core amplifying circuit is realized by a distributed amplifying arrangement of a plurality of single transistors, because the single transistors are affected by parasitic parameters, the power gain of the single transistors will be significantly reduced and the power characteristics will be significantly deteriorated as the working frequency increases, therefore, in order to obtain an ultra-wideband flat amplifying structure, the low frequency gain must be sacrificed to balance the high frequency loss, resulting in the ultra-wideband gain of the traditional distributed amplifier being very low;
② in order to improve the amplifier gain and isolation, it is also possible to use a Cascode two-transistor distributed amplification structure, but although Cascode two-transistor increases circuit isolation, it is not possible to achieve a tendency that gain is significantly deteriorated with frequency, and it is also not possible to achieve optimum impedance matching between Cascode two-transistors, thereby reducing output power characteristics.
Therefore, the design difficulty of the ultra-wideband radio frequency power amplifier based on the integrated circuit process is as follows: the high power output difficulty under the ultra-wide band is large; there are many limitations to the conventional single transistor structure or the distributed amplification structure of the Cascode transistor.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem that a high-power two-dimentional travelling wave CMOS power amplifier is provided, two have been combined and have been piled up big network technology, PMOS and the complementary cascade structure of NMOS, two-dimentional travelling wave and have advantages such as broadband, high power, high-gain and with low costs, the power supply network is simple and easy.
The utility model provides an above-mentioned technical problem's technical scheme as follows: a high-power two-dimensional traveling wave CMOS power amplifier is characterized by comprising an input power dividing network, a first input three-order artificial transmission line, a second input three-order artificial transmission line, a drain electrode bias network, a first high-gain two-pile PMOS (P-channel metal oxide semiconductor) amplification network, a second high-gain two-pile PMOS amplification network, a third high-gain two-pile PMOS amplification network, a first high-gain two-pile NMOS (N-channel metal oxide semiconductor) amplification network, a second high-gain two-pile NMOS amplification network, a third high-gain two-pile NMOS amplification network and an output two-dimensional three-order artificial transmission line network;
the input end of the input power dividing network is the input end of the whole high-power two-dimensional traveling wave CMOS power amplifier, the first output end of the input power dividing network is connected with the input end of a first input three-order artificial transmission line, and the second output end of the input power dividing network is connected with the input end of a second input three-order artificial transmission line;
the first, second and third output ends of the first input three-order artificial transmission line are respectively connected with the first input ends of the first high-gain second-pile PMOS amplification network, the second high-gain second-pile PMOS amplification network and the third high-gain second-pile PMOS amplification network;
the first, second and third output ends of the drain electrode biasing network are respectively connected with the second input ends of the first high-gain second-pile PMOS amplification network, the second high-gain second-pile PMOS amplification network and the third high-gain second-pile PMOS amplification network;
the output ends of the first high-gain second-pile PMOS amplification network, the second high-gain second-pile PMOS amplification network and the third high-gain second-pile PMOS amplification network are connected with the first input end, the second input end and the third input end of the output two-dimensional three-order artificial transmission line network;
the first, second and third output ends of the second input three-order artificial transmission line are respectively connected with the input ends of the first high-gain second-stack NMOS amplification network, the second high-gain second-stack NMOS amplification network and the third high-gain second-stack NMOS amplification network;
the output ends of the first high-gain second-pile NMOS amplification network, the second high-gain second-pile NMOS amplification network and the third high-gain second-pile NMOS amplification network are connected with the fourth, fifth and sixth input ends of the output two-dimensional third-order artificial transmission line network;
the output end of the output two-dimensional three-order artificial transmission line network is the output end of the whole high-power two-dimensional traveling wave CMOS power amplifier.
The beneficial effect of above-mentioned scheme is: the utility model discloses a two pile up and enlarge network technique, PMOS and the complementary cascade structure of NMOS, two-dimentional travelling wave amplification technique and have ultra wide band frequency response characteristic and the series connection partial pressure structure of simplifying for whole power amplifier has obtained good broadband, high-gain, high efficiency and high power output ability, and the power supply network is simple and easy simultaneously.
Furthermore, the input end of the input power dividing network is connected with a microstrip line T L1Microstrip line T L1Is connected with the microstrip line T L at the other end2And a microstrip line T L3Microstrip line T L2The other end is connected with a first output end of the input power dividing network, namely a microstrip line T L3The other end of the input power dividing network is connected with a second output end of the input power dividing network.
The beneficial effects of the further scheme are as follows: the utility model discloses the network can structurally realize power partition to the input merit, and microstrip line length can be according to circuit structure's territory needs and adjust simultaneously.
Furthermore, the input end of the first input three-order artificial transmission line is connected with the microstrip line T L23Microstrip line T L23Is connected with the microstrip line T L at the other end4And a first output end of the first input three-order artificial transmission line, microstrip line T L4The other end is connected with a microstrip line T L5And a second output end of the first input three-order artificial transmission line, microstrip line T L5Is connected with the microstrip line T L at the other end6And a third output end of the first input three-order artificial transmission line, microstrip line T L6Another end of the resistor R is connected with a resistor R1Resistance R1Is connected with the microstrip line T L at the other end7Microstrip line T L7Is connected with a bias voltage V at the other endgAnd a ground capacitor C1。
The beneficial effects of the further scheme are as follows: the utility model discloses a third-order artifical transmission line network of first input except can realizing carrying out impedance transformation matching back, still has advantages such as broadband, reflection coefficient index are good.
Furthermore, the input end of the second input three-order artificial transmission line is connected with the microstrip line T L24Microstrip line T L24Is connected with the microstrip line T L at the other end8And a first output end of a second input three-order artificial transmission line, microstrip line T L8The other end is connected with a microstrip line T L9And a second output end of the second input three-order artificial transmission line, microstrip line T L9Is connected with the microstrip line T L at the other end10And second input third-order manual transmissionA third output terminal of the line, microstrip line T L10Another end of the resistor R is connected with a resistor R2Resistance R2Is connected with the microstrip line T L at the other end11Microstrip line T L1The other end of the capacitor is connected with a grounding capacitor C2。
The beneficial effects of the further scheme are as follows: the utility model discloses a second input third-order artifical transmission line network except can realizing carrying out impedance transformation matching back, still has advantages such as broadband, reflection coefficient index are good.
Further, the first output terminal of the drain bias network is connected with the inductor Ls1Inductor Ls1Is connected to a second output terminal of the drain bias network and the inductor Ls2Inductor Ls2Is connected to the third output terminal of the drain bias network and the inductor Ls3Inductor Ls3Is connected with a bias voltage V at the other enddAnd a ground capacitor C3。
The beneficial effects of the further scheme are as follows: the utility model discloses a drain electrode biasing network stability good, and the drain electrode circuit can consider the electric source clutter well.
Further, the first high-gain two-stack PMOS amplification network, the second high-gain two-stack PMOS amplification network and the third high-gain two-stack PMOS amplification network form three amplification networks, wherein the first input end of the jth high-gain two-dimensional PMOS amplification network is connected with an inductor LtjInductor LtjIs connected with an inductor L at the other endmjAnd a ground capacitor CtjInductor LmjThe other end of the first electrode is connected with a field effect tube MtjA gate electrode of (1); the second input end of the jth high-gain two-dimensional PMOS amplification network is connected with a field effect transistor MtjDrain electrode of (1), field effect transistor MtjSource electrode of the transistor M is connected with a field effect transistor MmjDrain electrode of (1), field effect transistor MmjThe grid of the capacitor is connected with a grounding capacitor CmjAnd a resistance RcjResistance RcjThe other end of the resistor is connected with a grounding resistor RwjAnd a resistance RfjResistance RfjThe other end of the first electrode is connected with a field effect tube MmjAnd the output end of the jth high-gain two-stack PMOS amplifying network, wherein j is 1, 2 and 3.
The beneficial effects of the further scheme are as follows: the utility model discloses a pile up two PMOS amplification techniques of high gain and two dimension travelling wave amplification technique and have ultra wide band frequency response characteristic and the series connection partial pressure structure of simplifying for whole power amplifier has obtained good broadband, high gain, high efficiency and high power output ability.
Further, the first high-gain two-stack NMOS amplification network, the second high-gain two-stack NMOS amplification network and the third high-gain two-stack NMOS amplification network form three amplification networks, wherein the first input end of the ith high-gain two-stack NMOS amplification network is connected with an inductor LPiInductor LPiIs connected with an inductor L at the other endeiAnd a ground capacitor CpiInductor LeiThe other end of the first electrode is connected with a field effect tube MpiGrid electrode of (1), field effect transistor MpiThe source of (2) is grounded; the second input end of the ith high-gain two-stack NMOS amplification network is connected with a field effect transistor MpiDrain electrode of (1), field effect transistor MpiDrain electrode of the transistor M is connected with a field effect transistor MgiSource electrode of (1), field effect transistor MgiThe grid of the capacitor is connected with a grounding capacitor CeiAnd a resistance RgiResistance RgiThe other end of the resistor is connected with a grounding resistor R0jAnd a resistance RpiResistance RpiThe other end of the first electrode is connected with a field effect tube MgiAnd the output end of the jth high-gain two-stack NMOS amplification network, where i is 1, 2, and 3.
The beneficial effects of the further scheme are as follows: the utility model discloses a pile up two NMOS of high gain and pile up amplification technique and two-dimentional travelling wave amplification technique and have ultra wide band frequency response characteristic and the series connection partial pressure structure of simplifying for whole power amplifier has obtained good broadband, high gain, high efficiency and high power output ability.
Furthermore, a first input end of the output two-dimensional three-order artificial transmission line network is connected with a microstrip line T L13Microstrip line T L13Is connected with the microstrip line T L at the other end12Microstrip line T L14And a microstrip line T L15Microstrip line T L14The other end of the microstrip line is a fourth input end for outputting a two-dimensional three-order artificial transmission line network, and the microstrip line T L12Another end of the resistor R is connected with a resistor R3Resistance R3The other end of the capacitor is connected with a grounding capacitor C4Microstrip line T L15Is connected with the microstrip line T L at the other end16Microstrip line T L17And a microstrip line T L18Microstrip line T L16And a microstrip line T L17The other ends of the two-dimensional three-order microstrip lines are respectively a second input end and a fifth input end of the output two-dimensional three-order artificial transmission line network, and the microstrip line T L18Is connected with the microstrip line T L at the other end19Microstrip line T L20And a microstrip line T L21Microstrip line T L20And a microstrip line T L21The other ends of the microstrip lines are respectively a third input end and a sixth input end for outputting a two-dimensional three-order artificial transmission line network, and a microstrip line T L21The other end of the capacitor C is connected with a capacitor C5Capacitor C5Is connected with the microstrip line T L at the other end22Microstrip line T L22The other end of the two-dimensional three-order artificial transmission line network is an output end for outputting the two-dimensional three-order artificial transmission line network.
The beneficial effects of the further scheme are as follows: the utility model discloses an output two-dimentional third-order artifical transmission line network can realize six way radio frequency signal's power synthesis, and this kind of artifical transmission line has the bandwidth width, reflection coefficient low grade advantage, can ensure the output and the efficiency of amplifier.
Drawings
Fig. 1 is a schematic block diagram of a power amplifier of the present invention;
fig. 2 is a circuit diagram of the power amplifier of the present invention.
Detailed Description
Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It is to be understood that the embodiments shown and described in the drawings are merely exemplary and are intended to illustrate the principles and spirit of the invention, not to limit the scope of the invention.
The embodiment of the utility model provides a high-power two-dimentional travelling wave CMOS power amplifier, a serial communication port, including input merit branch network, first input third-order artifical transmission line, second input third-order artifical transmission line, drain electrode offset network, first high-gain two pile PMOS amplifier network, second high-gain two pile PMOS amplifier network, third high-gain two pile PMOS amplifier network, first high-gain two pile NMOS amplifier network, second high-gain two pile NMOS amplifier network, third high-gain two pile NMOS amplifier network and output two-dimentional third-order artifical transmission line network;
as shown in fig. 1, the input end of the input power dividing network is the input end of the whole high-power two-dimensional traveling wave CMOS power amplifier, the first output end of the input power dividing network is connected with the input end of the first input third-order artificial transmission line, and the second output end of the input power dividing network is connected with the input end of the second input third-order artificial transmission line;
the first, second and third output ends of the first input three-order artificial transmission line are respectively connected with the first input ends of the first high-gain second-pile PMOS amplification network, the second high-gain second-pile PMOS amplification network and the third high-gain second-pile PMOS amplification network;
the first, second and third output ends of the drain electrode biasing network are respectively connected with the second input ends of the first high-gain second-pile PMOS amplification network, the second high-gain second-pile PMOS amplification network and the third high-gain second-pile PMOS amplification network;
the output ends of the first high-gain second-pile PMOS amplification network, the second high-gain second-pile PMOS amplification network and the third high-gain second-pile PMOS amplification network are connected with the first input end, the second input end and the third input end of the output two-dimensional three-order artificial transmission line network;
the first, second and third output ends of the second input three-order artificial transmission line are respectively connected with the input ends of the first high-gain second-stack NMOS amplification network, the second high-gain second-stack NMOS amplification network and the third high-gain second-stack NMOS amplification network;
the output ends of the first high-gain second-pile NMOS amplification network, the second high-gain second-pile NMOS amplification network and the third high-gain second-pile NMOS amplification network are connected with the fourth, fifth and sixth input ends of the output two-dimensional third-order artificial transmission line network;
the output end of the output two-dimensional three-order artificial transmission line network is the output end of the whole high-power two-dimensional traveling wave CMOS power amplifier.
As shown in fig. 2, the input end of the input power dividing network is connected to microstrip line T L1Microstrip line T L1Another end of the microstrip line is connected withLine T L2And a microstrip line T L3Microstrip line T L2The other end is connected with a first output end of the input power dividing network, namely a microstrip line T L3The other end of the input power dividing network is connected with a second output end of the input power dividing network.
The input end of the first input three-order artificial transmission line is connected with a microstrip line T L23Microstrip line T L23Is connected with the microstrip line T L at the other end4And a first output end of the first input three-order artificial transmission line, microstrip line T L4The other end is connected with a microstrip line T L5And a second output end of the first input three-order artificial transmission line, microstrip line T L5Is connected with the microstrip line T L at the other end6And a third output end of the first input three-order artificial transmission line, microstrip line T L6Another end of the resistor R is connected with a resistor R1Resistance R1Is connected with the microstrip line T L at the other end7Microstrip line T L7Is connected with a bias voltage V at the other endgAnd a ground capacitor C1。
The input end of the second input three-order artificial transmission line is connected with a microstrip line T L24Microstrip line T L24Is connected with the microstrip line T L at the other end8And a first output end of a second input three-order artificial transmission line, microstrip line T L8The other end is connected with a microstrip line T L9And a second output end of the second input three-order artificial transmission line, microstrip line T L9Is connected with the microstrip line T L at the other end10And a third output end of the second input three-order artificial transmission line, microstrip line T L10Another end of the resistor R is connected with a resistor R2Resistance R2Is connected with the microstrip line T L at the other end11Microstrip line T L1The other end of the capacitor is connected with a grounding capacitor C2。
The first output terminal of the drain bias network is connected with the inductor Ls1Inductor Ls1Is connected to a second output terminal of the drain bias network and the inductor Ls2Inductor Ls2Is connected to the third output terminal of the drain bias network and the inductor Ls3Inductor Ls3Is connected with a bias voltage V at the other enddAnd a ground capacitor C3。
A first high-gain two-stack PMOS amplifier network and a second high-gain two-stack PMOS amplifier networkThe high-gain two-stack PMOS amplification network and the third high-gain two-stack PMOS amplification network form three amplification networks, wherein the first input end of the jth high-gain two-stack PMOS amplification network is connected with an inductor LtjInductor LtjIs connected with an inductor L at the other endmjAnd a ground capacitor CtjInductor LmjThe other end of the first electrode is connected with a field effect tube MtjA gate electrode of (1); the second input end of the jth high-gain two-stack PMOS amplification network is connected with a field effect transistor MtjDrain electrode of (1), field effect transistor MtjSource electrode of the transistor M is connected with a field effect transistor MmjDrain electrode of (1), field effect transistor MmjThe grid of the capacitor is connected with a grounding capacitor CmjAnd a resistance RcjResistance RcjThe other end of the resistor is connected with a grounding resistor RwjAnd a resistance RfjResistance RfjThe other end of the first electrode is connected with a field effect tube MmjAnd the output end of the jth high-gain two-stack PMOS amplifying network, wherein j is 1, 2 and 3.
The first high-gain two-stack NMOS amplification network, the second high-gain two-stack NMOS amplification network and the third high-gain two-stack NMOS amplification network form three amplification networks, wherein the first input end of the ith high-gain two-stack NMOS amplification network is connected with an inductor LPiInductor LPiIs connected with an inductor L at the other endeiAnd a ground capacitor CpiInductor LeiThe other end of the first electrode is connected with a field effect tube MpiGrid electrode of (1), field effect transistor MpiThe source of (2) is grounded; the second input end of the ith high-gain two-stack NMOS amplification network is connected with a field effect transistor MpiDrain electrode of (1), field effect transistor MpiDrain electrode of the transistor M is connected with a field effect transistor MgiSource electrode of (1), field effect transistor MgiThe grid of the capacitor is connected with a grounding capacitor CeiAnd a resistance RgiResistance RgiThe other end of the resistor is connected with a grounding resistor R0jAnd a resistance RpiResistance RpiThe other end of the first electrode is connected with a field effect tube MgiAnd the output end of the ith high-gain two-stack NMOS amplifying network, wherein i is 1, 2 and 3.
The first input end of the output two-dimensional third-order artificial transmission line network is connected with a microstrip line T L13Microstrip line T L13Is connected with the microstrip line T L at the other end12Micron, micronStrip line T L14And a microstrip line T L15Microstrip line T L14The other end of the microstrip line is a fourth input end for outputting a two-dimensional three-order artificial transmission line network, and the microstrip line T L12Another end of the resistor R is connected with a resistor R3Resistance R3The other end of the capacitor is connected with a grounding capacitor C4Microstrip line T L15Is connected with the microstrip line T L at the other end16Microstrip line T L17And a microstrip line T L18Microstrip line T L16And a microstrip line T L17The other ends of the two-dimensional three-order microstrip lines are respectively a second input end and a fifth input end of the output two-dimensional three-order artificial transmission line network, and the microstrip line T L18Is connected with the microstrip line T L at the other end19Microstrip line T L20And a microstrip line T L21Microstrip line T L20And a microstrip line T L21The other ends of the microstrip lines are respectively a third input end and a sixth input end for outputting a two-dimensional three-order artificial transmission line network, and a microstrip line T L21The other end of the capacitor C is connected with a capacitor C5Capacitor C5Is connected with the microstrip line T L at the other end22Microstrip line T L22The other end of the two-dimensional three-order artificial transmission line network is an output end for outputting the two-dimensional three-order artificial transmission line network.
The following introduces the specific working principle and process of the present invention with reference to fig. 2:
radio frequency input signal through input terminal RFinEntering the circuit, after impedance transformation matching is carried out through the first input three-order artificial transmission line and the second input three-order artificial transmission line network, simultaneously enters the input ends of a first high-gain two-pile PMOS amplifying network, a second high-gain two-pile PMOS amplifying network, a third high-gain two-pile PMOS amplifying network, a first high-gain two-pile NMOS amplifying network, a second high-gain two-pile NMOS amplifying network and a third high-gain two-pile NMOS amplifying network, after power amplification is carried out through the amplification network, the power is simultaneously output from the output ends of the first high-gain two-pile PMOS amplification network, the second high-gain two-pile PMOS amplification network, the third high-gain two-pile PMOS amplification network, the first high-gain two-pile NMOS amplification network, the second high-gain two-pile NMOS amplification network and the third high-gain two-pile NMOS amplification network, and after the power is output through the two-dimensional three-order manual transmission line network, six paths of signals are combined into one path of single-ended signal from the output end RF.outAnd (6) outputting.
Based on the circuit analysis, the utility model provides a high-power two-dimentional travelling wave CMOS power amplifier and the difference of the amplifier structure based on integrated circuit technology in the past lie in the form that the core framework adopted two heap PMOS amplifier networks of high gain and two heap NMOS amplifier networks of high gain to concatenate:
the high-gain two-stack PMOS amplifier network and the high-gain two-stack NMOS amplifier network are different from the conventional single transistor in structure, and are not described herein;
the two-dimensional distributed high-gain two-pile PMOS amplification network and the high-gain two-pile NMOS amplification network are different from the traditional distributed field effect transistor in that the traditional distributed power amplifier only has one input artificial transmission line and one output artificial transmission line, and particularly when the input impedance of a transistor is high, the capacitance voltage division is often needed to realize 50-ohm matching, so that the input matching characteristic is deteriorated, the high-frequency roll-off is serious, and the gain flatness index is poor; and the utility model discloses a two high gain of two dimension distributing types pile PMOS amplifier network and two high gain pile NMOS amplifier networks, have two artifical transmission lines of input, and the artifical transmission line of output of a sharing, the equivalence is parallelly connected for two 100 ohmic artifical transmission lines of input, and input impedance matches betterly, and simultaneously, the form that the output matches and adopts the transmission line of sharing, under the condition with traditional distributed power amplifier isopower, can show improvement efficiency and power index.
In the whole high-power enhanced field effect transistor power amplifier, the size of a transistor and the sizes of other resistors and capacitors are determined after the gain, bandwidth, output power and other indexes of the whole circuit are comprehensively considered, and through later-stage layout design and reasonable layout, the required indexes can be better realized, and the high-power output capacity, high-power gain and good input-output matching characteristic are realized.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the present invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included within the protection scope of the present invention.
Claims (8)
1. A high-power two-dimensional traveling wave CMOS power amplifier is characterized by comprising an input power dividing network, a first input three-order artificial transmission line, a second input three-order artificial transmission line, a drain electrode bias network, a first high-gain two-pile PMOS (P-channel metal oxide semiconductor) amplification network, a second high-gain two-pile PMOS amplification network, a third high-gain two-pile PMOS amplification network, a first high-gain two-pile NMOS (N-channel metal oxide semiconductor) amplification network, a second high-gain two-pile NMOS amplification network, a third high-gain two-pile NMOS amplification network and an output two-dimensional three-order artificial transmission line network;
the input end of the input power division network is the input end of the whole high-power two-dimensional traveling wave CMOS power amplifier, the first output end of the input power division network is connected with the input end of the first input three-order artificial transmission line, and the second output end of the input power division network is connected with the input end of the second input three-order artificial transmission line;
the first, second and third output ends of the first input three-order artificial transmission line are respectively connected with the first input ends of the first high-gain second-pile PMOS amplification network, the second high-gain second-pile PMOS amplification network and the third high-gain second-pile PMOS amplification network;
the first, second and third output ends of the drain electrode biasing network are respectively connected with the second input ends of the first high-gain second-pile PMOS amplification network, the second high-gain second-pile PMOS amplification network and the third high-gain second-pile PMOS amplification network;
the output ends of the first high-gain second-pile PMOS amplification network, the second high-gain second-pile PMOS amplification network and the third high-gain second-pile PMOS amplification network are connected with the first input end, the second input end and the third input end of the output two-dimensional three-order artificial transmission line network;
the first, second and third output ends of the second input three-order artificial transmission line are respectively connected with the input ends of the first high-gain second-stack NMOS amplification network, the second high-gain second-stack NMOS amplification network and the third high-gain second-stack NMOS amplification network;
the output ends of the first high-gain second-pile NMOS amplification network, the second high-gain second-pile NMOS amplification network and the third high-gain second-pile NMOS amplification network are connected with the fourth, fifth and sixth input ends of the output two-dimensional third-order artificial transmission line network;
and the output end of the output two-dimensional three-order artificial transmission line network is the output end of the whole high-power two-dimensional traveling wave CMOS power amplifier.
2. The CMOS power amplifier as claimed in claim 1, wherein the input end of the input power dividing network is connected to a microstrip line T L1Microstrip line T L1Is connected with the microstrip line T L at the other end2And a microstrip line T L3Microstrip line T L2The other end is connected with the first output end of the input power dividing network, namely a microstrip line T L3The other end of the input power dividing network is connected with the second output end of the input power dividing network.
3. The CMOS power amplifier of claim 1, wherein the input end of the first input third-order artificial transmission line is connected to a microstrip line T L23Microstrip line T L23Is connected with the microstrip line T L at the other end4And a first output end of the first input three-order artificial transmission line, namely a microstrip line T L4The other end is connected with a microstrip line T L5And a second output end of the first input three-order artificial transmission line, namely a microstrip line T L5Is connected with the microstrip line T L at the other end6And a third output end of the first input three-order artificial transmission line, namely a microstrip line T L6Another end of the resistor R is connected with a resistor R1Resistance R1Is connected with the microstrip line T L at the other end7Microstrip line T L7Is connected with a bias voltage V at the other endgAnd a ground capacitor C1。
4. The CMOS power amplifier of claim 1, wherein the input end of the second input third-order artificial transmission line is connected to a microstrip line T L24Microstrip line T L24Is connected with the microstrip line T L at the other end8And the second inputInto the first output end of the third-order artificial transmission line, microstrip line T L8The other end is connected with a microstrip line T L9And a second output end of the second input three-order artificial transmission line, namely a microstrip line T L9Is connected with the microstrip line T L at the other end10And a third output end of the second input three-order artificial transmission line, namely a microstrip line T L10Another end of the resistor R is connected with a resistor R2Resistance R2Is connected with the microstrip line T L at the other end11Microstrip line T L1The other end of the capacitor is connected with a grounding capacitor C2。
5. The high power two-dimensional travelling wave CMOS power amplifier according to claim 1, wherein said drain bias network first output terminal is connected to inductor Ls1Inductor Ls1Is connected to a second output terminal of the drain bias network and the inductor Ls2Inductor Ls2Is connected to the third output terminal of the drain bias network and the inductor Ls3Inductor Ls3Is connected with a bias voltage V at the other enddAnd a ground capacitor C3。
6. The CMOS power amplifier of claim 1, wherein said first, second and third high-gain two-stack PMOS amplifier networks constitute three amplifier networks, and wherein the first input terminal of the jth high-gain two-stack PMOS amplifier network is connected to inductor LtjInductor LtjIs connected with an inductor L at the other endmjAnd a ground capacitor CtjInductor LmjThe other end of the first electrode is connected with a field effect tube MtjA gate electrode of (1); the second input end of the jth high-gain two-stack PMOS amplification network is connected with a field effect transistor MtjDrain electrode of (1), field effect transistor MtjSource electrode of the transistor M is connected with a field effect transistor MmjDrain electrode of (1), field effect transistor MmjThe grid of the capacitor is connected with a grounding capacitor CmjAnd a resistance RcjResistance RcjThe other end of the resistor is connected with a grounding resistor RwjAnd a resistance RfjResistance RfjAnother end of (2) is connected to the field effectPipe MmjAnd the output end of the jth high-gain two-stack PMOS amplifying network, wherein j is 1, 2 and 3.
7. The CMOS power amplifier of claim 1, wherein said first, second and third high-gain NMOS amplifier networks constitute three amplifier networks, and wherein the first input terminal of the ith NMOS amplifier network is connected to an inductor LPiInductor LPiIs connected with an inductor L at the other endeiAnd a ground capacitor CpiInductor LeiThe other end of the first electrode is connected with a field effect tube MpiGrid electrode of (1), field effect transistor MpiThe source of (2) is grounded; the second input end of the ith high-gain two-stack NMOS amplification network is connected with a field effect transistor MgiDrain electrode of (1), field effect transistor MgiSource electrode of the transistor M is connected with a field effect transistor MpiDrain electrode of (1), field effect transistor MgiThe grid of the capacitor is connected with a grounding capacitor CeiAnd a resistance RgiResistance RgiThe other end of the resistor is connected with a grounding resistor R0jAnd a resistance RpiResistance RpiThe other end of the first electrode is connected with a field effect tube MgiAnd the output end of the ith high-gain two-stack NMOS amplifying network, wherein i is 1, 2 and 3.
8. The CMOS power amplifier of claim 1, wherein the first input terminal of said output two-dimensional third-order artificial transmission line network is connected to microstrip line T L13Microstrip line T L13Is connected with the microstrip line T L at the other end12Microstrip line T L14And a microstrip line T L15Microstrip line T L14The other end of the microstrip line is a fourth input end of the output two-dimensional three-order artificial transmission line network, and the microstrip line T L12Another end of the resistor R is connected with a resistor R3Resistance R3The other end of the capacitor is connected with a grounding capacitor C4Microstrip line T L15Is connected with the microstrip line T L at the other end16Microstrip line T L17And a microstrip line T L18Microstrip line T L16And a microstrip line T L17The other ends of the first and second microstrip lines are respectively a second and a fifth input ends of the output two-dimensional three-order artificial transmission line network, and the microstrip line T L18Is connected with the microstrip line T L at the other end19Microstrip line T L20And a microstrip line T L21Microstrip line T L20And a microstrip line T L21The other ends of the first and second microstrip lines are respectively a third input end and a sixth input end of the output two-dimensional three-order artificial transmission line network, and a microstrip line T L21The other end of the capacitor C is connected with a capacitor C5Capacitor C5Is connected with the microstrip line T L at the other end22Microstrip line T L22And the other end of the second-order transmission line network is an output end of the output two-dimensional three-order artificial transmission line network.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114362685A (en) * | 2021-12-14 | 2022-04-15 | 成都嘉纳海威科技有限责任公司 | Power amplifier based on high Q value differential coupling technology |
| CN114884472A (en) * | 2022-05-23 | 2022-08-09 | 王琮 | J-type distributed power amplifier based on harmonic regulation and optimization method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114362685A (en) * | 2021-12-14 | 2022-04-15 | 成都嘉纳海威科技有限责任公司 | Power amplifier based on high Q value differential coupling technology |
| CN114362685B (en) * | 2021-12-14 | 2022-09-20 | 成都嘉纳海威科技有限责任公司 | Power amplifier based on high Q value differential coupling technology |
| CN114884472A (en) * | 2022-05-23 | 2022-08-09 | 王琮 | J-type distributed power amplifier based on harmonic regulation and optimization method thereof |
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