CN116344561A - Photoelectric sensor, forming method thereof and electronic equipment - Google Patents
Photoelectric sensor, forming method thereof and electronic equipment Download PDFInfo
- Publication number
- CN116344561A CN116344561A CN202111583437.9A CN202111583437A CN116344561A CN 116344561 A CN116344561 A CN 116344561A CN 202111583437 A CN202111583437 A CN 202111583437A CN 116344561 A CN116344561 A CN 116344561A
- Authority
- CN
- China
- Prior art keywords
- layer
- pixel substrate
- opening
- metal
- pixel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 167
- 229910052751 metal Inorganic materials 0.000 claims abstract description 130
- 239000002184 metal Substances 0.000 claims abstract description 130
- 238000002955 isolation Methods 0.000 claims abstract description 103
- 238000002161 passivation Methods 0.000 claims abstract description 91
- 238000003466 welding Methods 0.000 claims abstract description 20
- 238000011049 filling Methods 0.000 claims abstract description 17
- 230000000149 penetrating effect Effects 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims description 83
- 230000008569 process Effects 0.000 claims description 33
- 229910052782 aluminium Inorganic materials 0.000 claims description 29
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 29
- 239000007769 metal material Substances 0.000 claims description 27
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 13
- 229910052721 tungsten Inorganic materials 0.000 claims description 13
- 239000010937 tungsten Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- QVQLCTNNEUAWMS-UHFFFAOYSA-N barium oxide Chemical compound [Ba]=O QVQLCTNNEUAWMS-UHFFFAOYSA-N 0.000 claims description 10
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 10
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- 229910052719 titanium Inorganic materials 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910003437 indium oxide Inorganic materials 0.000 claims description 6
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 claims description 6
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 6
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 5
- BRPQOXSCLDDYGP-UHFFFAOYSA-N calcium oxide Chemical compound [O-2].[Ca+2] BRPQOXSCLDDYGP-UHFFFAOYSA-N 0.000 claims description 5
- ODINCKMPIJJUCX-UHFFFAOYSA-N calcium oxide Inorganic materials [Ca]=O ODINCKMPIJJUCX-UHFFFAOYSA-N 0.000 claims description 5
- 239000000292 calcium oxide Substances 0.000 claims description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 5
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 5
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims description 5
- 239000000395 magnesium oxide Substances 0.000 claims description 5
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 claims description 5
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 claims description 5
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 5
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 5
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 5
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 5
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 claims 1
- 238000010276 construction Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 474
- 230000003287 optical effect Effects 0.000 description 25
- 230000009286 beneficial effect Effects 0.000 description 14
- 238000001514 detection method Methods 0.000 description 12
- 150000002500 ions Chemical class 0.000 description 11
- 239000003989 dielectric material Substances 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 230000000694 effects Effects 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 8
- 230000035945 sensitivity Effects 0.000 description 7
- 238000010521 absorption reaction Methods 0.000 description 6
- 239000012212 insulator Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 230000003190 augmentative effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000002349 favourable effect Effects 0.000 description 2
- 238000005429 filling process Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000010408 sweeping Methods 0.000 description 2
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 238000001994 activation Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14806—Structural or functional details thereof
- H01L27/14812—Special geometry or disposition of pixel-elements, address lines or gate-electrodes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
A photoelectric sensor, a forming method thereof, and an electronic device, the photoelectric sensor includes: a first opening penetrating the pixel substrate of the lead region and the dielectric layer over the interconnect layer; a first pad layer located at the bottom of the first opening and contacting the interconnection layer; a passivation layer filling the first opening and located on the first surface and covering the first pad layer and the conductive layer; the second opening is positioned in the passivation layer and exposes the first surface of the pixel substrate and the top surface of the isolation structure, and the second opening is in a grid shape; a metal layer filling the second opening and contacting the conductive layer; the second welding pad layer is positioned on the passivation layer on the first surface and connected with the metal layer. And the conducting layer of the isolation structure is connected with negative potential through the metal layer by applying negative potential to the second welding pad layer, so that positive charge is adsorbed on the side wall of the isolation structure, the interface state of the side wall of the isolation structure is improved, and the dark current of the pixel unit is reduced.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a photoelectric sensor, a forming method thereof and electronic equipment.
Background
A photosensor is a device that converts an optical signal into an electrical signal. The working principle is based on the photoelectric effect, which means that when light irradiates on certain substances, electrons of the substances absorb photon energy and corresponding electric effect phenomenon occurs.
For example, CCD (Charge Coupled Device ) image sensors and CMOS image sensors, which are widely used in digital cameras and other electronic optical devices, convert an optical image into an electrical signal by using a photoelectric conversion function and output the digital image. ToF (Time of Flight) distance sensor, for example: DTOF (Direct Time of Flight ) sensor, records the time at which the light pulse is emitted and detected, converting the time difference into distance information. The technique can be used in various ranging scenarios such as autopilot, sweeping robot, VR (Virtual Reality)/AR (Augmented Reality) modeling, etc.
However, the performance of the current photoelectric sensor still needs to be improved.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a photoelectric sensor, a forming method thereof and electronic equipment, and improves the performance of the photoelectric sensor.
To solve the above problems, an embodiment of the present invention provides a photoelectric sensor, including: the pixel substrate comprises a first surface and a second surface which are opposite to each other, the pixel substrate comprises a photosensitive area and a lead area surrounding the photosensitive area, and the photosensitive area comprises pixel unit areas which are arranged in an array; the isolation structure is positioned in the pixel substrate between the pixel unit areas and comprises a conductive layer, the top surface of the conductive layer is exposed out of the first surface, and the isolation structure is positioned in the photosensitive area; the dielectric layer is positioned on the second surface of the pixel substrate and positioned on the logic substrate; the interconnection layer is positioned in the dielectric layer of the lead area; a first opening penetrating the pixel substrate of the lead region and the dielectric layer above the interconnect layer, the first opening exposing a portion of the top of the interconnect layer toward the first surface; a first pad layer located at the bottom of the first opening and contacting the interconnection layer; the passivation layer is filled in the first opening and positioned on the first surface, and covers the first welding cushion layer and the conductive layer; the second opening is positioned in the passivation layer and exposes the first surface of the pixel substrate and the top surface of the isolation structure, and the second opening is in a grid shape; a metal layer filling the second openings in a grid shape and contacting the conductive layer; the second welding pad layer is positioned on the passivation layer on the first surface and connected with the metal layer, and the second welding pad layer is positioned between the isolation structure and the first welding pad layer.
Correspondingly, the embodiment of the invention also provides a method for forming the photoelectric sensor, which comprises the following steps: providing a pixel substrate, wherein the pixel substrate comprises a first surface and a second surface which are opposite to each other, the pixel substrate comprises a photosensitive area and a lead area surrounding the photosensitive area, the photosensitive area comprises pixel unit areas which are arranged in an array, an isolation structure is formed in the pixel substrate between the pixel unit areas, the isolation structure comprises a conducting layer, and the top surface of the conducting layer is exposed out of the first surface; a dielectric layer is formed on the second surface, and an interconnection layer is formed in the dielectric layer of the lead area; forming a first opening penetrating through the pixel substrate of the lead area and the dielectric layer above the interconnection layer, wherein the first opening exposes a part of the top of the interconnection layer facing the first surface; forming a first pad layer in contact with the interconnection layer at the bottom of the first opening; forming a passivation layer filling the first opening and located on the first surface, wherein the passivation layer covers the first pad layer and the conductive layer; and forming a metal layer penetrating through the passivation layer above the isolation structure and contacting with the conductive layer, and a second welding pad layer positioned on the passivation layer on the first surface and connected with the metal layer, wherein the metal layer is in a grid shape.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
In the photoelectric sensor provided by the embodiment of the invention, the metal layer fills the second openings in the grid shape and is in contact with the conductive layer; the second welding cushion layer is positioned on the passivation layer on the first surface and is connected with the metal layer, accordingly, when the photoelectric sensor works, the conductive layer of the isolation structure is easily connected with negative potential through the metal layer in a negative potential application mode, so that positive charges are adsorbed on the side wall of the isolation structure, interface states of the side wall of the isolation structure are improved, and dark current of a pixel unit is reduced; in addition, compared with the mode of improving the interface state of the side wall of the isolation structure by carrying out P-type ion doping on the pixel substrate, the embodiment of the invention is also beneficial to avoiding being limited by the ion implantation depth, and correspondingly the absorption thickness and the optical path of light are easy to be increased by increasing the thickness of the pixel substrate, so that the photon detection efficiency of a photosensitive area is improved, and the photon detection sensitivity performance of a photoelectric sensor is improved; in summary, the embodiment of the invention optimizes the performance of the photoelectric sensor.
In the method for forming the photoelectric sensor provided by the embodiment of the invention, the second welding cushion layer which penetrates through the passivation layer above the isolation structure and is in contact with the conductive layer and the second welding cushion layer which is positioned on the passivation layer on the first surface and is connected with the metal layer are formed, accordingly, when the photoelectric sensor works, the conductive layer of the isolation structure is connected with the negative potential through the metal layer in a negative potential applying way, so that positive charges are adsorbed on the side wall of the isolation structure, the interface state of the side wall of the isolation structure is improved, and dark current of a pixel unit is reduced; in addition, compared with the mode of improving the interface state of the side wall of the isolation structure by carrying out P-type ion doping on the pixel substrate, the embodiment of the invention is also beneficial to avoiding being limited by the ion doping depth, and correspondingly the absorption thickness and the optical path of light are easy to be increased by increasing the thickness of the pixel substrate, so that the photon detection efficiency of a photosensitive area is improved, and the photon detection sensitivity performance of a photoelectric sensor is improved; in summary, the embodiment of the invention optimizes the performance of the photoelectric sensor.
Drawings
Fig. 1 to 6 are schematic structural views corresponding to steps in a method for forming a photoelectric sensor;
FIGS. 7 and 8 are schematic structural views of an embodiment of the photoelectric sensor of the present invention;
fig. 9 to 18 are schematic structural views corresponding to each step in an embodiment of a method for forming a photoelectric sensor according to the present invention.
Detailed Description
As known from the background art, the performance of the current photoelectric sensor needs to be improved. The reason why the performance of a photoelectric sensor is to be improved is now analyzed in conjunction with a method of forming a photoelectric sensor. Fig. 1 to 6 are schematic structural views corresponding to each step in a method for forming a photoelectric sensor.
Referring to fig. 1, a pixel substrate 10 is provided, including a first surface 11 and a second surface 12 opposite to each other, the pixel substrate includes a photosensitive region 10P and a lead region 10N surrounding the photosensitive region 10P, the photosensitive region 10P includes pixel unit regions (not labeled) arranged in an array, an isolation structure 13 is formed in the pixel substrate 10 between the pixel unit regions, and a top surface of the isolation structure 13 is exposed from the first surface 11; a dielectric layer 14 is formed on the second surface 12, and an interconnection layer 15 is formed in the dielectric layer 14 of the lead area 10N; a logic substrate (not shown) is also bonded to the dielectric layer 14 of the second surface 12.
Referring to fig. 2, an opening 16 is formed through the pixel substrate 10 of the lead region 10N and the dielectric layer 14 over the interconnect layer 15, the opening 16 exposing a portion of the top of the interconnect layer 15 toward the first surface 11.
Referring to fig. 3, a pad layer 17 contacting the interconnect layer 15 is formed at the bottom of the opening 16.
Referring to fig. 4, a passivation layer 18 is formed filling the opening 16 and being located on the first surface 11, the passivation layer 18 covering the pad layer 17 and the top surface of the isolation structure 13.
Referring to fig. 5, a mesh-like metal layer 19 is formed on the passivation layer 18 on top of the isolation structure 13.
Referring to fig. 6, after forming the metal layer 19, an interconnection trench 20 penetrating the passivation layer 18 above the pad layer 17 is formed, exposing the pad layer 17.
In the above forming method, the step of forming the isolation structure generally includes: forming an isolation trench in the pixel substrate 10 between adjacent pixel cell areas; an isolation structure is formed within the isolation trench. The isolation trench is usually formed by an etching process, the isolation structure is formed in the isolation trench by a filling process, after the etching process and the filling process are performed, interface states are usually generated on the side wall of the isolation structure, the surface of the interface states can absorb negative charge electron layers in an inverted mode, and dark current of the pixel unit can be increased due to the existence of the interface states.
In order to prevent dark current caused by interface states, P-type ion implantation is typically performed on the pixel substrate before bonding of the pixel substrate to the logic substrate is achieved. By carrying out P-type ion implantation, the negative charge electron layer in the interface state can be neutralized to a certain extent, the problem of dark current caused by the interface state is correspondingly improved,
however, in the field of photosensors, the absorption thickness and optical path length of light are generally increased by increasing the thickness of the pixel substrate, thereby increasing photon detection efficiency and thus photon detection sensitivity.
With the gradual increase of the thickness of the pixel substrate, when the thickness of the pixel substrate is greater than the maximum depth of ion implantation, the side wall of the isolation structure cannot be completely surrounded by P-type ions, and when the photoelectric sensor works, the side wall of the isolation structure which is not surrounded by the P-type ions can increase the dark current of the pixel. In addition, when the first surface is the back surface of the pixel substrate, the front-stage device is already manufactured due to the fact that ion implantation is performed, and in order to prevent adverse effects on the electrical performance of the front-stage device, even if ion implantation can be performed, the implanted ions cannot be subjected to a high-temperature activation process, and the ion implantation cannot perform a corresponding function.
In order to solve the technical problem, the embodiment of the invention provides a photoelectric sensor, wherein a metal layer is filled in a second opening in a grid shape and is in contact with a conductive layer; the second welding cushion layer is positioned on the passivation layer on the first surface and is connected with the metal layer, accordingly, when the photoelectric sensor works, the conductive layer of the isolation structure is easily connected with negative potential through the metal layer in a negative potential application mode, so that positive charges are adsorbed on the side wall of the isolation structure, interface states of the side wall of the isolation structure are improved, and dark current of a pixel unit is reduced; in addition, compared with the mode of improving the interface state of the side wall of the isolation structure by carrying out P-type ion doping on the pixel substrate, the embodiment of the invention is also beneficial to avoiding being limited by the ion implantation depth, and correspondingly the absorption thickness and the optical path of light are easy to be increased by increasing the thickness of the pixel substrate, so that the photon detection efficiency of a photosensitive area is improved, and the photon detection sensitivity performance of a photoelectric sensor is improved; in summary, the embodiment of the invention optimizes the performance of the photoelectric sensor.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Referring to fig. 7 and 8, a schematic structural diagram of an embodiment of the photoelectric sensor of the present invention is shown.
As an example, the present embodiment is described with a photoelectric sensor as a TOF (Time of Flight) sensor as an example. More specifically, the photosensor may be a DTOF (Direct Time of Flight ) sensor. In other embodiments, the photosensor may also be an iTOF (indirect Time of Flight ) sensor.
In other embodiments, the photosensor may also be a CCD (Charge Coupled Device ) image sensor, a CMOS image sensor, or other type of photosensor.
As shown in fig. 7 and 8, in the present embodiment, the photoelectric sensor includes: the pixel substrate 100 includes a first surface 101 and a second surface 102 opposite to each other, the pixel substrate 100 includes a photosensitive region 100P and a lead region 100N surrounding the photosensitive region 100P, and the photosensitive region 100P includes pixel unit regions (not labeled) arranged in an array; the isolation structure is positioned in the pixel substrate 100 between the pixel unit areas and comprises a conductive layer 110, the top surface of the conductive layer 110 is exposed out of the first surface 101, and the isolation structure is positioned in the photosensitive area 100P; a dielectric layer 120 on the second surface 102 of the pixel substrate 100, the dielectric layer 120 being on the logic substrate; an interconnect layer 130 located within dielectric layer 120 of lead region 100N; a first opening 140 (refer to fig. 10 in combination), penetrating the dielectric layer 120 over the pixel substrate 100 and the interconnect layer 130 of the lead region 100N, the opening 140 exposing a portion of the top of the interconnect layer 130 toward the first surface 101; a first pad layer 150 located at the bottom of the first opening 140 and contacting the interconnect layer 130; a passivation layer 160 filling the first opening 140 and located on the first surface 101, the passivation layer 160 covering the first pad layer 150 and the conductive layer 110; a second opening 170 (refer to fig. 14 in combination) located in the passivation layer 160 and exposing the first surface 101 of the pixel substrate 100 and the top surface of the isolation structure, the second opening having a grid shape; a metal layer 210 filling the second openings in a grid shape and contacting the conductive layer 110; the second pad layer 220 is located on the passivation layer 160 of the first surface 101 and is connected to the metal layer 210.
The pixel substrate 100 is used to provide an operational platform for the formation of photosensors. In this embodiment, the pixel base 100 includes a substrate. In particular, the material of the substrate may include one or more of silicon, germanium, silicon carbide, gallium arsenide, and indium gallium. As an example, the substrate is a silicon substrate. In other embodiments, the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, among other types of substrates.
In this embodiment, the first surface 101 is a back surface of the pixel substrate 100, and the second surface 102 is a front surface of the pixel substrate 100. Specifically, the pixel substrate 100 is a backside illuminated (Backside Illumination, BSI) pixel wafer, and the first surface 101 of the pixel substrate 100 is a light-receiving surface.
The pixel substrate 100 includes a photosensitive region 100P, and the photosensitive region 100P is configured to receive an optical signal and convert the optical signal into an electrical signal. In this embodiment, the photosensitive area 100P includes an array of pixel unit areas, in which pixel units (not shown) are formed, and the pixel units are configured to receive optical signals so as to convert the optical signals into electrical signals.
The lead region 100N is used for wiring and forming leads to make electrical connection between the pixel cell or other device structure and external circuitry.
The isolation structure is used to reduce optical and electrical crosstalk between adjacent pixel cells. In this embodiment, the isolation structure is a deep trench isolation (Deep Trench Isolation, DTI) structure. In this embodiment, the isolation structure includes the conductive layer 110, so that a voltage is applied to the conductive layer 110 subsequently, thereby adsorbing positive charges on the sidewall of the isolation structure, further improving the interface state of the sidewall of the isolation structure, and reducing dark current of the pixel unit.
The end of the conductive layer 110 is exposed on the first surface 101, so that the metal layer 210 contacts the conductive layer 110, and the electrical property of the conductive layer 110 can be led out through the metal layer 210. In this embodiment, the material of the conductive layer 110 is a metal material. The metal material has good conductivity, is usually an opaque material, and can also play a role in isolating light between adjacent pixel units.
In this embodiment, the material of the conductive layer 110 includes one or more of tungsten, aluminum, titanium nitride, tantalum nitride, and copper. As an embodiment, the material of the conductive layer 110 is tungsten, which is not easy to diffuse and has superior hole filling capability, so that the filling effect of the conductive layer 110 in the deep trench is improved, and the tungsten is a light-tight metal material, which can play a role in light isolation, and is beneficial to making the reduction effect of the optical crosstalk between the isolation structure 110 and the adjacent pixel units more remarkable.
In this embodiment, the isolation structure further includes: an insulating layer (not shown) is located between the conductive layer 110 and the pixel substrate 100. The insulating layer serves to insulate between the conductive layer 110 and the pixel substrate 100. In this embodiment, the material of the insulating layer includes any one or more of silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, lanthanum oxide, and barium oxide.
In this embodiment, an insulating layer is also formed on the first surface 101 on the side of the conductive layer 110. In this embodiment, the insulating layer includes a negatively charged dielectric layer (not shown), which has a more comprehensive negative charge than the conventional dielectric layer, and the negative charge can increase hole accumulation at the interface of the negatively charged dielectric layer, and can correspondingly collect holes at the bottom and the side wall of the isolation structure, so as to form a P-type protection structure, which is beneficial to improving the leakage problem of the side wall of the isolation structure.
More specifically, the material of the negatively charged dielectric layer comprises a high-k dielectric material. As an example, the high-k dielectric material includes any one or more of aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, lanthanum oxide, and barium oxide.
The dielectric layer 120 is formed with pixel interconnection lines, and the dielectric layer 120 is used for realizing isolation between the pixel interconnection lines. The material of the dielectric layer 120 is a dielectric material, for example: one or more of silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, and ultra-low-k dielectric material.
The pixel interconnection lines are used to make electrical connection between the pixel cells and external circuitry or other interconnection structures. Specifically, the pixel interconnection includes one or more layers of interconnection lines.
In this embodiment, the pixel interconnect includes an interconnect layer 130 within the dielectric layer 120 of the lead region 100N. The interconnection layer 130 is used for realizing circuit connection between the pixel units, and is also used for realizing electric connection between the pixel units and the subsequent first pad layers, so as to realize electric connection between the pixel units and an external circuit. The material of the interconnect layer 130 is metal, for example: copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.
In this embodiment, the photoelectric sensor further includes: the logic substrate 200 is bonded to the dielectric layer 120 of the second surface 102 of the pixel substrate 100. The Logic substrate 200 serves as a Logic Wafer (Logic Wafer) for analyzing the electrical signals provided by the pixel substrate 100. Specifically, a logic device for analyzing and processing the electrical signal supplied from the pixel substrate 100 is formed in the logic substrate 200.
By disposing the pixel region (i.e., the photosensitive region) and the logic region on different substrates, and bonding the pixel substrate 100 and the logic substrate 200 together, the pixel area is advantageously increased, the path of light reaching the photoelectric element is advantageously shortened, the scattering of light is reduced, the light is more focused, the photosensitive capability of the photoelectric sensor in a low-light environment is further improved, and system noise and crosstalk are reduced.
As an embodiment, the bonding between the logic substrate 200 and the dielectric layer 120 of the second surface 102 of the pixel substrate 100 is achieved by Hybrid bonding (Hybrid bonding).
The bottom of the first opening 140 is used to provide a space for forming the first pad layer 150, and the first opening 140 exposes a portion of the top of the interconnect layer 130 so that the first pad layer 150 can contact the interconnect layer 130, thereby making an electrical connection between the first pad layer 150 and the interconnect layer 130.
The first pad layer 150 is for contacting the interconnect layer 130 for making electrical connection between the interconnect layer 130 and an external circuit or other interconnect structure. The material of the first pad layer 150 is a conductive material. In this embodiment, the material of the first pad layer 150 includes one or more of aluminum, titanium, gold, and tin-doped indium oxide. As an embodiment, the material of the first pad layer 150 is aluminum. Aluminum has good conductivity, and aluminum is a material that is easily etched, so that the first pad layer 150 is easily formed in a patterned manner.
The first pad layer 150 is located in the first opening 140, and the top surface of the first pad layer 150 is lower than the first surface 101.
The passivation layer 160 is used to fill the first opening 140 to provide a planar surface for the process. The first passivation layer 160 also serves to protect the first pad layer 150. In this embodiment, the material of the passivation layer 160 is an insulating material, and the material of the passivation layer 160 includes one or more of silicon oxide, silicon oxynitride, and silicon nitride. As an embodiment, the passivation layer 160 is made of silicon oxide.
The second opening 170 is used to provide a space for forming the metal layer 210, and the second opening 170 exposes the top surface of the conductive layer 110 so that the metal layer 210 can contact with the conductive layer 110.
The metal layer 210 corresponds to the position and shape of the isolation structure, and the region surrounded by the metal layer 210 corresponds to each pixel cell region, thereby preventing optical crosstalk between adjacent pixel cells.
Specifically, the metal layer 210 fills the second openings 170 in the grid shape, the metal layer 210 is correspondingly in a grid structure, and the metal layer 210 is located on the first surface 101 of the pixel substrate 100, that is, the metal layer 210 is located on the back surface of the pixel substrate 100, and the metal layer 210 is a back metal layer.
The metal layer 210 penetrates the passivation layer 160 over the isolation structure and contacts the conductive layer 110, so that the metal layer 210 serves to make electrical connection between the conductive layer 110 and the second pad layer 220.
In this embodiment, the metal layer 210 is in contact with a portion of the top surface of the conductive layer 110, or the metal layer 210 is in contact with the top surface of all of the conductive layer 110. In this case, since the conductive layers 110 in the respective isolation structures are connected, even if the metal layer 210 is in contact with only a portion of the top surface of the conductive layer 110, electrical connection between the entire conductive layer 110 and an external circuit can be achieved through the metal layer 210.
In this embodiment, the material of the metal layer 210 is a metal material, and the material of the metal layer 210 includes one or both of aluminum and tungsten. As an example, the material of the metal layer 210 is aluminum. Aluminum is a material which is easy to etch, so that a patterning process for forming the metal layer 210 is convenient to carry out, the aluminum has good conductivity, the electrical connection performance of the metal layer 210 is improved, and in addition, aluminum is a light-tight material, so that the effect of reducing optical crosstalk between adjacent pixel units by the metal layer 210 is ensured.
The second pad layer 220 is located on the passivation layer 160 of the first surface 101 and is connected with the metal layer 210, so as to realize electrical connection between the metal layer 210 and an external circuit, so that when the photoelectric sensor works, the conductive layer 110 of the isolation structure can be connected to the negative potential through the metal layer 210 by applying the negative potential to the second pad layer 220, thereby being beneficial to adsorbing positive charges on the side wall of the isolation structure, further being beneficial to improving the interface state of the side wall of the isolation structure, and reducing the dark current of the pixel unit.
In addition, compared with the mode of improving the interface state of the side wall of the isolation structure by carrying out P-type ion doping on the pixel substrate, the embodiment is also beneficial to avoiding being limited by the ion doping depth, and the absorption thickness and the optical path of light are increased by increasing the thickness of the pixel substrate 100 correspondingly, so that the photon detection efficiency of a photosensitive area is improved, and the photon detection sensitivity performance of the photoelectric sensor is improved.
In summary, this embodiment optimizes the performance of the photosensor.
In this embodiment, the material of the second pad layer 220 is a metal material. As an example, the material of the second pad layer 220 includes one or more of aluminum, titanium, gold, and tin-doped indium oxide. In this embodiment, the material of the second pad layer 220 is the same as the material of the metal layer 210.
More specifically, in the present embodiment, the second pad layer 220 and the metal layer 210 are formed as an integral structure, and the second pad layer 220 and the metal layer 210 are formed in the same step, so that not only is the process flow simplified, but also the electrical connection performance between the second pad layer 220 and the metal layer 210 is improved.
In this embodiment, the photoelectric sensor further includes: the ground line 230 penetrates the passivation layer 160 of a partial width and contacts the pixel substrate 100. The ground line 230 has a space from the metal layer 210 and the second pad layer 220. In this embodiment, the ground line 230 also penetrates a portion of the thickness of the pixel substrate 100.
During the formation of the second pad layer 220 and the metal layer 210, more charges are generally generated, and the ground line 230 contacts the pixel substrate 100, so as to release charges through the pixel substrate 100 during the formation of the second pad layer 220 and the metal layer 210, and prevent charges from accumulating on the first surface 101 of the pixel substrate 100, thereby preventing arcing (arcing) during the formation of the second pad layer 220 and the metal layer 210.
In this embodiment, the material of the grounding line 230 is the same as that of the metal layer 210. Specifically, in the present embodiment, the ground line 230, the metal layer 210 and the second pad layer 220 are formed in the same step, and the top surface of the ground line 230 is flush with the top surfaces of the metal layer 210 and the second pad layer 220.
In order to solve the problem, the invention also provides a method for forming the photoelectric sensor. Fig. 9 to 18 are schematic structural views corresponding to each step in an embodiment of a method for forming a photoelectric sensor according to the present invention.
As an example, the present embodiment is described with a photoelectric sensor as a TOF (Time of Flight) sensor as an example. More specifically, the photosensor may be a DTOF (Direct Time of Flight ) sensor. In other embodiments, the photosensor may also be an iTOF (indirect Time of Flight ) sensor.
In other embodiments, the photosensor may also be a CCD (Charge Coupled Device ) image sensor, a CMOS image sensor, or other type of photosensor.
The method of forming the photoelectric sensor of the present embodiment will be described in detail below with reference to the accompanying drawings.
Referring to fig. 9, a pixel substrate 100 is provided, including a first surface 101 and a second surface 102 opposite to each other, the pixel substrate 100 includes a photosensitive region 100P and a lead region 100N surrounding the photosensitive region 100P, the photosensitive region 100P includes pixel unit regions (not labeled) arranged in an array, an isolation structure is formed in the pixel substrate 100 between the pixel unit regions, the isolation structure includes a conductive layer 110, and a top surface of the conductive layer 110 is exposed from the first surface 101; a dielectric layer 120 is formed on the second surface 102, and an interconnect layer 130 is formed within the dielectric layer 120 of the lead region 100N.
The pixel substrate 100 is used to provide an operation platform for subsequent processing. In this embodiment, the pixel base 100 includes a substrate. In particular, the material of the substrate may include one or more of silicon, germanium, silicon carbide, gallium arsenide, and indium gallium. As one example, the substrate is a silicon substrate. In other embodiments, the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, among other types of substrates.
In this embodiment, the first surface 101 is a back surface of the pixel substrate 100, and the second surface 102 is a front surface of the pixel substrate 100. Specifically, the pixel substrate 100 is a back-illuminated (BSI) pixel wafer, and the first surface 101 of the pixel substrate 100 is a light-receiving surface.
The pixel substrate 100 includes a photosensitive region 100P, and the photosensitive region 100P is configured to receive an optical signal and convert the optical signal into an electrical signal. In this embodiment, the photosensitive area 100P includes an array of pixel unit areas, in which pixel units (not shown) are formed, and the pixel units are configured to receive optical signals so as to convert the optical signals into electrical signals.
The lead region 100N is used for wiring and forming leads to make electrical connection between the pixel cell or other device structure and external circuitry.
The isolation structure is used to reduce optical and electrical crosstalk between adjacent pixel cells. In this embodiment, the isolation structure is a Deep Trench Isolation (DTI) structure. In this embodiment, the isolation structure includes the conductive layer 110, so that a voltage is applied to the conductive layer 110 subsequently, thereby adsorbing positive charges on the sidewall of the isolation structure, thereby being beneficial to improving the interface state of the sidewall of the isolation structure and reducing dark current of the pixel unit.
The end of the conductive layer 110 is exposed on the first surface 101, so that a metal layer contacting with the conductive layer 110 can be formed on the first surface 101 later, and the electrical property of the conductive layer 110 is led out through the metal layer.
In this embodiment, the material of the conductive layer 110 is a metal material. The metal material has good conductivity, is usually an opaque material, and can also play a role in isolating light between adjacent pixel units.
In this embodiment, the material of the conductive layer 110 includes one or more of tungsten, aluminum, titanium nitride, tantalum nitride, and copper. As an embodiment, the material of the conductive layer 110 is tungsten, which is not easy to diffuse and has superior hole filling capability, so that the filling effect of the conductive layer 110 in the deep trench is improved, and the tungsten is a light-tight metal material, which can play a role in light isolation, and is beneficial to making the reduction effect of the optical crosstalk between the isolation structure 110 and the adjacent pixel units more remarkable.
In this embodiment, the isolation structure further includes: an insulating layer (not shown) is located between the conductive layer 110 and the pixel substrate 100. The insulating layer serves to insulate between the conductive layer 110 and the pixel substrate 100. The material of the insulating layer includes any one or more of silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, lanthanum oxide, and barium oxide.
In this embodiment, an insulating layer is also formed on the first surface 101 on the side of the conductive layer 110.
In this embodiment, the insulating layer includes a negatively charged dielectric layer (not shown), which has a more comprehensive negative charge than the conventional dielectric layer, and the negative charge can increase hole accumulation at the interface of the negatively charged dielectric layer, and can correspondingly collect holes at the bottom and the side wall of the isolation structure, so as to form a P-type protection structure, which is beneficial to improving the leakage problem of the side wall of the isolation structure. More specifically, the material of the negatively charged dielectric layer comprises a high-k dielectric material. As an example, the high-k dielectric material includes any one or more of aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, lanthanum oxide, and barium oxide.
In this embodiment, the step of forming the isolation structure includes: forming an isolation trench (not shown) in the pixel substrate 100 between adjacent pixel cell regions; an insulating layer on the sidewalls and bottom of the isolation trench, and a conductive layer 110 on the insulating layer and filling the isolation trench are formed.
The dielectric layer 120 is formed with pixel interconnection lines, and the dielectric layer 120 is used for realizing isolation between the pixel interconnection lines. The material of the dielectric layer 120 is a dielectric material, for example: one or more of silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, and ultra-low-k dielectric material.
The pixel interconnection lines are used to make electrical connection between the pixel cells and external circuitry or other interconnection structures. Specifically, the pixel interconnection includes one or more layers of interconnection lines. In this embodiment, the pixel interconnect includes an interconnect layer 130 within the dielectric layer 120 of the lead region 100N. The interconnection layer 130 is used for realizing circuit connection between the pixel units, and is also used for realizing electric connection between the pixel units and the subsequent first pad layers, so as to realize electric connection between the pixel units and an external circuit. The material of the interconnect layer 130 is metal, for example: copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.
In this embodiment, the logic substrate 200 is further bonded on the dielectric layer 120 of the second surface 102 of the pixel substrate 100. The logic substrate 200 serves as a logic wafer for analyzing the electrical signals provided by the pixel substrate 100. Specifically, a logic device for analyzing and processing the electrical signal supplied from the pixel substrate 100 is formed in the logic substrate 200.
By arranging the pixel region and the logic region on different substrates respectively and bonding the pixel substrate 100 and the logic substrate 200 together, the pixel area is increased, the path of light reaching the photoelectric element is shortened, the scattering of light is reduced, the light is focused more, the photosensitivity of the photoelectric sensor in a weak light environment is improved, and the system noise and crosstalk are reduced.
As an embodiment, the bonding between the logic substrate 200 and the dielectric layer 120 of the second surface 102 of the pixel substrate 100 is achieved by Hybrid bonding (Hybrid bonding).
As one example, the step of providing the pixel substrate 100 to which the logic substrate is bonded includes: providing a pixel substrate 100; providing a logic substrate 200; bonding between the dielectric layer 120 of the second side 102 of the pixel substrate 100 and the logic substrate 200 is achieved; after bonding is achieved, thinning processing is performed on the first surface 101 of the pixel substrate 100; after the thinning process, an isolation structure is formed in the pixel substrate 100 between adjacent pixel unit areas.
Referring to fig. 10, a first opening 140 is formed through the pixel substrate 100 of the lead region 100N and the dielectric layer 120 over the interconnect layer 130, the first opening 140 exposing a portion of the top of the interconnect layer 130 toward the first surface 101. The bottom of the first opening 140 is used to provide a space for forming the first pad layer, and the first opening 140 exposes a portion of the top of the interconnect layer 130, so that the first pad layer formed at the bottom of the first opening 140 can contact the interconnect layer 130, thereby achieving an electrical connection between the first pad layer and the interconnect layer 130.
As an embodiment, the step of forming the first opening 140 includes: forming a top opening 141 of the pixel substrate 100 penetrating the lead region 100N, the top opening exposing the dielectric layer 120; a bottom opening 142 is formed through the dielectric layer 120 under the top opening 141 exposing a portion of the top of the interconnect layer 130 towards the first surface 101, the bottom opening 142 and the top opening 141 constituting the first opening 140.
As an example, the top opening 141 of the pixel substrate 100 penetrating the lead region 100N is formed using an anisotropic dry etching process. The anisotropic dry etching process has high etching profile control, and is favorable for precisely controlling the profile of the top opening 141.
As an example, a bottom opening 142 is formed through the dielectric layer 120 under the top opening 141 using an anisotropic dry etching process. The anisotropic dry etching process has high etching profile control, is favorable for precisely controlling the profile of the bottom opening 142, and reduces the probability of misetching the interconnection layer 130.
In this embodiment, after forming the top opening 141 and before forming the bottom opening 142, the method for forming the photoelectric sensor further includes: an isolation layer (not shown) is formed on the sidewalls and bottom of the top opening 141 and the first surface 101, and also covers the conductive layer 110.
The isolation layer is used for protecting the pixel substrate 100 and isolating the pixel substrate 100 from the subsequent first pad layer. In this embodiment, the material of the isolation layer is silicon oxide.
Referring to fig. 11, a first pad layer 150 contacting the interconnect layer 130 is formed at the bottom of the first opening 140. The first pad layer 150 is in contact with the interconnect layer 130 for making electrical connection between the interconnect layer 130 and an external circuit or other interconnect structure. The first pad layer 150 is located in the first opening 140, and the top surface of the first pad layer 150 is lower than the first surface 101.
The material of the first pad layer 150 is a conductive material. In this embodiment, the material of the first pad layer 150 includes one or more of aluminum, titanium, gold, and tin-doped indium oxide. As an embodiment, the material of the first pad layer 150 is aluminum. Aluminum has good conductivity, and aluminum is a material that is easily etched, so that the first pad layer 150 is easily formed in a patterned manner.
In this embodiment, the step of forming the first pad layer 150 includes: forming a first pad material layer (not shown) on the bottom and sidewalls of the first opening 140 and the first surface 101; a portion of the first pad material layer located on the first surface 101 and at the bottom of the first opening 140 is removed, and the remaining first pad material layer located at the bottom of the first opening 140 is used as the first pad layer 150.
Referring to fig. 12 and 13, a passivation layer 160 (as shown in fig. 13) is formed filling the first opening 140 and on the first surface 101, the passivation layer 160 covering the first pad layer 150 and the conductive layer 110. The passivation layer 160 is used to fill the first opening 140 to provide a planar surface for subsequent processing. The passivation layer 160 also protects the first pad layer 150 from the subsequent process.
In this embodiment, the passivation layer 160 is made of an insulating material, including one or more of silicon oxide, silicon oxynitride, and silicon nitride. As an embodiment, the passivation layer 160 is made of silicon oxide.
In this embodiment, the step of forming the passivation layer 160 includes: as shown in fig. 12, a passivation material layer 155 is formed to fill the first opening 140 and is further located on the first surface 101, the passivation material layer 155 covers the first pad layer 150 and the conductive layer 110, and a groove (not shown) corresponding to the first opening 140 is formed in the passivation material layer 155; as shown in fig. 12, a pattern layer 145 is formed in the groove; as shown in fig. 13, the passivation material layer 155 exposed from the pattern layer 145 is thinned; as shown in fig. 13, the graphics layer 145 is removed; as shown in fig. 13, after the pattern layer 145 is removed, the passivation material layer 155 is planarized, and the remaining passivation material layer 155 is used as the passivation layer 160.
The passivation material layer 155 is used to form a passivation layer. As an example, the passivation material layer 155 is formed using a chemical vapor deposition process.
The pattern layer 145 serves as a mask for thinning the passivation material layer 155. In this embodiment, the material of the pattern layer 145 is photoresist.
By thinning the passivation material layer 155 exposed by the pattern layer 145, a thickness difference between the passivation material layer 155 on the top surface of the pixel substrate 100 and the passivation material layer 155 in the first opening 140 is reduced, and a top surface consistency of the passivation material layer 155 is improved, which is beneficial to a subsequent planarization process of the passivation material layer 155.
Specifically, the passivation material layer 155 exposed from the pattern layer 145 is thinned by an etching process. The etching process facilitates precise control of the reduced thickness of the passivation material layer 155.
The passivation material layer 155 is planarized to improve the top surface flatness of the passivation layer, so as to provide a flat surface for a subsequent process. As an example, the passivation material layer 155 is planarized using a chemical mechanical polishing process.
In this embodiment, during the planarization process of the passivation material layer 155, the passivation material layer 155 on the top surface of the pixel substrate 100 is also kept to have a partial thickness so as not to damage the conductive layer 110 by the planarization process.
Referring to fig. 14 to 16, a metal layer 210 penetrating the passivation layer 160 over the isolation structure and contacting the conductive layer 110, and a second pad layer 220 on the passivation layer 160 of the first surface 101 and connected to the metal layer 210 are formed, the metal layers having a mesh shape.
In this embodiment, the second pad layer 220 is used for accessing a negative potential, and when the photoelectric sensor works, the negative potential is easily applied to the second pad layer 220, so that the conductive layer 110 of the isolation structure is accessed to the negative potential through the metal layer 210, thereby facilitating the adsorption of positive charges on the side wall of the isolation structure, further improving the interface state of the side wall of the isolation structure, and reducing the dark current of the pixel unit.
In addition, compared with the mode of improving the interface state of the side wall of the isolation structure by carrying out P-type ion doping on the pixel substrate, the embodiment is also beneficial to avoiding being limited by the ion doping depth, and the absorption thickness and the optical path of light are increased by increasing the thickness of the pixel substrate 100 correspondingly, so that the photon detection efficiency of a photosensitive area is improved, and the photon detection sensitivity performance of the photoelectric sensor is improved.
In summary, this embodiment optimizes the performance of the photosensor.
The metal layer 210 corresponds to the position and shape of the isolation structure, and the region surrounded by the metal layer 210 corresponds to each pixel cell region, thereby preventing optical crosstalk between adjacent pixel cells. Specifically, the metal layer 210 is a grid structure, and the metal layer 210 is located on the first surface 101 of the pixel substrate 100, i.e. the metal layer 210 is located on the back surface of the pixel substrate 100, and the metal layer 210 is a back metal grid.
The metal layer 210 penetrates the passivation layer 160 over the isolation structure and contacts the conductive layer 110, so that the metal layer 210 serves to make electrical connection between the conductive layer 110 and the second pad layer 220.
In this embodiment, the metal layer 210 is in contact with a portion of the top surface of the conductive layer 110, or the metal layer 210 is in contact with the top surface of all of the conductive layer 110. In this case, since the conductive layers 110 in the respective isolation structures are connected, even if the metal layer 210 is in contact with only a portion of the top surface of the conductive layer 110, electrical connection between the entire conductive layer 110 and an external circuit can be achieved through the metal layer 210.
In this embodiment, the material of the metal layer 210 is a metal material, and the material of the metal layer 210 includes one or both of aluminum and tungsten. As an example, the material of the metal layer 210 is aluminum. Aluminum is a material which is easy to etch, so that a patterning process for forming the metal layer 210 is convenient to carry out, the aluminum has good conductivity, the electrical connection performance of the metal layer 210 is improved, and in addition, aluminum is a light-tight material, so that the effect of reducing optical crosstalk between adjacent pixel units by the metal layer 210 is ensured.
The second pad layer 220 is located on the passivation layer 160 of the first surface 101 and is connected to the metal layer 210, so as to realize electrical connection between the metal layer 210 and an external circuit, so that when the photoelectric sensor works, the conductive layer 110 can be connected to a negative potential by applying a negative potential to the second pad layer 220.
In this embodiment, the material of the second pad layer 220 is a metal material. As an example, the material of the second pad layer 220 includes one or more of aluminum, titanium, gold, and tin-doped indium oxide.
In this embodiment, the material of the second pad layer 220 is the same as the material of the metal layer 210.
More specifically, in the present embodiment, the second pad layer 220 and the metal layer 210 are formed in the same step, and the second pad layer 220 and the metal layer 210 are in an integrated structure, so that not only is the process flow simplified, but also the electrical resistance is reduced, and the electrical connection performance between the second pad layer 220 and the metal layer 210 is improved.
The forming method further includes: in the step of forming the metal layer 210, a ground line 230 penetrating the partial width passivation layer 160 on the pixel substrate 100 is also formed, and the ground line 230 is in contact with the pixel substrate 100. The ground line 230 has a space from the metal layer 210 and the second pad layer 220.
During the formation of the second pad layer 220 and the metal layer 210, more charges are generally generated, and the ground line 230 contacts the pixel substrate 100, so as to release charges through the pixel substrate 100 during the formation of the second pad layer 220 and the metal layer 210, and prevent charges from accumulating on the first surface 101 of the pixel substrate 100, thereby preventing arcing (arcing) during the formation of the second pad layer 220 and the metal layer 210. In this embodiment, the ground line 230 also penetrates a portion of the thickness of the pixel substrate 100.
In this embodiment, the material of the grounding line 230 is the same as that of the metal layer 210.
The specific steps for forming the metal layer 210, the second pad layer 220, and the ground line 230 according to this embodiment will be described below with reference to the accompanying drawings.
As shown in fig. 14, a second opening 170 is formed through the passivation layer 160 over the isolation structure, the second opening 170 exposing the top surface of the conductive layer 110. The second opening 170 is used to provide a space for forming the metal layer, and the second opening 170 exposes the conductive layer 110 so that the metal layer can contact the conductive layer 110.
In this embodiment, the second opening 170 exposes a portion of the top surface of the conductive layer 110, or the second opening 170 exposes all of the top surface of the conductive layer 110.
In the present embodiment, the process of forming the second opening 170 includes a dry etching process. The dry etching process has high process controllability, which is beneficial to improving the profile control of the second opening 170 and reducing the probability of damaging the conductive layer 110.
In this embodiment, the forming method further includes: after forming the passivation layer 160, before forming the metal layer 210 located in the second opening 170 and contacting the conductive layer 110, and the second pad layer 220 located on the passivation layer 160 of the first surface 101 and connected to the metal layer 210, a ground trench 180 penetrating a portion of the width passivation layer 160 on the pixel substrate 100 is formed, the ground trench 180 exposing the pixel substrate 100.
The ground trenches 180 are used to provide a spatial location for forming a ground line.
In this embodiment, during the formation of the ground trench 180, an over-etching process is also performed, and thus, the ground trench 180 also penetrates through a part of the thickness of the pixel substrate 100. In other embodiments, the ground trench may also extend through only the passivation layer.
In the present embodiment, the second opening 170 is formed after the ground trench 180 is formed as an example. In other embodiments, the ground trench may also be formed after the second opening is formed, or the second opening and the ground trench may be formed in the same step.
As shown in fig. 15 to 16, a metal layer 210 positioned in the second opening 170 and in contact with the conductive layer 110, and a second pad layer 220 positioned on the passivation layer 160 of the first surface 101 and connected to the metal layer 210 are formed. Wherein the forming method further comprises: a ground line 230 is formed within the ground trench 180, the ground line 230 being spaced apart from the metal layer 210 and the second pad layer 220.
Specifically, as shown in fig. 15, a metal material layer 190 is formed on the passivation layer 160, the metal material layer 190 filling the second opening 170 and the ground trench 180; as shown in fig. 16, the metal material layer 190 is patterned, the metal material layer 190 located in the second opening 170 and in contact with the conductive layer 110 is reserved as a metal layer 210, a portion of the metal material layer 190 on the passivation layer 160 above the pixel substrate 100 adjacent to the isolation structure is reserved as a second pad layer 220, the second pad layer 220 is electrically connected to the metal layer 210, and the metal material layer 190 located in the ground trench 180 is reserved as a ground line 230.
In this embodiment, a physical vapor deposition (Physical Vapor Deposition, PVD) process is used to form the metal material layer 190.
The first surface 101 of the pixel substrate 100 is an insulating surface formed by the passivation layer 160, and before the metal material layer 190 is formed, the conductive layer 110 is electrically isolated from the pixel substrate 100, so that a large amount of charges are easily accumulated on the first surface 101 during the process of forming the metal material layer 190 by using a physical vapor deposition process, and the metal material layer 190 is further formed in the grounding trench 180 and contacts the pixel substrate 100, so that charges are released through the pixel substrate 100, so as to avoid arcing problems caused by charge accumulation on the first surface 101.
In this embodiment, an etching process is used to pattern the metal material layer 190. Specifically, the metal material layer 190 is patterned using an anisotropic dry etching process.
Referring to fig. 17 and fig. 18, fig. 17 is a cross-sectional view, fig. 18 is a top view corresponding to fig. 17, and in this embodiment, the forming method further includes: after forming the metal layer 210, an interconnect trench 240 is formed through the passivation layer 160 over the first pad layer 150, exposing the first pad layer 150.
The interconnect trench 240 is formed to expose the first pad layer 150 so that electrical connection between the first pad layer 150 and an external circuit can be subsequently achieved. For example: and the subsequent packaging and testing processes are facilitated.
In this embodiment, before forming the interconnection trench 240, the method for forming a photoelectric sensor further includes: a protective layer 250 is formed on top and sidewalls of the metal layer 210 and the second pad layer 220. The protective layer 250 is also formed on the top surface and sidewalls of the ground line 230.
The protection layer 250 is used for protecting the metal layer 210, the second pad layer 220, and the ground line 230. In this embodiment, the material of the protection layer 250 is silicon oxide. In other embodiments, the material of the protective layer may also be silicon nitride or silicon oxynitride.
In addition, during the formation of the interconnection trench 240, the protective layer 250 on the top surface of the second pad layer 220 is also removed so as to expose the second pad layer 220, thereby enabling subsequent electrical connection between the second pad layer 220 and an external circuit, such that the second pad layer 220 can be connected to a negative potential.
Correspondingly, the embodiment of the invention also provides electronic equipment comprising the photoelectric sensor provided by the embodiment of the invention.
The electronic device of the embodiment may be any electronic product or device having a photoelectric sensing function, such as a mobile phone, a tablet computer, a notebook computer, a navigator, a camera, a video camera, a sweeping robot, a virtual reality device, an augmented reality device, or any intermediate product including the aforementioned photoelectric sensor.
As can be seen from the foregoing description, the photoelectric sensor provided in the embodiment of the present invention has excellent performance, and by using the photoelectric sensor provided in the embodiment of the present invention, the performance of the electronic device is improved, and the use sensitivity of the user is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (22)
1. A photoelectric sensor, comprising:
the pixel substrate comprises a first surface and a second surface which are opposite to each other, the pixel substrate comprises a photosensitive area and a lead area surrounding the photosensitive area, and the photosensitive area comprises pixel unit areas which are arranged in an array;
the isolation structure is positioned in the pixel substrate between the pixel unit areas and comprises a conductive layer, the top surface of the conductive layer is exposed out of the first surface, and the isolation structure is positioned in the photosensitive area;
a dielectric layer on the second surface of the pixel substrate, the dielectric layer being on a logic substrate;
the interconnection layer is positioned in the dielectric layer of the lead area;
A first opening penetrating through the pixel substrate of the lead region and the dielectric layer above the interconnect layer, the first opening exposing a portion of the top of the interconnect layer toward the first surface;
a first pad layer located at the bottom of the first opening and in contact with the interconnection layer;
a passivation layer filling the first opening and located on the first surface, the passivation layer covering the first pad layer and the conductive layer;
the second opening is positioned in the passivation layer and exposes the first surface of the pixel substrate and the top surface of the isolation structure, and the second opening is in a grid shape;
a metal layer filling the second openings in a grid shape and contacting with the conductive layer;
and the second welding pad layer is positioned on the passivation layer of the first surface and connected with the metal layer, and the second welding pad layer is positioned between the isolation structure and the first welding pad layer.
2. The photosensor of claim 1 wherein the second pad layer is for accessing a negative potential.
3. The photosensor according to claim 1, wherein the photosensor further comprises: and the grounding wire penetrates through the passivation layer with partial width and is contacted with the pixel substrate.
4. The photosensor of claim 3 wherein the top surface of the ground line is flush with the top surfaces of the metal layer and the second pad layer.
5. The photosensor of claim 1 wherein the metal layer and the second pad layer are of unitary construction.
6. The photosensor of claim 1, wherein the metal layer is in contact with a portion of the top surface of the conductive layer or the metal layer is in contact with the top surface of all of the conductive layer.
7. The photosensor according to claim 1, wherein the photosensor further comprises: and the logic substrate is bonded on the dielectric layer of the second surface of the pixel substrate.
8. The photosensor of claim 1 or 7, wherein the first surface is a back surface of the pixel substrate and the second surface is a front surface of the pixel substrate.
9. The photosensor of claim 1, wherein the isolation structure further comprises: and the insulating layer is positioned between the conductive layer and the pixel substrate.
10. The photosensor of claim 9, wherein the material of the conductive layer includes one or more of tungsten, aluminum, titanium nitride, tantalum nitride, copper; the material of the insulating layer comprises any one or more of silicon nitride, silicon oxide, aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, lanthanum oxide and barium oxide.
11. The photosensor of claim 1, wherein the material of the pixel substrate includes one or more of silicon, germanium, silicon carbide, gallium arsenide, and indium gallium arsenide; the material of the interconnection layer comprises one or more of copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride and tantalum nitride; the material of the first welding pad layer comprises one or more of aluminum, titanium, gold and tin-doped indium oxide; the material of the passivation layer comprises one or more of silicon oxide, silicon oxynitride and silicon nitride; the material of the metal layer comprises one or two of aluminum and tungsten; the material of the second welding pad layer comprises one or more of aluminum, titanium, gold and tin-doped indium oxide.
12. A method of forming a photoelectric sensor, comprising:
providing a pixel substrate, wherein the pixel substrate comprises a first surface and a second surface which are opposite to each other, the pixel substrate comprises a photosensitive area and a lead area surrounding the photosensitive area, the photosensitive area comprises pixel unit areas which are arranged in an array, an isolation structure is formed in the pixel substrate between the pixel unit areas, the isolation structure comprises a conductive layer, and the top surface of the conductive layer is exposed out of the first surface; a dielectric layer is formed on the second surface, and an interconnection layer is formed in the dielectric layer of the lead area;
Forming a first opening penetrating through the pixel substrate of the lead area and the dielectric layer above the interconnection layer, wherein the first opening exposes a part of the top of the interconnection layer, which faces the first surface;
forming a first pad layer in contact with the interconnection layer at the bottom of the first opening;
forming a passivation layer filling the first opening and located on the first surface, wherein the passivation layer covers the first pad layer and the conductive layer;
the metal layer penetrates through the passivation layer above the isolation structure and is in contact with the conductive layer, and the second welding pad layer is located on the passivation layer on the first surface and connected with the metal layer, and the metal layer is in a grid shape.
13. The method of claim 12, wherein the second pad layer is configured to be connected to a negative potential.
14. The method of forming a photosensor of claim 12, where the step of forming the metal layer and the second pad layer includes: forming a second opening penetrating through the passivation layer above the isolation structure, wherein the second opening exposes the top surface of the conductive layer; and forming a metal layer positioned in the second opening and contacted with the conductive layer, and a second welding pad layer positioned on the passivation layer of the first surface and connected with the metal layer.
15. The method of forming a photosensor of claim 14 where the step of forming a metal layer and the second pad layer includes: forming a metal material layer on the passivation layer, wherein the metal material layer fills the second opening; and patterning the metal material layer, reserving the metal material layer which is positioned in the second opening and is in contact with the conductive layer for being used as the metal layer, reserving a part of the metal material layer on the passivation layer above the pixel substrate adjacent to the isolation structure for being used as the second welding pad layer, and electrically connecting the second welding pad layer with the metal layer.
16. The method of forming a photosensor of claim 14, where the process of forming the second opening includes a dry etching process.
17. The method of claim 13, wherein the metal layer is in contact with a portion of the top surface of the conductive layer or the metal layer is in contact with all of the top surface of the conductive layer.
18. The method of forming a photosensor of claim 13, further comprising: after the metal layer is formed, an interconnection trench is formed through the passivation layer over the first pad layer, exposing the first pad layer.
19. The method of claim 13, wherein in the step of providing a pixel substrate, a logic substrate is further bonded to the dielectric layer on the second surface of the pixel substrate.
20. The method of claim 13 or 19, wherein the first surface is a back surface of a pixel substrate and the second surface is a front surface of the pixel substrate.
21. The method of forming a photosensor of claim 12, further comprising: in the step of forming the metal layer, a ground line penetrating through a part of the width passivation layer on the pixel substrate is also formed, the ground line being in contact with the pixel substrate.
22. An electronic device, comprising: the photosensor according to any one of claims 1 to 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111583437.9A CN116344561A (en) | 2021-12-22 | 2021-12-22 | Photoelectric sensor, forming method thereof and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111583437.9A CN116344561A (en) | 2021-12-22 | 2021-12-22 | Photoelectric sensor, forming method thereof and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116344561A true CN116344561A (en) | 2023-06-27 |
Family
ID=86891673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111583437.9A Pending CN116344561A (en) | 2021-12-22 | 2021-12-22 | Photoelectric sensor, forming method thereof and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116344561A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116682837A (en) * | 2023-08-02 | 2023-09-01 | 武汉楚兴技术有限公司 | Semiconductor structure and preparation method thereof |
-
2021
- 2021-12-22 CN CN202111583437.9A patent/CN116344561A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116682837A (en) * | 2023-08-02 | 2023-09-01 | 武汉楚兴技术有限公司 | Semiconductor structure and preparation method thereof |
| CN116682837B (en) * | 2023-08-02 | 2023-10-24 | 武汉楚兴技术有限公司 | Semiconductor structure and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102192867B1 (en) | Back-side deep trench isolation (bdti) structure for pinned photodiode image sensor | |
| KR102034482B1 (en) | Image sensor and method of forming the same | |
| CN105720067B9 (en) | Solid-state image pickup apparatus | |
| US7800192B2 (en) | Backside illuminated image sensor having deep light reflective trenches | |
| CN110600490B (en) | Backside illuminated global shutter pixel | |
| US9559135B2 (en) | Conduction layer for stacked CIS charging prevention | |
| CN108511476B (en) | Backside illuminated image sensor and forming method thereof | |
| KR20130099425A (en) | Image sensor | |
| CN116344561A (en) | Photoelectric sensor, forming method thereof and electronic equipment | |
| EP3817053A1 (en) | Image sensor and method of manufacturing same | |
| CN111029357B (en) | Semiconductor structure and preparation method thereof | |
| CN112490259A (en) | Pixel unit structure and manufacturing method | |
| CN116344560A (en) | Photoelectric sensor, forming method thereof and electronic equipment | |
| CN116344559A (en) | Photoelectric sensor, forming method thereof and electronic equipment | |
| KR20200038147A (en) | Image sensor | |
| US10304889B2 (en) | Image sensor device and manufacturing method thereof | |
| CN115377130A (en) | Image sensor, manufacturing method thereof and electronic device | |
| CN213519955U (en) | Backside illuminated image sensor chip | |
| CN117080228A (en) | Method for forming photoelectric sensor | |
| CN113644084B (en) | Semiconductor device and method for manufacturing the same | |
| WO2023019547A1 (en) | Photoelectric sensor, method for forming same, and electronic device | |
| CN116978972A (en) | Photoelectric sensor and forming method thereof | |
| KR102109952B1 (en) | Image sensor and method of forming the same | |
| US7952124B2 (en) | Image sensor and a method for manufacturing the same | |
| CN113809103A (en) | Backside illuminated image sensor chip and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |