CN213519955U - Backside illuminated image sensor chip - Google Patents

Abstract

The utility model provides an image sensor chip, include: a semiconductor substrate having a front side and a back side; the metal interconnection structure is positioned on the front surface of the semiconductor substrate; and the step-shaped through hole or the step-shaped groove is positioned on the back surface of the semiconductor substrate, and a conductive layer is filled in the step-shaped through hole or the step-shaped groove to form a back surface routing. The utility model discloses reduced semiconductor substrate back difference in height, reduced the influence to the color filter and the microlens appearance at pixel array edge in the follow-up technology, improved the technology reliability, reduced the color cast risk, the step form through-hole or the dielectric layer thickness of step form slot lateral wall are controllable, can reduce the electric leakage risk, owing to need not consider walk the line, the influence of pad thickness to the difference in height, can bring better device electrical property through increasing the thickness reduction resistance of walking the line, pad. Because the utility model discloses a step form through-hole or step form slot's appearance and width are easily controlled, can not cause too much chip area extravagant.

Description

Backside illuminated image sensor chip

Technical Field

The utility model relates to a back of body illumination formula image sensor chip.

Background

The CMOS image sensor is used as a device unit for converting an optical signal into a digital electrical signal, and is widely applied to various emerging fields such as smart phones, tablet computers, automobiles, medical treatment and the like. A typical image sensor converts incident photons into electrons or holes through a pixel array, and when an integration period is completed, the collected charges are converted into digital signals through an analog circuit and a digital circuit, and are transmitted to an output terminal of the sensor.

The conventional image sensor adopts front-illuminated incidence, that is, incident photons are required to reach the photodiode and be smoothly absorbed by the photodiode, and need to pass through a light path channel and/or a metal interconnection layer formed by a plurality of dielectric layers, and meanwhile, part of incident photons are reflected by the interface of the metal interconnection layer and then rebound to the air and even crosstalk to other pixel units, so that the sensitivity of the image sensor is reduced and/or the color of the image sensor is distorted.

With the continuous development of image sensor technology, the size of a pixel unit is reduced from 1.75 μm to 1.12 μm or even lower, the optical path of a medium layer through which photons need to pass is reduced synchronously, and the performances such as sensitivity and dark light performance are seriously deteriorated. At this time, the back-illuminated image sensor can fundamentally solve the above-mentioned problems due to its unique structure. In the back-illuminated image sensor, incident photons are incident from the back of the image sensor, so that on one hand, energy loss when the photons pass through a dielectric layer and/or a metal interconnection layer is avoided, on the other hand, the area ratio of a photodiode to the metal interconnection layer is not required to be balanced, the device design is facilitated, and the sensitivity, the dark light performance and other performances of the image sensor can be obviously improved.

For back side illuminated image sensor technology, the prior art focuses mainly on the active pixel area, the metal shielding area, the pad area and the routing area. For the active pixel region, a great deal of research is focused on structures such as metal grids or composite material grids, and the optical crosstalk between pixels can be reduced; the metal mask region is formed by photolithography to form a metal layer over part of the pixel region, and mainly functions to collect non-optical signals such as dark current, heat generation signals, and the like in the absence of light, and corrects the output signal of the image sensor by subtracting the non-optical signals. Pads and traces for bonding or testing also need to be formed on the backside of the semiconductor substrate. Wherein the pad region has a conductive layer thickness between about 3K a and about 15K a in order to ensure good conductivity, and the routing region is typically disposed at a periphery of the pixel array region for transmitting power, ground or data signals.

In the prior art, the bonding pad and the routing wire are generally located on a dielectric layer on the back surface of a semiconductor substrate, and have large thickness, and have obvious height difference with other areas (an active pixel area and a metal shielding area), which is easy to cause changes in the shapes of a color filter and a micro lens at the edge of a pixel array in the spin coating process of a subsequent color filter layer and a micro lens layer, thereby causing abnormal pixel response at the edge of the pixel array, further causing image color cast and other problems.

Based on the structure, the height difference between the pad area and the wiring area and between the active pixel area and the metal shielding area can be reduced by reducing the thickness of the dielectric layer, however, reducing the thickness of the dielectric layer may cause the thickness of the dielectric layer coated by the side wall of the through hole or the trench for connecting the back wiring, the pad and the front metal interconnection structure to be insufficient, and cause the risks of electric leakage between the back wiring, the pad and the semiconductor substrate and the like. On the other hand, besides the thickness of the dielectric layer, the routing and bonding pads also have certain thickness, and the height difference caused by the thickness of the routing and bonding pads cannot be completely avoided, so that the formation of the color filter and the micro-lens at the later stage is not facilitated.

In addition, for the above-mentioned problem of the pad region, at present, another solution is to completely etch the semiconductor substrate material of the pad region, stop on the STI layer (shallow trench isolation layer), then form an opening through the STI layer and the ILD layer (interlayer dielectric layer) by patterning and performing an etching process, reach the metal interconnection structure, form a pad in the opening, and fill up the etched portion in a subsequent process. The technical scheme is complex in process, and meanwhile, the semiconductor substrate material is completely etched, so that the semiconductor substrate material in the region cannot be utilized to form a device structure, and the waste of the chip area is caused. The same problem can also occur if this solution is applied to the routing area.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a back of body illumination formula image sensor chip reduces semiconductor substrate back difference in height, improves the process reliability, reduces the color cast risk, guarantees device electrical property, and simple process is easy, saves the chip area.

Based on the above consideration, the utility model provides a back of body illumination formula image sensor chip, include: a semiconductor substrate having a front side and a back side; the metal interconnection structure is positioned on the front surface of the semiconductor substrate; and the step-shaped through hole or the step-shaped groove is positioned on the back surface of the semiconductor substrate, and a conductive layer is filled in the step-shaped through hole or the step-shaped groove to form a back surface routing.

Preferably, the wiring on the back side is electrically connected with the metal interconnection structure on the front side.

Preferably, the back-illuminated image sensor chip further includes: and a pad structure of the image sensor chip formed by the conductive layer in the step-shaped through hole or the step-shaped groove.

Preferably, the stepped through hole or the stepped trench includes a first opening and a second opening located in the first opening, and a bottom of the second opening is lower than a bottom of the first opening.

Preferably, a dielectric layer covers the conductive layer, the bottom of the first opening, the side wall of the first opening and the side wall of the second opening.

Preferably, the difference of the surface height of the wiring area and/or the pad area on the back surface of the semiconductor substrate and the other area is less than 0.5 μm.

Preferably, the other area on the back surface of the semiconductor substrate comprises an active pixel area and a metal shielding area.

Preferably, the depth of the first opening does not penetrate through the semiconductor substrate.

Preferably, the conductive layer in the step-shaped through hole or the step-shaped trench includes a first conductive layer and a second conductive layer located on the first conductive layer.

Preferably, the back-illuminated image sensor chip further includes a deep trench isolation structure located in the active pixel region and the metal shielding region on the back surface of the semiconductor substrate.

Preferably, the semiconductor substrate further includes a deep P-type doped well surrounding the stepped through hole or the stepped trench, and a deep N-type doped well surrounding the deep P-type doped well.

Preferably, the conductive layer in the first opening connects the metal interconnection structures of the front surfaces to each other.

Preferably, the conductive layer in the second opening connects the metal interconnection structures of the front surfaces to each other.

Preferably, the back-illuminated image sensor chip further includes: and the step-shaped through hole or the step-shaped groove is positioned around the metal shielding area on the back surface of the semiconductor substrate, and a conductive layer is filled in the step-shaped through hole or the step-shaped groove.

Preferably, the back-illuminated image sensor chip further includes: and the step-shaped through hole or the step-shaped groove is positioned around the analog circuit area on the back surface of the semiconductor substrate, and a conductive layer is filled in the step-shaped through hole or the step-shaped groove.

The utility model discloses a back of body illumination formula image sensor chip forms step form through-hole or step form slot at the semiconductor substrate back fill the conducting layer in step form through-hole or the step form slot and in order to form walking the line at the back or form the pad simultaneously, semiconductor substrate back difference in height has been reduced, the influence to the color filter and the microlens appearance at pixel array edge in the follow-up technology has been reduced, the process reliability has been improved, the color cast risk has been reduced, the dielectric layer thickness of step form through-hole or step form slot lateral wall is controllable, can reduce the electric leakage risk, owing to need not consider walking the line, the influence of pad thickness to difference in height, can walk the line through the increase, the thickness of pad reduces resistance, bring better device electrical property. In addition, the back routing formed by the utility model can be used for communicating the metal interconnection structures on the front side, so that the driving capability of signals can be effectively improved, and the voltage drop in transmission can be reduced; also can utilize this back to walk the physical isolation that line formed specific area, and owing to adopt the utility model discloses the step form through-hole that the method formed or the appearance and the width of step form slot are easily controlled, can not cause too much chip area extravagant.

Drawings

Other features, objects and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments thereof, which proceeds with reference to the accompanying drawings.

Fig. 1-8 are process schematic diagrams of a method of manufacturing a backside illuminated image sensor chip according to the present invention;

fig. 9 is a partial top view of a back-illuminated image sensor chip according to an embodiment of the present invention;

FIG. 10 is a cross-sectional view taken along line B1-B1 of FIG. 9;

fig. 11 is a partial top view of a back-illuminated image sensor chip according to another embodiment of the present invention;

FIG. 12 is a cross-sectional view taken along line B2-B2 of FIG. 11;

fig. 13 is a partial cross-sectional view of a back-illuminated image sensor chip according to yet another embodiment of the present invention;

fig. 14 is a partial cross-sectional view of a back-illuminated image sensor chip according to yet another embodiment of the invention.

In the drawings, like or similar reference numbers indicate like or similar devices (modules) or steps throughout the different views.

Detailed Description

For solving the problem among the above-mentioned prior art, the utility model provides a back illuminated image sensor chip forms step form through-hole or step form slot at the semiconductor substrate back fill the conducting layer in step form through-hole or the step form slot in order to form the line of walking at the back, semiconductor substrate back difference in height has been reduced, the influence to the color filter and the micro lens appearance at pixel array edge in the follow-up technology has been reduced, the process reliability has been improved, the color cast risk has been reduced, the dielectric layer thickness of step form through-hole or step form slot lateral wall is controllable, can reduce the electric leakage risk, owing to need not consider walking the influence of line thickness itself to difference in height, can reduce resistance through the thickness that increases the line of walking, bring better device electrical property.

In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof. The accompanying drawings illustrate, by way of example, specific embodiments in which the invention may be practiced. The illustrated embodiments are not intended to be exhaustive of all embodiments according to the invention. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

The present invention will be described in detail with reference to the following embodiments.

Referring to fig. 1, a semiconductor substrate 100 is provided, the semiconductor substrate 100 has a front surface 101 and a back surface 102, and a routing area 100B, a pad area 100A and other areas 100C in the semiconductor substrate 100 are distinguished by dotted lines, wherein the other areas 100C may include an active pixel area and a metal shielding area. Those skilled in the art will appreciate that the specific arrangement of the location, size, etc. of the various regions can be selected as desired, and is shown by way of example and not limitation.

On the semiconductor substrate 100, a metal interconnection structure 103 is formed by completing a front process of the image sensor, the metal interconnection structure 103 is located in the first dielectric layer 104, only the metal interconnection structure 103 in the routing area 100B and the pad area 100A is shown here, and details of the other area 100C are not shown.

Subsequently, the back surface 102 of the semiconductor substrate 100 is thinned by bonding to another wafer or substrate (not shown) for support from the front surface 101 side of the semiconductor substrate 100 to reduce the optical path length of the active pixel region. Preferably, deep trench isolation structures (not shown) may be formed in the active pixel region and the metal shielding region of the backside 102 of the semiconductor substrate 100 to reduce electrical crosstalk between pixel cells of the active pixel region and the metal shielding region.

Preferably, one or more high dielectric constant films (not shown), such as hafnium oxide, aluminum oxide, or tantalum oxide, are deposited on the thinned back surface 102 of the semiconductor substrate 100, with a total thickness of about 40-1000 a, for passivating the back surface 102 of the semiconductor substrate 100, and a second dielectric layer (not shown) is deposited on the high dielectric constant films to prevent subsequent etching from damaging the passivation layer.

Subsequently, one preferred embodiment of forming a stepped through-hole or stepped trench 120, 121 in the back surface 102 of the semiconductor substrate 100 to expose a portion of the metal interconnect structure 103 formed by the front side process is illustrated by fig. 2-7.

Specifically, as shown in fig. 2, a first opening 120 with a depth of about 7000-. A third dielectric layer (not shown) and an etch stop layer (not shown) are sequentially deposited on the back surface 102 of the semiconductor substrate 100, wherein the third dielectric layer mainly serves to relieve stress on the semiconductor substrate 100 caused by the deposition of the etch stop layer in the subsequent steps, and the etch stop layer may be silicon nitride.

As shown in fig. 3, a fourth dielectric layer 117 is deposited over the etch stop layer to a thickness of about 2000 a-.

As shown in fig. 4, etching is continued in the first opening 120 to form a second opening 121, and the bottom of the second opening 121 is lower than the bottom of the first opening 120. The first opening 120 is formed by etching, and the thickness of the semiconductor substrate 100 in the area is reduced, so that the appearance and the width of the second opening 121 formed by etching again can be better controlled, and excessive area waste is avoided.

Preferably, a certain thickness of the first dielectric layer 104 still remains above the metal interconnection structure 103 at this time, so as to prevent the metal interconnection structure 103 exposed during the subsequent etching from contaminating the semiconductor substrate 100.

As shown in fig. 5, the semiconductor substrate 100 at the sidewall of the second opening 121 is selectively etched, so that the sidewall of the second opening 121 extends toward the inside of the semiconductor substrate 100 relative to other surrounding dielectric layers (e.g., the first dielectric layer 104 and the fourth dielectric layer 117), which is beneficial to controlling the thickness of the dielectric layer at the sidewall of the second opening 121 and avoiding the dielectric layer at the corner above the second opening 121 from being too thin in the subsequent steps, thereby reducing the risk of leakage.

As shown in fig. 6, a fifth dielectric layer is deposited on the back surface 102 of the semiconductor substrate 100, and since the fifth dielectric layer is similar to the fourth dielectric layer 117 and the first dielectric layer 104 thereunder and has the same function, in fig. 6, the fifth dielectric layer is combined with the previous fourth dielectric layer 117 and the previous first dielectric layer 104 to be labeled as a dielectric layer 118.

As shown in fig. 7, the etching of the dielectric layer 118 at the bottom of the second opening 121 is continued, and the etching process may be performed without using a mask until the metal interconnection structure 103 on the front surface is exposed.

To this end, step-shaped through holes or step-shaped trenches 120, 121 of the routing area 100B and the pad area 100A are formed, the step-shaped through holes or step-shaped trenches include the first opening 120 and the second opening 121 located in the first opening 120, the bottom of the second opening 121 is lower than the bottom of the first opening 120, the front metal interconnection structure 103 is exposed at the bottom of the second opening 121, and the dielectric layer 118 with sufficient thickness is covered on the bottom and the sidewall of the first opening 120 and the sidewall of the second opening 121, so as to perform the function of insulation protection and reduce the risk of leakage.

In addition to the methods shown in the above embodiments, in other embodiments not shown, a step-shaped via or a step-shaped trench having a similar structure may be formed by forming the second opening 121 first and then forming the first opening 120 around the second opening 121, wherein the bottom of the second opening 121 is lower than the bottom of the first opening 120.

As shown in fig. 8, the conductive layers 133 and 134 are filled in the step-shaped via holes or step-shaped trenches 120 and 121 to form back traces and pads electrically connected to the front metal interconnection structure 103. In the present embodiment, the two conductive layers 133 and 134 are filled in the step-shaped through holes or the step-shaped trenches 120 and 121, but in other embodiments not shown, only one conductive layer may be filled in the step-shaped through holes or the step-shaped trenches 120 and 121, and the conductive layers outside the step-shaped through holes or the step-shaped trenches 120 and 121 may be separately disposed through another step.

Specifically, the first conductive layer 133 and the second conductive layer 134 may be formed in this order on the rear surface 102 of the semiconductor substrate 100. Wherein first conductive layer 133 may sequentially include a first barrier/adhesion layer, a metal layer, and a second barrier/adhesion layer (not shown), which may include at least one of titanium, titanium nitride, tantalum, and tantalum nitride, having a thickness of about 400 a and 700 a, the metal layer may be tungsten, copper, nickel, or a remaining metal material having sufficient etch selectivity to second conductive layer 134, having a thickness of about 1000 a and 3500 a. The second conductive layer 134 may be composed of aluminum or other metal materials, or may be a combination material of at least one of titanium, titanium nitride, tantalum, and tantalum nitride and aluminum, and the thickness of the second conductive layer 134 is ensured to increase the stability of the electrical conduction, preferably in a range of about 6000-.

Then, a patterning step is performed to remove the second conductive layer 134 outside the step-shaped via or the step-shaped trench 120, 121 by using the first conductive layer 133 as an etching stop layer, and only the second conductive layer 134 in the step-shaped via or the step-shaped trench 120, 121 is remained (as shown in fig. 8). With the dielectric layer 118 as an etching stop layer, a patterning step is performed on the first conductive layer 133 to remove the first conductive layer 133 (not shown in fig. 8) between the routing region 100B and the pad region 100A and between the routing region 100B and the other region 100C. Thus, the first conductive layer 133 and the second conductive layer 134 in the step-shaped via holes or the step-shaped trenches 120, 121 form a back trace or pad electrically connected to the metal interconnection structure 103 on the front side.

Through the utility model discloses the back of formation is walked the line and can be used for communicating positive metal interconnect structure each other, can effectively improve the driving force of signal, reduces the voltage drop in the transmission. Fig. 9-12 show specific implementations in which the back traces in the trace area 100B connect the front metal interconnect structures 103 to each other. In a preferred embodiment shown in fig. 9 and 10, the front metal interconnection structures 103 can be connected to each other only through the conductive layers 133 and 134 in the first opening 120; in another preferred embodiment shown in fig. 11 and 12, the metal interconnection structures 103 on the front side can be connected to each other through the conductive layers 133 and 134 in the first opening 120 and the conductive layers 133 and 134 in the second opening, so as to further reduce the resistance of the current path and improve the electrical performance.

In addition, also can utilize the back to walk the physical isolation that line formed specific area, and owing to adopt the utility model discloses step form through-hole or step form slot's that the method formed appearance and width are easily controlled, can not cause too much chip area extravagant. In addition, other structures on the back side can be formed by conventional process steps, such as forming a composite grid, color filters and micro-lenses in the active pixel regions of the other regions 100C, and forming a shielding metal in the metal shielding region.

Therefore, the heights of the routing area 100B and the pad area 100A can be controlled by adjusting the thickness of the dielectric layer 118, the thicknesses of the conductive layers 133 and 134, and the depth of the first opening 120, so that the height difference between the surfaces of the routing area 100B, the pad area 100A, and the other area 100C on the back surface of the semiconductor substrate is maintained at a low level, for example, less than 0.5 μm, which is beneficial to the formation of a subsequent color filter and a microlens, improves the process reliability, and reduces the color cast risk. Because the influence of the thickness of the routing and the bonding pad on the height difference is not considered, the resistance can be reduced by increasing the thickness of the routing and the bonding pad, and better electrical performance of the device is brought.

It can be understood by those skilled in the art that, in order to achieve the purpose of reducing the height difference of the back surface of the semiconductor substrate, improving the process reliability, and reducing the color cast risk, the method of the present invention is adopted at least in the back wiring area 100B to form the back wiring, and in the above embodiments, while the step-shaped through hole or the step-shaped groove is filled with the conductive layer to form the back wiring, the technical solution of forming the pad structure of the image sensor chip is merely a preferred embodiment of the present invention, and is not limited thereto.

Preferably, the method for manufacturing a backside illuminated image sensor chip of the present invention further includes forming a deep P-type doped well surrounding the step-shaped via or the step-shaped trench 120, 121 and a deep N-type doped well surrounding the deep P-type doped well in the semiconductor substrate 100 by ion implantation, and connecting the deep P-type doped well to a ground signal and the deep N-type doped well to a high voltage, so as to reduce a risk of leakage caused by a defect generated by etching the semiconductor substrate 100.

As shown in fig. 13, according to another preferred embodiment of the present invention, step-shaped through holes or step-shaped trenches 120, 121 may be further formed around the metal shielding region 200 on the back surface of the semiconductor substrate 100, and the conductive layer 135 is filled in the step-shaped through holes or step-shaped trenches 120, 121 (the conductive layer 135 may or may not be connected to the metal interconnection structure 103 on the front surface), so as to reduce the influence of stress in the conductive layer 135 and achieve better light shielding effect and electrical isolation for the metal shielding region 200.

As shown in fig. 14, according to another preferred embodiment of the present invention, step-shaped through holes or step-shaped trenches 120, 121 may be further formed around the analog circuit area 300 on the back surface of the semiconductor substrate 100, and the conductive layers 135 are filled in the step-shaped through holes or step-shaped trenches 120, 121 (the conductive layers 135 may or may not be connected to the metal interconnection structures 103 on the front surface), so as to form a better light shielding effect on the analog circuit area 300 and reduce the interference of noise caused by light to signals.

Another aspect of the present invention also provides a backside illuminated image sensor chip, a preferred embodiment of which is shown in fig. 8, and which includes: a semiconductor substrate 100 having a front surface 101 and a back surface 102; a metal interconnection structure 103 located on the front surface 101 of the semiconductor substrate 100; step-shaped through holes or step-shaped grooves 120 and 121 positioned on the back surface 102 of the semiconductor substrate 100, wherein the step-shaped through holes or step-shaped grooves 120 and 121 are filled with conductive layers 133 and 134 to form back-surface traces; the traces on the back side 102 are electrically connected to the metal interconnection structure 103 on the front side 101.

Preferably, the back-illuminated image sensor chip further includes: a pad structure of the image sensor chip formed by the conductive layers 133, 134 in the stepped through-holes or the stepped trenches 120, 121.

Wherein the step-shaped through hole or the step-shaped groove comprises a first opening 120 and a second opening 121 positioned in the first opening 120, and the bottom of the second opening 121 is lower than the bottom of the first opening 120. Preferably, the depth of the first opening 120 does not penetrate the semiconductor substrate 100. Dielectric layer 118 covers the conductive layers 133 and 134 and the bottom of the first opening 120, the sidewall of the first opening 120, and the sidewall of the second opening 121.

Preferably, the difference between the surface height of the routing area 100B and the surface height of the other area 100C on the back surface 102 of the semiconductor substrate 100 is less than 0.5 μm. The other region 100C includes an active pixel region and a metal shielding region. Further preferably, deep trench isolation structures are disposed in the active pixel region and the metal shielding region.

Preferably, the semiconductor substrate further includes a deep P-type doped well surrounding the step-shaped via or the step-shaped trench 120, 121, and a deep N-type doped well surrounding the deep P-type doped well, and the deep N-type doped well is connected to a high voltage by connecting a signal to ground the deep P-type doped well, so that a leakage risk caused by a defect generated by etching the semiconductor substrate 100 can be reduced.

In a preferred embodiment, the front metal interconnect structures 103 may be connected to each other only through the conductive layers 133, 134 in the first opening 120; in another preferred embodiment, the metal interconnection structures 103 on the front side can be connected to each other through the conductive layers 133 and 134 in the first opening 120 and the conductive layers 133 and 134 in the second opening 121, so that the resistance of the current path is further reduced, and the electrical performance is improved.

In yet another preferred embodiment as shown in fig. 13, the back-illuminated image sensor chip further includes: the step-shaped through holes or the step-shaped trenches 120 and 121 are located around the metal shielding region 200 on the back surface of the semiconductor substrate 100, and the conductive layers 135 (the conductive layers 135 may or may not be connected to the metal interconnection structures 103 on the front surface) are filled in the step-shaped through holes or the step-shaped trenches 120 and 121, so as to reduce the influence of stress in the conductive layers 135, and achieve better light shielding effect and electrical isolation for the metal shielding region 200.

In yet another preferred embodiment as shown in fig. 14, the back-illuminated image sensor chip further includes: the step-shaped through holes or the step-shaped trenches 120 and 121 are located around the analog circuit area 300 on the back surface of the semiconductor substrate 100, and the conductive layers 135 are filled in the step-shaped through holes or the step-shaped trenches 120 and 121 (the conductive layers 135 and the metal interconnection structures 103 on the front surface may be connected or not connected), so that a better light shielding effect is formed on the analog circuit area 300, and interference of noise caused by light rays on signals is reduced.

To sum up, the utility model discloses a back side illumination formula image sensor chip forms step form through-hole or step form slot at the semiconductor substrate back fill the conducting layer in step form through-hole or the step form slot and walk the line or form the pad simultaneously at the back in order to form the back, semiconductor substrate back difference in height has been reduced, the influence to the color filter and the microlens appearance at pixel array edge in the follow-up technology has been reduced, the process reliability has been improved, the color cast risk has been reduced, the dielectric layer thickness of step form through-hole or step form slot lateral wall is controllable, can reduce the electric leakage risk, owing to need not consider walking the line, the influence of pad thickness to difference in height, can walk the line through increasing, the thickness of pad reduces resistance, bring better device electrical property. In addition, the back routing formed by the utility model can be used for communicating the metal interconnection structures on the front side, so that the driving capability of signals can be effectively improved, and the voltage drop in transmission can be reduced; also can utilize this back to walk the physical isolation that line formed specific area, and owing to adopt the utility model discloses the step form through-hole that the method formed or the appearance and the width of step form slot are easily controlled, can not cause too much chip area extravagant.

It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. Furthermore, it will be obvious that the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. Several elements recited in the apparatus claims may also be implemented by one element. The terms first, second, etc. are used to denote names, but not any particular order.

Claims (14)

1. A back-illuminated image sensor chip, comprising:

a semiconductor substrate having a front side and a back side;

the metal interconnection structure is positioned on the front surface of the semiconductor substrate;

and the step-shaped through hole or the step-shaped groove is positioned on the back surface of the semiconductor substrate, and a conductive layer is filled in the step-shaped through hole or the step-shaped groove to form a back surface routing.

2. The back-illuminated image sensor chip of claim 1, wherein the back side traces are in electrical communication with the front side metal interconnect structures.

3. The back-illuminated image sensor chip of claim 1, further comprising: and a pad structure of the image sensor chip formed by the conductive layer in the step-shaped through hole or the step-shaped groove.

4. The back-illuminated image sensor chip of claim 1, wherein the stepped via or stepped trench comprises a first opening and a second opening in the first opening, the bottom of the second opening being lower than the bottom of the first opening.

5. The back-illuminated image sensor chip of claim 4, wherein a dielectric layer covers the conductive layer and the bottom of the first opening, the sidewalls of the first opening, and the sidewalls of the second opening.

6. The back-illuminated image sensor chip of claim 1, wherein a surface height difference between the routing region of the back surface of the semiconductor substrate and the active pixel region and the metal shielding region is less than 0.5 μm.

7. The back-illuminated image sensor chip of claim 4, wherein a depth of the first opening does not penetrate the semiconductor substrate.

8. The back-illuminated image sensor chip of claim 1, wherein the conductive layer in the stepped via or the stepped trench comprises a first conductive layer and a second conductive layer located on the first conductive layer.

9. The back-illuminated image sensor chip of claim 1, further comprising deep trench isolation structures in active pixel regions and metal shielding regions at the back side of the semiconductor substrate.

10. The back-illuminated image sensor chip of claim 1, further comprising a deep P-type doped well surrounding the stepped via or stepped trench and a deep N-type doped well surrounding the deep P-type doped well in the semiconductor substrate.

11. The back-illuminated image sensor chip of claim 4, wherein the conductive layer in the first opening connects the metal interconnects of the front side to each other.

12. The back-illuminated image sensor chip of claim 11, wherein the conductive layer in the second opening connects the metal interconnects of the front side to each other.

13. The back-illuminated image sensor chip of claim 1, further comprising: and the step-shaped through hole or the step-shaped groove is positioned around the metal shielding area on the back surface of the semiconductor substrate, and a conductive layer is filled in the step-shaped through hole or the step-shaped groove.

14. The back-illuminated image sensor chip of claim 1, further comprising: and the step-shaped through hole or the step-shaped groove is positioned around the analog circuit area on the back surface of the semiconductor substrate, and a conductive layer is filled in the step-shaped through hole or the step-shaped groove.

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