CN108695173B

CN108695173B - Method for manufacturing semiconductor device

Info

Publication number: CN108695173B
Application number: CN201710220805.0A
Authority: CN
Inventors: 戚德奎; 陈福成
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-04-06
Filing date: 2017-04-06
Publication date: 2020-05-12
Anticipated expiration: 2037-04-06
Also published as: CN108695173A

Abstract

The invention provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a device wafer, the device wafer comprising: a plurality of embedded photodiode regions; a metal interconnection layer; a first groove outside the photodiode region, wherein a part of the metal interconnection layer is exposed at the bottom of the first groove; forming a patterned mask layer on the device wafer, wherein a first opening and a second opening exposing the first groove and a welding pad area outside the first groove are formed in the mask layer, and the number of the first openings is a plurality and the first openings are arranged at intervals; forming a conductive material layer on the bottom of the first opening, the bottom of the second opening and the bottom and the side wall of the first groove, wherein the conductive material layer on the bottom of the second opening and the bottom and the side wall of the first groove is a conductive layer electrically connected with the metal interconnection layer; and removing the mask layer to enable the parts of the conductive material layer except the conductive layer to form a grid structure, wherein grid openings are formed in the grid structure at positions corresponding to the mask layer.

Description

Method for manufacturing semiconductor device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device.

Background

Generally, an image sensor is a back-illuminated image sensor that converts an optical image into an electrical signal. The image sensor includes a Charge Coupled Device (CCD) and a Complementary Metal Oxide Semiconductor (CMOS) image sensor.

Since a CMOS Image Sensor (CIS) has improved manufacturing technology and characteristics, various aspects of semiconductor manufacturing technology have focused on developing CMOS image sensors. CMOS image sensors are manufactured using CMOS technology, and have lower power consumption, are easier to realize high integration, and manufacture devices having smaller sizes, and thus, CMOS image sensors are widely used in various products such as digital cameras and digital camcorders.

The backside illuminated (BSI) image sensor can reduce/avoid the absorption and reflection of light by the circuit layer or the oxide layer, thereby having higher sensitivity and signal-to-noise ratio. To improve photon capture efficiency, many high performance CMOS image sensors are now backside illuminated (BSI) image sensors.

As pixel sizes shrink, backside illuminated (BSI) image sensors are suffering from severe cross talk (crosstalk) problems. Mainly including the following crosstalk: spectral crosstalk (spectral crosstalk), optical crosstalk (optical crosstalk), and electrical crosstalk (electrical crosstalk). Among them, spectral crosstalk is caused by misalignment (mis-alignment) of a Color Filter (CF) process, optical crosstalk is caused by photons penetrating into an adjacent wrong photodiode, and electrical crosstalk is caused by electrons diffusing or drifting to other pixels. Spectral crosstalk (spectral crosstalk) and optical crosstalk (optical crosstalk) can be addressed by inlaying color filters into a metal mesh structure.

However, the existing backside illuminated (BSI) image sensor has a complex manufacturing process, and particularly after a metal grid structure is introduced, for example, a multi-step metal layer deposition is required, and a multi-step dry etching process is performed to pattern the metal layer to form structures such as metal grids, so that during the implementation of dry etching, etching plasma damage is easily caused to the device, and the performance and yield of the device are further affected.

Therefore, it is necessary to provide a new method for manufacturing a semiconductor device to solve the above technical problems.

Disclosure of Invention

In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

In view of the shortcomings of the prior art, the present invention provides a method for manufacturing a semiconductor device, comprising:

providing a device wafer, the device wafer comprising: a plurality of embedded photodiode regions; a metal interconnection layer; a first groove outside the photodiode region, wherein a part of the metal interconnection layer is exposed from the bottom of the first groove;

forming a patterned mask layer on the device wafer, wherein a first opening and a second opening exposing the first groove and a welding pad area outside the first groove are formed in the mask layer, and the number of the first openings is a plurality and the first openings are arranged at intervals;

forming a conductive material layer on the bottom of the first opening, the bottom of the second opening and the bottom and the side wall of the first groove, wherein the conductive material layer on the bottom of the second opening and the bottom and the side wall of the first groove is a conductive layer electrically connected with the metal interconnection layer;

and removing the mask layer to enable the part of the conductive material layer except the conductive layer to form a grid structure, wherein grid openings are formed in the grid structure at positions corresponding to the mask layer.

Further, the size of the top of the first opening is smaller than that of the bottom, and the size of the top of the second opening is smaller than that of the bottom.

Further, the projections of the photodiode regions and the grid openings in the thickness direction of the device wafer are overlapped and correspond to each other one by one.

Further, after the photodiode is formed and before the first groove is formed, a step of performing thinning processing on the surface of the device wafer, where the first groove is to be formed, is also included.

Further, the device wafer includes:

a device substrate, the photodiode region being located within the device substrate;

an interlayer dielectric layer located on the device substrate, the metal interconnection layer being located in the interlayer dielectric layer, the interlayer dielectric layer and the first groove being respectively disposed on opposite surfaces of the device substrate;

and the first groove sequentially penetrates through the insulating layer, the device substrate and part of the interlayer dielectric layer.

Further, the first groove includes a trench penetrating the insulating layer and the device substrate and a via opening penetrating a portion of the interlayer dielectric layer, the via opening exposes a portion of the surface of the metal interconnection layer, and a diameter of the trench is larger than a diameter of the via opening.

Further, the step of forming the first groove includes:

forming a first insulating layer on the device substrate, the first insulating layer and the interlayer dielectric layer being formed on opposite surfaces of the device substrate;

sequentially etching a part of the first insulating layer and the device substrate outside the photodiode until a part of the interlayer dielectric layer is exposed to form the groove;

forming a second insulating layer on the surface of the first insulating layer and the bottom and the side wall of the trench;

etching a part of the interlayer dielectric layer exposed from the trench until a part of the surface of the metal interconnection layer is exposed to form the via opening.

Further, the material of the mask layer comprises a photoresist material.

Further, the material of the conductive material layer includes a metal material including at least one of W, Al, Ti, TiN, Ta, and TaN.

And further, removing the mask layer by wet etching.

Further, after removing the mask layer, the method further comprises the following steps:

forming a cover layer to cover the mesh structure and the conductive layer;

etching and removing part of the covering layer in the welding pad area to form a welding pad opening exposing part of the conducting layer;

forming a welding pad on the conducting layer exposed from the welding pad opening;

and forming a solder ball on the welding pad.

Further, the method also comprises the following steps after the solder balls are formed:

forming a color filter in the mesh opening of the mesh structure such that the color filter is embedded in the mesh opening;

forming a plurality of microlenses on the surface of the color filter.

Further, the first insulating layer includes a nitride layer and an oxide layer sequentially formed on the second surface of the device substrate.

Further, the method also comprises the step of providing a support wafer and jointing the support wafer and the surface of the interlayer dielectric layer before the first groove is formed.

According to the manufacturing method, fewer dry etching process steps are used, the damage of etching plasma can be effectively reduced, in addition, a grid structure is formed, meanwhile, a conducting layer electrically connected with a subsequent welding pad is made, the process flow can be simplified, the process cost is greatly reduced, in addition, the grid structure is formed above the area between the adjacent photodiodes, the arrangement of the grid structure can effectively improve the spectrum and optical crosstalk of the device, and the performance of the device is improved.

Drawings

The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In the drawings:

fig. 1 illustrates a cross-sectional view of a BSI image sensor of one embodiment of the prior art;

fig. 2A to 2I show cross-sectional views of devices obtained at relevant steps of a method of fabricating a BSI image sensor of an embodiment of the invention, wherein fig. 2F also includes a partial top view of a grid structure;

fig. 3 shows a process flow diagram of a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.

It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.

Fig. 1 illustrates a cross-sectional view of a BSI image sensor of one embodiment of the prior art, in one example, a pixel region of the prior art BSI image sensor mainly includes: the pixel structure comprises a P-type substrate 100, a depletion region 101 formed in the P-type substrate, a gate structure 102 formed on the front surface of the P-type substrate 100, and a via 1031 electrically connected with the gate structure 102 and a metal interconnection layer 1032 electrically connected with the via, and further comprises an anti-reflection coating 104, a back passivation layer 105, a color filter 106 and a micro lens 107 which are sequentially formed on the back surface of the P-type substrate 100, wherein the elements shown in the dotted line boxes are the constituent elements of the pixel unit 10.

As pixel sizes shrink, backside illuminated (BSI) image sensors are suffering from severe cross talk (crosstalk) problems. Mainly including the following crosstalk: spectral crosstalk (spectral crosstalk), optical crosstalk (optical crosstalk), and electrical crosstalk (electrical crosstalk). Where spectral crosstalk is caused by mis-alignment of Color Filter (CF) process, causing a pixel cell to receive wrong color information, optical crosstalk is caused by photons penetrating into an adjacent wrong photodiode, and electrical crosstalk is caused by electrons diffusing or drifting to other wrong pixel cells. Spectral crosstalk (spectral crosstalk) and optical crosstalk (optical crosstalk) can be addressed by inlaying color filters into a metal mesh structure.

In order to solve the foregoing technical problem, an embodiment of the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 3, the method mainly includes the following steps:

step S1, providing a device wafer, the device wafer including: a plurality of embedded photodiode regions; a metal interconnection layer; a first groove outside the photodiode region, wherein a part of the metal interconnection layer is exposed from the bottom of the first groove;

step S2, forming a patterned mask layer on the device wafer, wherein first openings and second openings exposing the first grooves and the bonding pad areas outside the first grooves are formed in the mask layer, and the number of the first openings is a plurality and the first openings are arranged at intervals;

step S3, forming a conductive material layer on the bottom of the first opening, the bottom of the second opening, and the bottom and the sidewall of the first groove, wherein the conductive material layer on the bottom of the second opening and the bottom and the sidewall of the first groove is a conductive layer electrically connected to the metal interconnection layer;

step S4, removing the mask layer, so that a grid structure is formed on the conductive material layer except the conductive layer, and grid openings are formed in the grid structure at positions corresponding to the mask layer.

According to the manufacturing method, fewer dry etching process steps are used, the damage of etching plasma can be effectively reduced, in addition, a conductive layer electrically connected with a subsequent welding pad is made while a grid is formed, the process flow can be simplified, the process cost is greatly reduced, the grid is formed above the area between the adjacent photodiodes, the arrangement of the grid can effectively improve the spectrum and optical crosstalk of the device, and the performance of the device is improved.

In particular, the memory structure of the present invention is described in detail below with reference to fig. 2A-2I, wherein fig. 2A-2I illustrate cross-sectional views of devices obtained at relevant steps of a method of fabricating a BSI image sensor in accordance with one embodiment of the present invention.

In one example, the semiconductor device of the present invention is a BSI image sensor, and the manufacturing method thereof includes the steps of:

firstly, executing a step one, providing a device wafer, wherein the device wafer comprises: a plurality of embedded photodiode regions; a metal interconnection layer; and the bottom of the first groove exposes part of the metal interconnection layer. In the present invention, the photodiode region is buried, which means that the photodiode region is not exposed on the surface of the device wafer.

Specifically, as shown in fig. 2A, the device wafer includes: a device substrate 200, the photodiode region being located within the device substrate 200; an interlayer dielectric layer 202 on the device substrate 200, the metal interconnection layer 2031 being located within the interlayer dielectric layer 202, the interlayer dielectric layer 202 and the first groove being respectively disposed on opposite surfaces of the device substrate; and the first groove sequentially penetrates through the insulating layer, the device substrate and part of the interlayer dielectric layer.

The device substrate 200 may be at least one of the following mentioned materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others.

Wherein the device substrate 200 includes a first surface and a second surface disposed opposite to each other.

In one embodiment, the device substrate 200 includes a pixel region including a plurality of pixel units arranged in an array in the device substrate 200. The photodiode array includes a plurality of photodiodes and a plurality of pixel transistors, and is spread over the entire substrate in a pixel region, wherein a photodiode region 201 is formed in a device substrate 200 of each pixel unit, and adjacent photodiode regions are isolated from each other.

In one example, the photodiode region is located between the first and second surfaces of the device substrate 200, and is not exposed at the surfaces.

The photodiode may be a PN junction type photodiode, and illustratively, an N-type doped region may be formed in a P-type semiconductor substrate, and the N-type doped region and the P-type semiconductor substrate constitute the photodiode.

In one example, a plurality of CMOS devices (not shown) may be further formed on the first surface of the device substrate 200, and the CMOS devices may be constituent elements of the pixel unit, each of the CMOS devices including a well region formed in the semiconductor substrate, a source electrode and a drain electrode located in the well region, and a gate structure and the like located on the surface of the semiconductor substrate between the source electrode and the drain electrode. Wherein isolation structures (not shown) are also formed in the first surface of the device substrate 200 to isolate adjacent CMOS devices. In this embodiment, the isolation structure is preferably a shallow trench isolation structure.

In one example, an interlayer dielectric layer 202 is disposed on the first surface of the device substrate 200, and the interlayer dielectric layer 202 may be a silicon oxide layer, including a layer of doped or undoped silicon oxide material, such as Undoped Silicate Glass (USG), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG), formed using a thermal chemical vapor deposition (thermal CVD) process or a High Density Plasma (HDP) process. In addition, the interlayer dielectric layer may also be spin-on-glass (SOG) doped with boron or phosphorus, tetraethoxysilane (PTEOS) doped with phosphorus, or tetraethoxysilane (BTEOS) doped with boron.

The device substrate 200 includes a pixel region for forming various elements of an image sensor (e.g., a CMOS image sensor) and an interconnection structure, and a logic region for forming various interconnection structures and packaging structures, for example, a metal interconnection layer 2031 in a damascene interlayer dielectric layer is formed in the logic region.

Further, a plurality of interconnect structures 203 are disposed in the interlayer dielectric layer 202 at regions opposite to the pixel regions, where the interconnect structures 203 include metal layers (e.g., copper or aluminum layers), metal plugs for electrically connecting adjacent metal layers above and below, or metal vias, and a bottom metal layer of the interconnect structure is located above the first surface of the device substrate.

In one example, a metal interconnection layer 2031 is formed in the interlayer dielectric layer outside the photodiode region (i.e., the pixel region), and the metal interconnection layer 2031 is located at the same layer as the bottom metal layer of the interconnection structure and spaced apart from the bottom metal layer.

The interconnect structure may be formed by a conventional manufacturing method, for example, forming an interlayer dielectric layer 202, then patterning the interlayer dielectric layer to form an opening and filling the opening with a conductive material, and sequentially forming metal layers and vias to form the interconnect structure, wherein a metal interconnect layer 2031 may be formed simultaneously when forming a bottom metal layer of the interconnect structure, and a dielectric layer is further deposited after forming the top metal layer to cover the top metal layer and planarize the metal layer, as shown in fig. 2A.

Optionally, other devices, such as passive devices and rf devices, may also be formed in the device substrate 200.

Alternatively, the passive device may include a metal-insulator-metal capacitor (MIM), a spiral inductor, or the like. In this embodiment, transistors are used to form various circuits, rf devices are used to form rf components or modules, and interconnect structures are used to connect the transistors, rf devices, and other components in the front-end device.

The specific structure and the forming method of each component formed in the device substrate 200 may be selected by those skilled in the art according to actual needs by referring to the prior art, and are not described herein again.

In one example, a support wafer 300 is provided and the support wafer 300 and the surface of the interlayer dielectric layer 202 opposite the first surface of the device substrate 200 are bonded to effect bonding of the device substrate 200 and the support wafer 300, for example, using any suitable bonding method, such as oxide fusion bonding or the like.

The support wafer 300 may be any semiconductor material, such as at least one of the following: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. Other glass or ceramic materials may be used.

In one example, the second surface of the device substrate 200 may also be thinned to achieve a target thickness.

The thinning process of this step may be performed by any method known to those skilled in the art, such as an etching process or a back grinding process. In this embodiment, the thinning process is preferably performed using a back grinding process. Illustratively, after thinning, the remaining thickness of the device substrate 200 is in the range of 2-3 μm.

Wherein the photodiode is formed within the first surface of the device substrate, the thinned device substrate may have a thickness approximately equal to a depth of the photodiode.

Subsequently, as shown in fig. 2A, a first insulating layer is deposited and formed on the second surface of the thinned device substrate 200.

In one example, the material of the first insulating layer may include any suitable insulating material known to those skilled in the art, such as oxide and nitride, and the first insulating layer may be formed of a single thin film or a plurality of stacked thin films, for example, in this embodiment, the material of the first insulating layer includes oxide 204 and nitride 205 deposited in sequence, the oxide may include silicon oxide, and the nitride may include silicon nitride.

The thickness of the oxide 204 and the nitride 205 may be any suitable thickness, and is not limited in any way.

The first insulating layer can be formed by any of several methods. Non-limiting examples include chemical vapor deposition methods and physical vapor deposition methods.

Specifically, in one example, as shown in fig. 2C, the first recess includes a trench 2061 penetrating through the device substrate 200 and an insulating layer (e.g., a first insulating layer) and a via opening 2062 penetrating a portion of the interlayer dielectric layer 202, the via opening 2062 exposes a portion of the surface of the metal interconnect layer 2031, and the aperture of the trench 2061 is larger than the aperture of the via opening 2062.

Illustratively, the method of forming the first groove includes the steps of:

first, as shown in fig. 2B, a patterned photoresist layer (not shown) is formed on the surface of the first insulating layer, the photoresist layer defines a pattern of a predetermined trench to be formed, a portion of the first insulating layer outside the photodiode and the device substrate 200 are sequentially etched using the patterned photoresist layer as a mask until a portion of the interlayer dielectric layer 202 is exposed to form the trench 2061, and the photoresist layer is removed by, for example, ashing or wet etching.

The etching in this step may be performed by any dry etching or wet etching method known to those skilled in the art, and is not particularly limited herein.

Next, as shown in fig. 2C, a second insulating layer 207 is formed on the surface of the first insulating layer 205 and the bottom and the sidewall of the trench 2061.

The second insulating layer 207 can be formed by using an inorganic insulating layer such as a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, an insulating layer such as a layer containing polyvinyl phenol, polyimide, siloxane, or the like.

The second insulating layer 207 can be formed by any of several methods. Non-limiting examples include chemical vapor deposition methods and physical vapor deposition methods.

In this embodiment, the material of the second insulating layer 207 includes an oxide, particularly silicon oxide.

Next, with continued reference to fig. 2C, portions of the second insulating layer 207 and the interlayer dielectric layer 202 exposed from the trench 2061 are sequentially etched until portions of the surface of the metal interconnection layer 2031 are exposed to form the via opening 2062.

Specifically, a patterned photoresist layer may be formed on the second insulating layer, the photoresist layer defining a pattern of a via opening 2062 to be formed, a portion of the second insulating layer 207 and the interlayer dielectric layer 202 exposed from the trench 2061 may be sequentially etched using the patterned photoresist layer as a mask until a portion of the surface of the metal interconnection layer 2031 is exposed to form the via opening 2062, and then, the patterned photoresist layer may be removed using a method such as wet etching or dry etching.

The etching method of this step may use dry etching or wet etching.

And then, executing a second step, forming a patterned mask layer on the second surface of the device substrate, wherein a plurality of first openings defining a pattern of a predetermined grid structure and a plurality of second openings exposing pad areas outside the first groove are formed in the mask layer, and the pad areas are also positioned outside the first groove.

Specifically, as shown in fig. 2D, a patterned mask layer 208 is formed on the second surface of the device substrate 200, wherein a first opening 2081 defining a pattern of a predetermined grid structure and a second opening 2082 exposing the first groove and a pad area outside the photodiode area 201 (i.e., a pixel area) are formed in the mask layer 208, wherein a top of the first opening is smaller than a bottom of the first opening, a top of the second opening is smaller than a bottom of the second opening, and the pad area is also outside the first groove.

Wherein mask layer 208 may generally comprise any of several mask materials, including but not limited to: a hard mask material and a photoresist mask material. Preferably, the mask layer comprises a photoresist mask material. The photoresist mask material may include a photoresist material selected from the group consisting of a positive photoresist material, a negative photoresist material, and a hybrid photoresist material. Typically, the masking layer comprises a positive photoresist material or a negative photoresist material having a thickness of from about 2000 to about 5000 angstroms.

The size of the top of the first opening 2081 is smaller than that of the bottom, and the size of the top of the second opening 2082 is smaller than that of the bottom.

And the size of the bottom of the first opening 2081 is equal to the size of the predetermined mesh structure to be formed.

In one example, the patterned mask layer 208 may be formed by first spin-coating a photoresist layer on the second surface of the device substrate 200 and then using a photolithography process.

And then, a third step is executed, a conductive material layer is formed on the bottom of the first opening, the bottom of the second opening and the bottom and the side wall of the first groove exposed by the second opening, and the conductive material layer on the bottom of the second opening and the bottom and the side wall of the first groove is a conductive layer electrically connected with the metal interconnection layer.

Specifically, as shown in fig. 2E, a conductive material layer 209 is formed on the bottom of the first opening 2081 and the bottom and the sidewall of the first groove exposed by the second opening 2082 and on a portion of the second surface of the device substrate, and further, the conductive material layer 209 also covers the surface of the mask layer 208 and a portion of the sidewall of the first opening 2081 and the second opening 2082 on the top.

During the deposition of the conductive material layer 209, since the top of the first opening 2081 is smaller than the bottom, and the top of the second opening 2082 is smaller than the bottom, the sidewalls of the first opening 2081 and the second opening 2082 are inclined, that is, the sidewalls of the mask layer 208 exposed from the first opening 2081 and the second opening 2082 are inclined, the included angle between the sidewall of the first opening 2081 and the second surface of the device substrate exposed from the first opening 2081 is an acute angle, and the included angle between the sidewall of the second opening 2082 and the second surface of the device substrate exposed from the second opening 2082 is an acute angle, so that the conductive material layer 209 is difficult to be deposited on the portion of the sidewalls between the top and the bottom of the first opening and the second opening, and the sidewalls of the portion of the mask layer in the first opening and the second opening are exposed.

Further, when the second insulating layer 207 is formed on the second surface of the device substrate 200, the conductive material layer 209 located at the bottom of the first opening 2081 and the second opening 2082 is formed on the surface of the second insulating layer 207.

In one example, the conductive material layer 209 is formed on the bottom and the sidewall of the first groove exposed by the second opening 2082 and on a portion of the second surface of the device substrate, i.e., on the sidewall and the bottom of the trench 2061 and in the via opening, wherein further, the conductive material layer can fill the entire via opening to electrically connect to the metal interconnection layer 2031.

In one example, the conductive material layer further covers a portion of the second surface of the device substrate outside the first recess and in the pad area.

The material of the conductive material layer is not particularly limited as long as the material is conductive. It may include a metal or a metal compound, a conductive polymer, or the like, for example, in this embodiment, a metal material may be used as a material of the conductive material layer, wherein the metal material may include at least one of W, Al, Ti, titanium nitride (TiN), Ta, and tantalum nitride (TaN).

The conductive material layer 209 may be formed by Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Metal Organic Chemical Vapor Deposition (MOCVD), and Atomic Layer Deposition (ALD), or other advanced deposition techniques.

The thickness of the conductive material layer may be set reasonably according to the thickness of the predetermined grid, and is not limited herein.

And then, executing a fourth step, removing the mask layer, so that a grid structure is formed on the part of the conductive material layer except the conductive layer, and grid openings are formed in the grid structure at positions corresponding to the mask layer.

Specifically, as shown in fig. 2F, the mask layer is removed, so that a mesh structure 2092 is formed at a portion of the conductive material layer 209 except for the conductive layer 2092, and a mesh opening 209a is formed at a position corresponding to the mask layer in the mesh structure.

The mask layer 208 may be removed by any suitable method, and in the present embodiment, the mask layer 208 is preferably removed by a wet etching method, wherein the wet etching has a high etching rate for the mask layer 208, and has a low etching rate for the conductive material layer, the second insulating layer, and the like, or hardly causes any corrosion for the layers.

The masking layer (e.g., photoresist material) is removed using a wet etch, wherein the excess conductive material layer on top of the masking layer is naturally stripped away as the masking layer is removed.

In one example, the photoresist material can be removed using any suitable wet etching method known to those skilled in the art, such as by dissolving the photoresist material using an organic solvent or by using an ethanolic solution of potassium hydroxide.

Therefore, after the mask layer is removed, a grid structure located in the pixel region is formed, where the grid structure includes a conductive material layer and a plurality of grid openings penetrating through the conductive material layer, and the grid openings expose the surface of the second insulating layer 207, further, each grid opening may correspond to one pixel unit, and further, each grid opening corresponds to one photodiode region 201, that is, projections of the photodiode region 201 and the grid openings in the thickness direction of the device wafer coincide and correspond to each other one by one.

Finally, the portion of the deposited conductive material layer located in the pixel area forms a grid structure, while the portion located in the logic area (which may also be a pad area) outside the pixel area forms a conductive layer for electrically connecting the metal interconnection layer 2031 and a pad to be formed, the conductive layer including a back via formed by filling the via opening with the conductive material layer, and an outer back conductive layer formed on the bottom and sidewalls of the trench and on the second surface of the device substrate outside the trench (i.e., on the surface of the second insulating layer), the outer back conductive layer electrically connecting the back via and a pad to be formed later, the back via and the metal interconnection layer 2031 being electrically connected.

The grid structure and the conducting layer can be synchronously formed after the mask layer is removed by wet etching, so that plasma damage to a device caused by dry etching can be effectively avoided compared with the existing method for forming the grid structure and the conducting layer by using dry etching.

And then, executing a fifth step, forming a covering layer to cover the grid structure, the conducting layer and the second surface of the device substrate, and etching and removing part of the covering layer in the welding pad area to form a welding pad opening exposing part of the conducting layer.

Specifically, as shown in fig. 2G, a covering layer 210 is formed to cover the mesh structure 2091, the conductive layer 2092 and the second surface of the device substrate 200, and exemplarily, the conductive layer 2092 covers the exposed surface of the second insulating layer 207, and the surface of the conductive layer and the surface of the conductive material layer constituting the mesh structure 2091.

Illustratively, a portion of the cap layer 210 in the pad area is etched away to form a pad opening 210a exposing a portion of the conductive layer

The pad opening 210a may be formed by a photolithography process and an etching process, a patterned photoresist layer defining the pad opening 210a is formed first, then a portion of the cap layer 210 in the pad region is removed by etching using a method such as dry etching or wet etching, and finally the photoresist layer is removed.

And then, executing a sixth step, forming a welding pad on the conducting layer exposed from the welding pad opening, and forming a welding ball on the welding pad.

Specifically, as shown in fig. 2H, a pad 211 is formed on the conductive layer exposed by the pad opening, and a solder ball 212 is formed on the pad 211.

Wherein the pad 211 is a conductive material, the pad 201 is formed in the pad opening using PVD, CVD, sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process, as an example, the pad 211 may be an Under Bump Metallization (UBM) structure, which may be one or more layers of Ti, TiW, NiV, Cr, CrCu, Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. As one example, an Under Bump Metallization (UBM) structure may be formed from a multi-layer metal stack of an adhesion layer, a barrier layer, and a seed or wetting layer. The UBM structure helps prevent diffusion between the solder balls and the integrated circuit of the multi-chip semiconductor device while providing a low resistance electrical connection.

In one example, solder balls 212 are provided, and the solder balls 212 are placed over the solder pads 211.

The selected solder balls 212 matching with the solder pads are correspondingly placed on the solder pads 211, this process is called ball placement, the ball placement method can be manual ball placement or ball placement by a ball placement device, preferably ball placement by a ball placement device, the above process is prior art, and will not be described herein again. It should be noted that the present invention is only illustrated by using solder balls as an example, so the solder balls mentioned herein are not limited to strictly spherical solder, and may be solder or metal bumps with other shapes.

Optionally, a reflow process step may be performed after the ball mounting.

A reflow process step is performed to melt the solder balls 212 to electrically connect them with the pads 211. As an example, the temperature range for reflow soldering is 200 ℃ to 260 ℃.

Then, executing step seven, forming a color filter in the grid opening of the grid structure, so that the color filter is embedded in the grid opening; forming a plurality of microlenses on the surface of the color filter.

Specifically, as shown in fig. 2I, color filters 213 are formed in the grid openings of the grid structure such that the color filters 213 are embedded in the grid openings and adjacent color filters 213 are connected, and a plurality of microlenses 214 are formed on the surface of the color filters 213 without a gap between the adjacent microlenses 214.

A color filter means a filter that allows only light of a specific color component to pass through. Are generally disposed above the light receiving units in an array, and the color filter array includes red, green, and blue filters (primary color filters) or cyan, violet, and yellow filters (compensation filters) arranged to correspond to the pixels of the light receiving units, respectively, to obtain color information.

The microlens is generally arranged above the color filter in an array formation, and the microlens array means "a plurality of microlenses each having a hemispherical shape arranged above the photoelectric conversion device in a two-dimensional space to increase the amount of light entering the photodiode as the photoelectric conversion element of the pixel".

Any suitable method known to those skilled in the art can be used to form the color filters and the microlenses, and will not be described in detail here.

Thus, the introduction of the key steps of the method for manufacturing a semiconductor device of the present invention is completed, and other steps are required for the preparation of the complete device, which is not described herein again.

In summary, the manufacturing method of the present invention can realize the manufacturing of the grid structure and the conductive layer and other elements by using fewer dry etching process steps, which can effectively reduce the etching plasma damage, and in addition, the conductive layer electrically connected with the subsequent bonding pad is formed while forming the grid (the conductive layer includes the through hole electrically connected with the metal interconnection layer and the outer back conductive layer electrically connected with the back through hole and the bonding pad), which can simplify the process flow and greatly reduce the process cost.

The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

and removing the mask layer to enable the part of the conductive material layer except the conductive layer to form a grid structure, wherein grid openings are formed in the grid structure at positions corresponding to the mask layer, the size of the top of the first opening is smaller than that of the bottom, the size of the top of the second opening is smaller than that of the bottom, and the mask layer is removed through wet etching.

2. The method of claim 1, wherein the projections of the photodiode regions and the grid openings in the thickness direction of the device wafer are coincident and correspond one-to-one.

3. The manufacturing method according to claim 1, further comprising a step of performing thinning processing on a surface of the device wafer on which the first groove is to be formed, after the photodiode is formed, before the first groove is formed.

4. The method of manufacturing of claim 1, wherein the device wafer comprises:

5. The manufacturing method according to claim 4, wherein the first recess includes a trench penetrating the insulating layer and the device substrate and a via opening penetrating a portion of the interlayer dielectric layer, the via opening exposing a portion of a surface of the metal interconnection layer, and an aperture of the trench is larger than an aperture of the via opening.

6. The method of manufacturing of claim 5, wherein the step of forming the first recess comprises:

7. The method of manufacturing of claim 1, wherein the material of the masking layer comprises a photoresist material.

8. The manufacturing method according to claim 1, wherein a material of the conductive material layer includes a metal material including at least one of W, Al, Ti, TiN, Ta, and TaN.

9. The method of manufacturing of claim 1, further comprising, after removing the mask layer, the steps of:

forming a cover layer to cover the mesh structure and the conductive layer;

and forming a solder ball on the welding pad.

10. The manufacturing method of claim 9, further comprising, after forming the solder balls, the steps of:

forming a plurality of microlenses on the surface of the color filter.

11. The manufacturing method according to claim 6, wherein the first insulating layer comprises a nitride layer and an oxide layer which are sequentially formed on the second surface of the device substrate.

12. The method of manufacturing of claim 4, further comprising the step of providing a support wafer and bonding the support wafer to the surface of the interlevel dielectric layer prior to forming the first recess.