CN108695173A - A kind of manufacturing method of semiconductor devices - Google Patents
A kind of manufacturing method of semiconductor devices Download PDFInfo
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- CN108695173A CN108695173A CN201710220805.0A CN201710220805A CN108695173A CN 108695173 A CN108695173 A CN 108695173A CN 201710220805 A CN201710220805 A CN 201710220805A CN 108695173 A CN108695173 A CN 108695173A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
Abstract
The present invention provides a kind of manufacturing method of semiconductor devices, including:Device wafers are provided, the device wafers include:Inbuilt several photodiode regions;Metal interconnecting layer;The first groove on the outside of photodiode region, the bottom exposed portion metal interconnecting layer of the first groove;Patterned mask layer is formed in device wafers, the first opening is formed in mask layer and is formed with the second opening for exposing the pad zone on the outside of the first groove and the first groove, and the quantity of the first opening is several and is spaced setting;Conductive material layer is formed in the bottom and side wall of the bottom of the first opening, the bottom of the second opening and the first groove, the conductive material layer in the second open bottom and the first bottom portion of groove and side wall is the conductive layer being electrically connected with metal interconnecting layer;Remove mask layer so that part of the conductive material layer in addition to conductive layer forms network, and network is formed with mesh openings in the position of corresponding mask layer.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of manufacturing method of semiconductor devices.
Background technology
In general, imaging sensor is the back side illumination image sensor that optical imagery is converted into electric signal.Imaging sensor
Including charge coupling device (CCD) and complementary metal oxide semiconductor (CMOS) imaging sensor.
Since cmos image sensor (CMOS image sensor, CIS) has improved manufacturing technology and characteristic, because
This semiconductor fabrication everyway concentrates on exploitation cmos image sensor.Cmos image sensor utilizes CMOS technology system
It makes, and there is lower power consumption, it is easier to it realizes highly integrated, produces smaller device, therefore, cmos image sensing
Device is widely used in various products, such as digital camera and digital camera etc..
Back-illuminated type (BSI) imaging sensor can reduce/avoid circuit layer or oxide layer absorption and reflection to light, because
And there is higher sensitivity and signal-to-noise ratio.In order to improve photon arresting efficiency, present many high-performance CMOS image sensors
All it is back-illuminated type (BSI) imaging sensor.
With the diminution of Pixel Dimensions, back-illuminated type (BSI) imaging sensor is just asked by serious crosstalk (crosstalk)
Topic.Include mainly following several crosstalks:Spectra overlap (spectral crosstalk), optical crosstalk (optical
) and electrical crosstalk (electrical crosstalk) crosstalk.Wherein, spectra overlap by filter (color filter,
CF) misalignment (mis-alignment) of technique causes, and optical crosstalk is that adjacent wrong photodiode is penetrated by photon
In cause, electrical crosstalk is electrons spread or floats to caused by other pixels.Spectra overlap (spectral crosstalk) and
Optical crosstalk (optical crosstalk) can be solved by the way that filter to be mounted in metal mesh structure.
However, the preparation process of existing back-illuminated type (BSI) imaging sensor is complicated, especially metal grill is being introduced
After structure, for example, it is desired to multiple deposition metal layer, and the dry etch process step of multistep is carried out, to carry out figure to metal layer
To form the structures such as metal grill, dry etching is easy to cause etching plasma to damage device case during implementing,
And then influence the performance and yields of device.
Therefore, it is necessary to propose a kind of manufacturing method of new semiconductor devices, to solve the above technical problems.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In view of the deficiencies of the prior art, the present invention provides a kind of manufacturing method of semiconductor devices, including:
Device wafers are provided, the device wafers include:Inbuilt several photodiode regions;Metal interconnecting layer;It is described
The first groove on the outside of photodiode region, metal interconnecting layer described in the bottom exposed portion of first groove;
Patterned mask layer is formed in the device wafers, and the first opening and formation are formed in the mask layer
There is expose the pad zone on the outside of first groove and first groove second to be open, the quantity of first opening is
Several are simultaneously spaced setting;
In the bottom and side wall of the bottom of first opening, the bottom of second opening and first groove
Conductive material layer is formed, the conductive material layer in second open bottom and first bottom portion of groove and side wall is
The conductive layer being electrically connected with the metal interconnecting layer;
Removing the mask layer so that part of the conductive material layer in addition to the conductive layer forms network,
The network is formed with mesh openings in the position of the correspondence mask layer.
Further, the top dimension of first opening is less than the size of bottom, and the top dimension of second opening is small
Size in bottom.
Further, the projection of the photodiode region, the mesh openings on the thickness direction of the device wafers
It overlaps, and corresponds.
Further, further include to the device before forming first groove after forming the photodiode
The step of predetermined surface for forming first groove of part wafer carries out reduction processing.
Further, the device wafers include:
Device substrate, the photodiode region are located in the device substrate;
Interlayer dielectric layer in the device substrate, the metal interconnecting layer are located in the interlayer dielectric layer, institute
It states interlayer dielectric layer and first groove is separately positioned on the opposite surface of the device substrate;
Insulating layer in the device substrate and photodiode region, first groove sequentially pass through the insulation
Layer, the device substrate and the part interlayer dielectric layer.
Further, first groove includes the groove and through part through the insulating layer and the device substrate
The via openings of the interlayer dielectric layer, the surface of metal interconnecting layer described in the via openings exposed portion, the groove
Bore is more than the bore of the via openings.
Further, the step of formation first groove includes:
The first insulating layer is formed in the device substrate, first insulating layer and the interlayer dielectric layer are formed in institute
It states on the opposite surface of device substrate;
Part first insulating layer and the device substrate being sequentially etched on the outside of the photodiode, until exposing
The part interlayer dielectric layer, to form the groove;
Second insulating layer is formed in the bottom and side wall of the surface of first insulating layer and the groove;
The part interlayer dielectric layer that exposes from the groove is etched, the metal interconnecting layer described in the exposed portion
Surface, to form the via openings.
Further, the material of the mask layer includes Other substrate materials.
Further, the material of the conductive material layer includes metal material, the metal material include W, Al, Ti, TiN,
At least one of Ta and TaN.
Further, wet etching removes the mask layer.
Further, further comprising the steps of after removing the mask layer:
Coating is formed, to cover the network and the conductive layer;
The part coating in etching removal pad zone, to form the welding pad opening of conductive layer described in exposed portion;
Weld pad is formed on the conductive layer that the welding pad opening exposes;
Soldered ball is formed on the weld pad.
Further, further comprising the steps of after forming the soldered ball:
Filter is formed in the mesh openings of the network, so that filter is embedded in the mesh openings
In;
Several lenticules are formed on the surface of the filter.
Further, first insulating layer includes the nitride layer being sequentially formed on the second surface of the device substrate
And oxide skin(coating).
Further, further include that support wafer is provided before forming the first groove, by the support wafer and the interlayer
The step of surface of dielectric layer engages.
Manufacturing method according to the invention, using less dry etch process step, can effectively reduce etching etc. from
Son damage, in addition, doing the conductive layer for being electrically connected with subsequent weld pad while forming network, can simplify technique
Process costs are greatly reduced in flow, and overlying regions of the manufacturing method of the present invention between adjacent photodiode are formed
Network, the setting of network can effectively improve the improvement spectrum and optical crosstalk of device, improve the performance of device.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Fig. 1 shows the sectional view of the BSI imaging sensors of an existing embodiment;
Fig. 2A to Fig. 2 I shows the correlation step of the manufacturing method of the BSI imaging sensors of one embodiment of the present invention
The sectional view of the device obtained further includes the partial top view of network in wherein Fig. 2 F;
Fig. 3 shows the process flow chart of the manufacturing method of the semiconductor devices of one embodiment of the present invention.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further includes making
With the different orientation with the device in operation.For example, if the device in attached drawing is overturn, then, it is described as " under other elements
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute
There is combination.
It describes to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the variation of shown shape.Therefore,
The embodiment of the present invention should not necessarily be limited to the specific shape in area shown here, but include due to for example manufacturing caused shape
Shape deviation.For example, be shown as the injection region of rectangle its edge usually there is circle or bending features and/or implantation concentration ladder
Degree, rather than the binary from injection region to non-injection regions changes.Equally, the disposal area can be led to by injecting the disposal area formed
Some injections in area between the surface passed through when injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step and structure will be proposed in following description, to illustrate this
Invent the technical solution proposed.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this hair
It is bright to have other embodiment.
Fig. 1 shows the sectional view of the BSI imaging sensors of an existing embodiment, in one example, existing
The pixel regions of BSI imaging sensors include mainly:P type substrate 100, the depletion region 101 being formed in P type substrate, is formed in P
100 positive gate structure 102 of type substrate, and be electrically connected with gate structure 102 through-hole 1031 and through-hole electrical connection gold
Belong to interconnection layer 1032, further includes the anti-reflection coating 104 for being sequentially formed at 100 back side of P type substrate, back-passivated layer 105, colour filter
Mirror 106 and lenticule 107, the element wherein shown in dashed rectangle are the constituent element of pixel unit 10.
With the diminution of Pixel Dimensions, back-illuminated type (BSI) imaging sensor is just asked by serious crosstalk (crosstalk)
Topic.Include mainly following several crosstalks:Spectra overlap (spectral crosstalk), optical crosstalk (optical
) and electrical crosstalk (electrical crosstalk) crosstalk.Wherein, spectra overlap by filter (color filter,
CF) misalignment (mis-alignment) of technique causes, and pixel unit is made to receive wrong colouring information, optical crosstalk be by
Photon, which is penetrated into adjacent wrong photodiode, to be caused, and electrical crosstalk is electrons spread or floats to the pixel unit of other mistakes
It is caused.Spectra overlap (spectral crosstalk) and optical crosstalk (optical crosstalk) can be by that will filter
Look mirror is mounted in metal mesh structure and solves.
However, the preparation process of existing back-illuminated type (BSI) imaging sensor is complicated, especially metal grill is being introduced
After structure, for example, it is desired to multiple deposition metal layer, and the dry etch process step of multistep is carried out, to carry out figure to metal layer
To form the structures such as metal grill, dry etching is easy to cause etching plasma to damage device case during implementing,
And then influence the performance and yields of device.
In order to solve aforementioned technical problem, a kind of manufacturing method of semiconductor devices is provided in the embodiment of the present invention, such as
Shown in Fig. 3, the manufacturing method mainly includes the following steps that:
Step S1, provides device wafers, and the device wafers include:Inbuilt several photodiode regions;Metal interconnects
Layer;The first groove on the outside of the photodiode region, metal interconnecting layer described in the bottom exposed portion of first groove;
Step S2 forms patterned mask layer in the device wafers, the first opening is formed in the mask layer
And it is formed with the second opening for exposing the pad zone on the outside of first groove and first groove, first opening
Quantity be several and be spaced setting;
Step S3, the bottom in the bottom of first opening, the bottom of second opening and first groove
With conductive material layer, the conduction in second open bottom and first bottom portion of groove and side wall are formed on side wall
Material layer is the conductive layer being electrically connected with the metal interconnecting layer;
Step S4 removes the mask layer so that part of the conductive material layer in addition to the conductive layer forms net
Lattice structure, the network are formed with mesh openings in the position of the correspondence mask layer.
Manufacturing method according to the invention, using less dry etch process step, can effectively reduce etching etc. from
Son damage, in addition, doing the conductive layer for being electrically connected with subsequent weld pad while forming grid, can simplify technique stream
Process costs are greatly reduced in journey, and overlying regions of the manufacturing method of the present invention between adjacent photodiode form net
Lattice, the setting of grid can effectively improve the improvement spectrum and optical crosstalk of device, improve the performance of device.
Specifically, the memory construction of the present invention is described in detail below with reference to Fig. 2A-Fig. 2 I, wherein Fig. 2A to figure
2I shows cuing open for the device that the correlation step of the manufacturing method of the BSI imaging sensors of one embodiment of the present invention is obtained
View.
In one example, semiconductor devices of the invention is BSI imaging sensors, and manufacturing method includes following step
Suddenly:
First, step 1 is executed, provides device wafers, the device wafers include:Inbuilt several photodiode regions;
Metal interconnecting layer;The first groove on the outside of the photodiode region, metal described in the bottom exposed portion of first groove
Interconnection layer.In the present invention, so-called photodiode region is embedded refers to photodiode region and is not exposed to the table of device wafers
Face.
Specifically, as shown in Figure 2 A, the device wafers include:Device substrate 200, the photodiode region are located at institute
It states in device substrate 200;Interlayer dielectric layer 202 in the device substrate 200, the metal interconnecting layer 2031 are located at institute
It states in interlayer dielectric layer 202, it is opposite that the interlayer dielectric layer 202 with first groove is separately positioned on the device substrate
On surface;Insulating layer in the device substrate and photodiode region, first groove sequentially pass through the insulation
Layer, the device substrate and the part interlayer dielectric layer.
The device substrate 200 can be following at least one of the material being previously mentioned:Silicon, silicon-on-insulator (SOI),
Be laminated on insulator silicon (SSOI), stacking SiGe (S-SiGeOI) on insulator, germanium on insulator SiClx (SiGeOI) and
Germanium on insulator (GeOI) etc..
Wherein, the device substrate 200 includes the first surface and second surface being oppositely arranged.
In one embodiment, the device substrate 200 includes pixel region, and pixel region includes multiple pixel units, these
Pixel unit is arranged in array way in device substrate 200.Photodiode array includes multiple photodiodes and multiple
Pixel transistor is dispersed throughout in the entire substrate in pixel region, wherein the equal shape in the device substrate 200 of each pixel unit
It is mutually isolated between adjacent photodiode area at there is a photodiode region 201.
In one example, photodiode region is located between the first surface and second surface of device substrate 200, not
It is exposed to surface.
Wherein, the photodiode can be that PN junction photodiode illustratively can be in P-type semiconductor substrate
Middle formation N-doped zone, N-doped zone and P-type semiconductor substrate constitute photodiode.
In one example, multiple cmos device (not shown) can also be formed in the first surface of device substrate 200,
Cmos device can include the trap being formed in semiconductor substrate as the constituent element of pixel unit, each cmos device
Area, the gate structure in the source electrode and drain electrode being located in well region, and semiconductor substrate surface between source electrode and drain electrode
Deng.Wherein, isolation structure (not shown) is also formed in the first surface of the device substrate 200, it is adjacent to be isolated
Cmos device.In the present embodiment, isolation structure is preferably fleet plough groove isolation structure.
In one example, interlayer dielectric layer 202, layer are provided on the first surface of the device substrate 200
Between dielectric layer 202 can be silicon oxide layer, including the use of thermal chemical vapor deposition (thermal CVD) manufacturing process or high density etc.
The material layer for having doped or undoped silica that gas ions (HDP) manufacturing process is formed, such as undoped silica glass
(USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).In addition, interlayer dielectric layer can also be doping boron or doping phosphorus
Spin cloth of coating-type glass (spin-on-glass, SOG), the tetraethoxysilane (PTEOS) of doping phosphorus or boron-doped four ethoxy
Base silane (BTEOS).
Wherein, the device substrate 200 includes pixel region and logic area, wherein the pixel region is used to form image biography
The various elements and interconnection structure of sensor (such as cmos image sensor), the logic area are used to form various interconnection structures
And encapsulating structure, such as the metal interconnecting layer 2031 that is formed in the logic area in inlaying interlayer dielectric layer.
Further, region opposite with the pixel region in interlayer dielectric layer 202 is provided with multiple interconnection structures
203, the interconnection structure 203 includes that metal layer (such as layers of copper or aluminium layer), metal plug or metal throuth hole, metal plug are used for
It is electrically connected neighbouring metal layer, wherein the bottom metal layer of the interconnection structure is located at the first surface of the device substrate
Top.
In one example, it is formed in the interlayer dielectric layer on the outside of the photodiode region (namely pixel region)
There is a metal interconnecting layer 2031, the bottom metal layers of metal interconnecting layer 2031 and interconnection structure are located at identical layer, and interval is set
It sets.
Wherein, the forming method of the interconnection structure can select conventional manufacturing method, such as form interlayer dielectric layer
202, then the interlayer dielectric layer is patterned, to form opening and conductive material is selected to fill the opening, successively
Each metal layer and through-hole are formed, to form the interconnection structure, wherein can be same when forming the bottom metal layers of interconnection structure
Step forms metal interconnecting layer 2031, the further dielectric layer after forming the metal layer at top, to cover the top
Metal layer simultaneously planarizes, as shown in Figure 2 A.
Optionally, other devices, such as passive device and radio-frequency devices can also be formed in the device substrate 200
Deng.
Optionally, the passive device may include metal-insulating layer-metal capacitor (MIM), spiral inductor etc..
In the present embodiment, transistor is for constituting various circuits, and radio-frequency devices are used to form radio frequency component or module, and interconnection structure is used for
Connect the other assemblies in transistor, radio-frequency devices and front-end devices.
Wherein, the concrete structure and forming method of the various components formed in the device substrate 200, the skill of this field
Art personnel can select with reference to the prior art according to actual needs, and details are not described herein again.
In one example, provide support wafer 300, by it is described support wafer 300 and the interlayer dielectric layer 202 with
The surface that the first surface of the device substrate 200 is opposite engages, to realize device substrate 200 and support wafer 300
Engagement, for example, any suitable bonding method, which can be used, carries out the engagement step, for example, oxide fusion bonding etc..
It can be any semi-conducting material, such as following at least one of the material being previously mentioned to support wafer 300:Silicon,
Silicon (SSOI), stacking SiGe (S-SiGeOI), germanium on insulator on insulator are laminated on silicon-on-insulator (SOI), insulator
SiClx (SiGeOI) and germanium on insulator (GeOI) etc..Or other glass or ceramic material etc..
In one example, can also reduction processing be carried out to the second surface of the device substrate 200, to reach mesh
Mark thickness.
The reduction processing that any method well known to those skilled in the art carries out this step can be used, for example, etching technics
Or backgrind technique etc..In the present embodiment, reduction processing is carried out preferably with backgrind technique.Illustratively, subtract
Bao Hou, ranging from 2~3 μm of the residual thickness of the device substrate 200.
Wherein, the photodiode is formed in the first surface of the device substrate, can be made after being thinned
The thickness of the device substrate is approximately equal to the depth of the photodiode.
Then, as shown in Figure 2 A, deposition forms the first insulation on the second surface of the device substrate 200 after being thinned
Layer.
In one example, the material of first insulating layer may include well known to those skilled in the art any suitable
Insulating materials, such as oxide, nitride, first insulating layer can be made of the film of single layer, can also be by multilayer layer
Folded film is constituted, for example, in the present embodiment, the material of first insulating layer includes being sequentially depositing the oxide 204 to be formed
With nitride 205, oxide may include silica, and nitride may include silicon nitride.
Wherein, the thickness range of oxide 204 and nitride 205 can be any suitable thickness, not do herein specific
It limits.
Any one of several methods may be used and form aforementioned first insulating layer.Non-limiting examples include chemical gas
Phase deposition method and physical gas-phase deposite method.
Specifically, in one example, as shown in Figure 2 C, first groove includes running through 200 He of the device substrate
The via openings 2062 of interlayer dielectric layer 202 described in the groove 2061 and through part of insulating layer (such as first insulating layer),
The bore on the surface of metal interconnecting layer 2031 described in 2062 exposed portion of the via openings, the groove 2061 is more than described lead to
The bore of hole opening 2062.
Illustratively, the method for forming first groove includes the following steps:
First, as shown in Figure 2 B, patterned photoresist layer (not shown) is formed on the surface of first insulating layer,
The pattern that the photoresist layer defines the groove of predetermined formation is sequentially etched using the patterned photoresist layer as mask
Part first insulating layer on the outside of the photodiode and the device substrate 200, the interlayer described in the exposed portion
Dielectric layer 202, to form the groove 2061, then for example, by the method for the ashing or wet etching removal photoresist
Layer.
The method that any dry etching or wet etching well known to those skilled in the art can be used carries out this step
Rapid etching, is not specifically limited herein.
Then, as shown in Figure 2 C, in the surface of first insulating layer 205 and the bottom and side wall of the groove 2061
Upper formation second insulating layer 207.
Second insulating layer 207 can be by using such as inorganic insulation of silicon oxide layer, silicon nitride layer or silicon oxynitride layer
Layer, including insulating layer of the layer of polyvinyl phenol, polyimides or siloxanes etc. etc. is formed.
Any one of several methods may be used and form aforementioned second insulating layer 207.Non-limiting examples include changing
Learn vapor deposition method and physical gas-phase deposite method.
In the present embodiment, the material of the second insulating layer 207 includes oxide, especially silica.
Then, with continued reference to Fig. 2 C, the part exposed from the groove 2061 second insulating layer 207 is etched successively
With the interlayer dielectric layer 202, the surface of the metal interconnecting layer 2031 described in the exposed portion, to form the via openings
2062。
Specifically, patterned photoresist layer can be formed over the second dielectric, and photoresist layer definition has predetermined formation
The patterns of via openings 2062 etch reveal from the groove 2061 successively using the patterned photoresist layer as mask
The part second insulating layer 207 and the interlayer dielectric layer 202 gone out, the metal interconnecting layer 2031 described in the exposed portion
Surface then, the figure is removed using the method for such as wet etching or dry etching to form the via openings 2062
The photoresist layer of case.
The engraving method of this step can use dry etching or wet etching.
Then, step 2 is executed, patterned mask layer is formed in the second surface of the device substrate, it is described to cover
Formed in film layer be defined preboarding at network pattern the first opening and be formed with and expose first groove
The quantity of second opening of the pad zone in outside, first opening is several and is spaced setting, wherein first opening
The size at top is less than the size of bottom, and the top dimension of second opening is less than the size of bottom, and the pad zone is also simultaneously
Positioned at the outside of first groove.
Specifically, as shown in Figure 2 D, patterned mask layer is formed in the second surface of the device substrate 200
208, formed in the mask layer 208 be defined preboarding at network pattern the first opening 2081 and be formed with
Expose the second opening of the pad zone on the outside of first groove and the photodiode region 201 (namely pixel region)
2082, wherein the size of first open top is less than the size of bottom, and the top dimension of second opening is less than bottom
Size, the pad zone also simultaneously positioned at first groove outside.
Wherein mask layer 208 usually may include any type of several mask materials, including but not limited to:Hard mask material
Material and photoresist mask material.Preferably, mask layer includes photoresist mask material.Photoresist mask material may include being selected from
Other substrate materials in group including positive-tone photo glue material, negative photo glue material and mixing Other substrate materials.In general, mask
Layer includes the positive-tone photo glue material or negative photo glue material with from about 2000 to about 5000 angstroms of thickness.
Wherein, the size at 2081 top of the first opening is less than the size of bottom, and the size at 2082 top of the second opening is less than
The size of bottom.
And the size of the first 2081 bottoms of opening and the network of predetermined formation is equal sized.
In one example, photoetching process shape can be recycled first in the second surface spin coating lithography layer of device substrate 200
At the patterned mask layer 208.
Then, step 3 is executed, is opened in the bottom of first opening, the bottom of second opening and described second
Conductive material layer, second open bottom and described first are formed in the bottom and side wall for first groove that mouth exposes
The conductive material layer on bottom portion of groove and side wall is the conductive layer being electrically connected with the metal interconnecting layer.
Specifically, as shown in Figure 2 E, expose in the bottom of first opening 2081 and second opening 2082
Conductive material layer is formed in the bottom and side wall of first groove and on the second surface of the part device substrate
209, further the conductive material layer 209 also cover the mask layer 208 surface and it is described first opening 2081 Hes
Second opening 2082 is located at the partial sidewall at top.
Wherein, during conductive material layer 209 deposits, since the size at 2081 top of the first opening is less than bottom
The size of size, 2082 top of the second opening is less than the size of bottom, therefore, is located at the first opening 2081 and the second opening 2082
Sidewall slope, namely the side wall of mask layer 208 that exposes from the first opening 2081 and the second opening 2082 be it is inclined, the
The side wall of one opening 2081 and from the angle between the second surface of device substrate exposed in the first opening 2081 be acute angle, the
The side wall of two openings 2082 and from the angle between the second surface of device substrate exposed in the second opening 2082 be acute angle, because
This, conductive material layer 209 be difficult deposit in the first opening and partial sidewall between the second open top and bottom, and
So that the side wall exposure of the first opening and the part mask layer in the second opening.
Further, when the second surface of the device substrate 200 is formed with second insulating layer 207, it is located at described the
The conductive material layer 209 of 2082 bottoms of one opening 2081 and second opening is both formed on the surface of second insulating layer 207.
In one example, in the bottom and side wall for first groove that second opening 2082 is exposed and part
Form conductive material layer 209 on the second surface of the device substrate, namely in the side wall of groove 2061 and bottom and
Conductive material layer is each formed in via openings, wherein further, the also fillable full entire via openings of conductive material layer,
So that it is electrically connected with metal interconnecting layer 2031.
In one example, conductive material layer also further covers the part device positioned at pad zone on the outside of the first groove
The second surface of part substrate.
As long as material is conductive, the material of conductive material layer is not particularly limited.It may include metal or gold
Belong to compound or conducting polymer etc., for example, in the present embodiment, the material of conductive material layer can use metal material,
In, metal material may include at least one of W, Al, Ti, titanium nitride (TiN), Ta and tantalum nitride (TaN).
Conductive material layer 209 can pass through low-pressure chemical vapor deposition (LPCVD), plasma auxiliary chemical vapor deposition
(PECVD), metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD) or other advanced deposition techniques are formed.
Wherein, the thickness of conductive material layer can according to the thickness of the grid of predetermined formation reasonable set, do not do herein
Concrete restriction.
Then, step 4 is executed, removes the mask layer so that portion of the conductive material layer in addition to the conductive layer
Divide and form network, the network is formed with mesh openings in the position of the correspondence mask layer.
Specifically, as shown in Figure 2 F, the mask layer is removed so that the conductive material layer 209 removes the conductive layer
Part except 2092 forms network 2092, and the network is formed with grid in the position of the correspondence mask layer and opens
Mouth 209a.
Any suitable method can be used to remove the mask layer 208, in the present embodiment, preferably, being carved using wet method
The method of erosion removes mask layer 208, wherein and wet etching has the etch-rate high to mask layer 208, and for conductive material
Layer and second insulating layer etc. have low rate or hardly cause any corrosion to those film layers.
Using wet etching removal mask layer (for example, Other substrate materials), wherein extra at the top of the mask layer is led
Material layer naturally falls off removal when mask layer is removed.
Big vast in one example, the method that can use any suitable wet etching well known to those skilled in the art is gone
Except Other substrate materials, organic solvent dissolving removal Other substrate materials can be used for example, ethanolic potassium hydroxide can also be used molten
Liquid removes Other substrate materials.
Therefore, after removing mask layer, that is, the network positioned at pixel region is formd, which includes conduction
Material layer and several mesh openings through the conductive material layer, mesh openings expose the surface of second insulating layer 207, into one
Step ground, each mesh openings can correspond to a pixel unit, and further, each mesh openings correspond to two pole of luminous point
The projection of area under control 201 namely the photodiode region 201, the mesh openings on the thickness direction of the device wafers
It overlaps, and corresponds.
Finally, the conductive material layer of deposition is located at the part formation network of pixel region, and on the outside of pixel region
The part of logic area (can also be pad zone) forms conductive layer, and the conductive layer is simultaneously and pre- for being electrically connected metal interconnecting layer 2031
The weld pad being shaped as, the conductive layer include the backside vias and shape filled the via openings by conductive material layer and formed
At (namely the surface of second insulating layer on channel bottom and side wall and on the second surface of groove exterior portion device substrate
On) outer back conductive layer, this outer back conductive layer electrical connection backside vias and weld pad for being formed later, backside vias and metal
Interconnection layer 2031 is electrically connected.
Wherein, using can synchronize to form network and conductive layer after wet etching removal mask layer, thus with it is existing
Some forms network using dry etching and is compared with the method for conductive layer, it is possible to prevente effectively from dry etching causes device
Plasma damage.
Then, step 5 is executed, coating is formed, is served as a contrast with covering the network, the conductive layer and the device
The second surface at bottom, etching removes the part coating in pad zone, to form the weld pad of exposed portion conductive layer
Opening.
Specifically, as shown in Figure 2 G, coating 210 is formed, to cover the network 2091, the conductive layer 2092
With the second surface of the device substrate 200, illustratively, second insulation that the covering of the conductive layer 2092 is exposed
The surface of the conductive material layer of the surface of layer 207 and the surface of conductive layer and composition network 2091.
Illustratively, the part coating 210 of etching removal pad zone, to form the weld pad of exposed portion conductive layer
Be open 210a
Photoetching process and etch process can be utilized to form welding pad opening 210a, being initially formed definition has welding pad opening 210a's
Patterned photoresist layer recycles the method etching of such as dry etching or wet etching to remove described in the part of pad zone
Coating 210, finally removes photoresist layer.
Then, step 6 is executed, weld pad is formed on the conductive layer that the welding pad opening exposes, on the weld pad
Form soldered ball.
Specifically, as illustrated in figure 2h, weld pad 211 is formed on the conductive layer that the welding pad opening exposes, described
Soldered ball 212 is formed on weld pad 211.
Wherein, the weld pad 211 be conductive material, using PVD, CVD, sputtering, electrolysis plating, electrodeless plating technique,
Or other suitable metal deposition process form weld pad 201 in welding pad opening, as an example, weld pad 211 can be convex block
Lower metallization (UBM) structure, can be one or more layers Ti, TiW, NiV, Cr, CrCu, Al, Cu, Sn, Ni, Au, Ag or its
Its conductive material appropriate.As an example, under-bump metallization (UBM) structure can by adhesion layer, barrier layer and seed or
The multiple layer metal of wetting layer stacks.UBM structures help to prevent the integrated circuit of soldered ball and multi-chip semiconductor device it
Between diffusion, while provide low-resistance electrical connection.
In one example, soldered ball 212 is provided, soldered ball 212 is positioned on weld pad 211.
The soldered ball 212 to match with weld pad will be chosen, correspondence is positioned on weld pad 211, this process is known as planting ball, plants
The method of ball can be implant ball or plant ball device plant ball, preferably plant ball device and plant ball, above procedure is the prior art, herein
It does not repeat.It is noted that the present invention carries out general explaination only by taking soldered ball as an example, so the soldered ball mentioned by here is simultaneously
It is not limited to stringent spherical scolding tin, it may also is that other shapes of scolding tin or metal coupling.
Illustratively, after planting ball, reflow soldering process step is also optionally executed.
Reflow soldering process step is executed, melting soldered ball 212 is so that it is electrically connected with weld pad 211.As an example, reflux
The temperature range of weldering is 200 DEG C~260 DEG C.
Then, step 7 is executed, filter is formed in the mesh openings of the network, so that filter is inlayed
In the mesh openings;Several lenticules are formed on the surface of the filter.
Specifically, as shown in figure 2i, filter 213 is formed in the mesh openings of the network, so that filter
Look mirror 213 is embedded in the mesh openings, and adjacent filter 213 is connected, in the surface shape of the filter 213
At several lenticules 214, gap is not present between contiguous microlens 214.
Filter refers to a kind of optical filtering for only allowing the light of particular color ingredient to pass through.Usually it is arranged in the form of an array
Above light receiving unit, color filter array includes red, green, blue filter (primary filter) or the blueness, (compensation of purple and yellow filter
Filter), these filter arrange to correspond to the pixel of light receiving unit respectively, to obtain color information.
Lenticule is usually arranged in array formation above filter, and microlens array refers to " multiple lenticules, Mei Gejun
It with hemispherical, is arranged in above photoelectric conversion device in two-dimensional space, to increase the photoelectric conversion element entered as pixel
The light quantity of the photodiode of part ".
Wherein, any suitable side well known to those skilled in the art can be used by forming filter and the method for lenticule
Method is not done repeat one by one herein.
So far the introduction for completing the committed step of the manufacturing method of the semiconductor devices to the present invention, for complete device
The step of preparation of part also needs to other, this will not be repeated here.
In conclusion the manufacturing method of the present invention, can be realized network using less dry etch process step
And the making of the elements such as conductive layer, etching plasma damage can be effectively reduced, in addition, being used for while forming grid
(conductive layer includes the through-hole being electrically connected with metal interconnecting layer and the electrical connection back of the body to the conductive layer being electrically connected with subsequent weld pad
The outer back conductive layer of portion's through-hole and weld pad), process costs, and the system of the present invention can be greatly reduced with simplification of flowsheet
It makes overlying regions of the method between adjacent photodiode and forms network, the setting of network can effectively improve
The improvement spectrum and optical crosstalk of device, improve the performance of device.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (14)
1. a kind of manufacturing method of semiconductor devices, which is characterized in that the method includes:
Device wafers are provided, the device wafers include:Inbuilt several photodiode regions;Metal interconnecting layer;The photoelectricity
The first groove on the outside of diode region, metal interconnecting layer described in the bottom exposed portion of first groove;
Patterned mask layer is formed in the device wafers, and the first opening is formed in the mask layer and is formed with dew
Go out the second opening of the pad zone on the outside of first groove and first groove, the quantity of first opening is several
It is a and be spaced setting;
It is formed in the bottom and side wall of the bottom of first opening, the bottom of second opening and first groove
The conductive material layer on conductive material layer, second open bottom and first bottom portion of groove and side wall for institute
State the conductive layer of metal interconnecting layer electrical connection;
Remove the mask layer so that part of the conductive material layer in addition to the conductive layer forms network, described
Network is formed with mesh openings in the position of the correspondence mask layer.
2. manufacturing method as described in claim 1, which is characterized in that the top dimension of first opening is less than the ruler of bottom
Very little, the top dimension of second opening is less than the size of bottom.
3. manufacturing method as described in claim 1, which is characterized in that the photodiode region, the mesh openings are in institute
The projection stated on the thickness direction of device wafers overlaps, and corresponds.
4. manufacturing method as described in claim 1, which is characterized in that after forming the photodiode, forming institute
Further include that reduction processing is carried out to the predetermined surface for forming first groove of the device wafers before stating the first groove
Step.
5. manufacturing method as described in claim 1, which is characterized in that the device wafers include:
Device substrate, the photodiode region are located in the device substrate;
Interlayer dielectric layer in the device substrate, the metal interconnecting layer are located in the interlayer dielectric layer, the layer
Between dielectric layer and first groove be separately positioned on the opposite surface of the device substrate;
Insulating layer in the device substrate and photodiode region, first groove sequentially pass through the insulating layer,
The device substrate and the part interlayer dielectric layer.
6. manufacturing method as claimed in claim 5, which is characterized in that first groove includes running through the insulating layer and institute
State device substrate groove and through part described in interlayer dielectric layer via openings, described in the via openings exposed portion
The surface of metal interconnecting layer, the bore of the groove are more than the bore of the via openings.
7. manufacturing method as claimed in claim 6, which is characterized in that formed first groove the step of include:
The first insulating layer is formed in the device substrate, first insulating layer and the interlayer dielectric layer are formed in the device
On the opposite surface of part substrate;
Part first insulating layer and the device substrate being sequentially etched on the outside of the photodiode, until exposed portion
The interlayer dielectric layer, to form the groove;
Second insulating layer is formed in the bottom and side wall of the surface of first insulating layer and the groove;
The part interlayer dielectric layer that exposes from the groove is etched, the table of the metal interconnecting layer described in the exposed portion
Face, to form the via openings.
8. manufacturing method as described in claim 1, which is characterized in that the material of the mask layer includes Other substrate materials.
9. manufacturing method as described in claim 1, which is characterized in that the material of the conductive material layer includes metal material,
The metal material includes at least one of W, Al, Ti, TiN, Ta and TaN.
10. the manufacturing method as described in claim 1 or 8, which is characterized in that wet etching removes the mask layer.
11. manufacturing method as described in claim 1, which is characterized in that further include following step after removing the mask layer
Suddenly:
Coating is formed, to cover the network and the conductive layer;
The part coating in etching removal pad zone, to form the welding pad opening of conductive layer described in exposed portion;
Weld pad is formed on the conductive layer that the welding pad opening exposes;
Soldered ball is formed on the weld pad.
12. manufacturing method as claimed in claim 11, which is characterized in that after forming the soldered ball further include following step
Suddenly:
Filter is formed in the mesh openings of the network, so that filter is embedded in the mesh openings;
Several lenticules are formed on the surface of the filter.
13. manufacturing method as claimed in claim 7, which is characterized in that first insulating layer is described including being sequentially formed at
Nitride layer on the second surface of device substrate and oxide skin(coating).
14. manufacturing method as claimed in claim 5, which is characterized in that further include providing support before forming the first groove
Wafer, the step of the surface of the support wafer and the interlayer dielectric layer is engaged.
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| CN102668080A (en) * | 2009-12-22 | 2012-09-12 | 佳能株式会社 | Solid-state image pickup device and method of producing the same |
| CN102867832A (en) * | 2011-07-07 | 2013-01-09 | 台湾积体电路制造股份有限公司 | Backside illumination sensor having a bonding pad structure and method of making the same |
| CN103681708A (en) * | 2012-09-05 | 2014-03-26 | 台湾积体电路制造股份有限公司 | Multiple metal film stack in BSI chips |
| CN104167430A (en) * | 2014-08-08 | 2014-11-26 | 京东方科技集团股份有限公司 | Organic electroluminescent display (OLED), manufacturing method thereof and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102668080A (en) * | 2009-12-22 | 2012-09-12 | 佳能株式会社 | Solid-state image pickup device and method of producing the same |
| CN102867832A (en) * | 2011-07-07 | 2013-01-09 | 台湾积体电路制造股份有限公司 | Backside illumination sensor having a bonding pad structure and method of making the same |
| CN103681708A (en) * | 2012-09-05 | 2014-03-26 | 台湾积体电路制造股份有限公司 | Multiple metal film stack in BSI chips |
| CN104167430A (en) * | 2014-08-08 | 2014-11-26 | 京东方科技集团股份有限公司 | Organic electroluminescent display (OLED), manufacturing method thereof and display device |
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